Integrated circuit Fabrication Process

The Fabrication process used in manufacturing silicon integrated circuits is discussed here.

1 Introduction: Fabrication process described here applies only to silicon as it is by far the most commonly used semiconductor material, and covers all the stages involved in the fabrication of any microelectronics device. GaAs fabrication process has many parallels with silicon processing but is different in some significant. Semiconductors essential for the fabrication of microelectronic devices because their atomic band structures are such that the addition of small amounts of certain elements (doping) changes the electrical properties of the semiconductor dramatically. Silicon naturally occurs as silicon dioxide in sand, chemically reduced and purified until it is very pure containing typically <1 part per billion (ppb) impurity.

Polysilicon Ingots

Ingot Pulling Silicon is then treated using processes such as float zone so as to produce single crystal ingots typically 8-10" diameter of highly pure or accurately doped silicon.

Silicon Ingots (Mitsubishi)

Single Silicon Ingot

Ingots sawn into thin wafers or substrates which are the starting points of the IC fabrication process

Wafers

Many variants of the basic IC process to produce different types of IC eg. bipolar, CMOS, nMOS, etc. but all essentially follow the stages shown in Figure

2 Epitaxial Growth or Epitaxy: Process whereby very thin layers (1-10m) of accurately controlled doped silicon 'grown' onto the wafer in such a way that the crystal structure is continuous between the substrate and the epitaxial layer. See diagrams for the equipment used for epitaxy.

Epitaxial Reactor 1

Epitaxial Reactor 2

Interior of epitaxial reactor (Mitsubishi)

Epitaxial reactors (Mitsubishi)

3 Photolithography and Etching:

Process which effectively transfers the chip layout on a mask onto the silicon surface - has similarities to photographic printing.

Mask

Photoresist Application (Ontrak)

Stepper (AMS Lithography)

Object is to enable many (millions) of shapes to be printed on the wafer in one operation (enormous cost benefits). Most important process as far as ensuring that the various components line up with each other and are interconnected correctly (determines line width)
Mask (SGS Thomson)

4 Diffusion and Ion Implantation:

bility to change the doping level or type essential in IC fabrication process since parts of the IC have to be doped differently in order that the IC functions correctly. For example, for a high gain BJT, emitter doping>base doping>collector doping. Epitaxy (section 2.2) changes the doping over the whole of the wafer (globally) whereas more often it is required to change the doping over part of the slice (selectively). Photolithography used to form patterns on the wafer surface but cannot, in itself, be used as a mask to prevent dopants reaching the silicon wafer underneath it. This is because both diffusion and ion implantation are high temperature/high energy processes and the chemical elements involved would simply pass through the photoresist. Silicon dioxide which can be easily formed on the surface of the wafer and is very dense and strong, is capable of forming an excellent dopant barrier. Process to selectively dope an area in two steps; firstly photolithography used to define the required pattern in the silicon dioxide layer which is then used in the second step to limit the dopant to the required areas only. Process relies on the ability to accurately remove material such as silicon dioxide defined by photolithography - process known as etching. Originally used acids or solvents of various types (wet etching) but suffered seriously since that removed material in all directions (isotropic) thus removing the masking material also resulting in a change in the pattern dimensions from original layout/mask. This was known as undercutting and affected device line widths and in some cases produced faulty devices.

Acid Etch (Cybor)

Automated Acid Etch

Plasma Asher (Fusion Systems)

Dry etching anisotropic processes developed which only remove material in one direction (normally vertically) overcoming undercutting, giving a faithful representation of the mask pattern on the silicon wafer. 4.1 Diffusion

Diffusion (or solid state diffusion) is the process whereby a solid will physically diffuse itself into another solid in close contact with it due to the random thermal movement of atoms. Essentially zero at room temperatures and up to 300-400C, over long periods at normal operating temperatures. Important in finished devices maintaining their functionality. At high temperatures (>1,000C) diffusion increases considerably. To form a p-type region the element boron is diffused into silicon while the elements arsenic or phosphorus used to form n-type regions. For an n-type wafer placed in a furnace at high temperatures in the presence of a high concentration of boron, the boron will progressively diffuse into the wafer to a depth dependent on the furnace temperature and duration. (Typical depths used are 0.25-2.0m). A p-n junction is then formed in the wafer whose electrical properties are those of a diode and is electrically stable.
4.2 Ion Implantation

Alternative to diffusion which may be used in certain cases. Some diffusion processes are difficult to control accurately in terms of junction depths and doping concentration and in particular, due to the high temperatures involved, the profiles of the dopant fronts are not square but tapered in depth resulting in non-ideal device performance. Ion implantation works in two stages by firing high energy atoms of the relevant elements, say boron, onto the silicon wafer. The ions travel a small distance (typically <1m) into the wafer before losing their energy and being absorbed. Accurate control of the energy of the ions ensures that the absorption depth has a tight tolerance. Second stage is the annealing process at temperatures of about 600C for a short time to repair the mechanical damage caused by the high energy ions and also to cause ions to fit into the silicon crystal lattice substitutionally and hence become electrically active as dopant atoms. Essentially a low temperature process ensuring squarer diffusion profiles and less unwanted diffusions and hence improved device electrical characteristics but much slower throughput than diffusion. High capital investment required.

5 Silicon Dioxide & Other Dielectric Layers

Silicon dioxide and silicon nitride are dielectric materials and are used in IC processing for electrical insulation purposes and for passivation (final covering of all exposed areas of silicon). Silicon dioxide and silicon nitride also used as dopant masks, and as dielectrics in capacitors. Both types of layers easily formed by deposition or by heating the wafer at temperatures up to around 1,000C in the presence of relevant gases. Polycrystalline Silicon (polysilicon) is made up of many small grains of silicon and is not a regular crystal structure as the wafer itself is formed by depositing silicon onto the wafer Used as an interconnect between parts of the chip (highly doped in order to reduce resistance) or for passivation (undoped to increase its resistance).
6 Aluminium & Other Metallisation Layers:

Oxidation Furnace (Thermco Systems)

ICs contain a very large number of transistors and other components formed in the silicon wafer surface. The components have to be interconnected to form a working circuit using a low resistance material (metal) - usually aluminium - that is compatible with the silicon fabrication process (metallisation). Copper also now also used to reduce voltage drops and increase power levels. Polysilicon also used as it offers the ability to form extra layers relatively easily but its resistance is higher than a metal.

Thin Film Deposition (Acatel Corporation)

PVD Sputtering Tool (Sputtered Films Corporation)

Metallisation takes place towards the end of the fabrication process and involves the deposition of a thin layer of aluminium (typically 1m) over the whole of the wafer, (by processes known as aluminium evaporation or sputtering) and then the use of photolithography to define the interconnect pattern. A layer of dielectric over the first level interconnect will allow a further layer of interconnect to be formed and so on (multi-level interconnect). The interconnect on the higher layers are connected to the silicon wafer by cutting contact holes in the insulator or to each other. A typical IC process will use two or three layers of polysilicon and two or three or more layers of aluminium.
7 Packaging & Assembly and Test:

This is covered in more detail in unit 3 but is included here briefly for completness. Before assembly into an IC package starts each die on the finished wafer is electrically tested using a computer driven wafer probe system. Failed die are ink-marked and will not be packaged.

Wire Bonding (Kaijo Corporation)

Wire Bonding (Kulicke & Soffa Industries Incorporated)

Wafer is diced up, faulty chips removed, good chips bonded into appropriate IC packages, interconnect between chip and package formed using thin gold wire, and finally package hermetically sealed. Alternatively package sealed by moulding plastic around the silicon chip.

Die Lead Frame Attachment(Ablestik )