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(Some very basic comments are included in this document, for the benefit of different users levels.) THE CORE <MICROCONTROLLER> SPEED Devices in the PIC18F2455/2550/4455/4550 family incorporate a different oscillator and microcontroller clock system than previous PIC18F devices. The addition of the USB module, with its unique requirements for a stable clock source, make it necessary to provide a separate clock source that is compliant with both USB low-speed and full-speed specifications. The USB module must be clocked from the primary clock source; however, the microcontroller core and other peripherals can be separately clocked from the secondary or internal oscillators. Since a 20MHz xtal setup is used in HSPLL mode, the option is restricted to the PLL Postcaler deriving the microcontroller clock from the PLL (do not confuse it with the Oscillator Postscaler <see figure 2.1 of datasheet>). This allows the USB peripheral and microcontroller to use the same oscillator input and still operate at different clock speeds. So the core speed is defined by the CONFIG1L: CONFIGURATION REGISTER: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) bit 4-3 CPUDIV1:CPUDIV0: System Clock Postscaler Selection bits For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes: 11 = 96 MHz PLL divided by 6 to derive system clock (96MHz/6=16MHz) 10 = 96 MHz PLL divided by 4 to derive system clock (96MHz/4=24MHz) 01 = 96 MHz PLL divided by 3 to derive system clock (96MHz/3=32MHz) 00 = 96 MHz PLL divided by 2 to derive system clock (96MHz/2=48MHz) For any case the Tcy is equal the result divided by 4 (16MHz/4 = 4MHz; 24MHz/4 = 6MHz; 32MHz/4 = 8MHz; 48MHz/4 =12MHz) The selection will be essentially based on the peripherals setup and some other considerations (a PLL divided by 6 to derive system clock is selected for this case, so Tcy= 4MHz) USB CONFIGURATION Prior to communicating over USB, the modules associated internal and/or external hardware must be configured. Most of the configuration is performed with the UCFG register. A USB device not recognized message is mostly caused by an inappropriate hardware and/or software configuration. IMPORTANT NOTE:

The software used here is essentially based on the Assembler version of Jan Axelsons genhid firmware for PIC18F4455. It has been modified for this project. Four files are contained in it: genhid.asm ENGR : SECTION 01 PIC ASSEMBLER MACROS: Created by Bradley A. Minch 9/2004 to facilitate reasonably structured programming in PIC assembler. These macros were inspired and informed both by Karl Lunts PIC macros, described in an atricle in the July 1999 Nuts & Volts magazine, and by Myke Predkos structured programming macros, which are described on pp. 542546 of the second edition of Programming and Customizing PICmicro Microcontrollers. These macros provide facilities for for-next loops, repeat-until loops, select statements, and if statements. 18f2550.lkr

The initial configuration setup is (genhid.asm):

#include <> #include #include

In terms of register values the above configuration means (see datasheet, section 25.1Configuration Bits): CONFIG1L value = 3C CONFIG1H value = 0E CONFIG2L value = 3F CONFIG2H value = 1E CONFIG3H value = 81 CONFIG4L value = A1 CONFIG5L value = 0F CONFIG5H value = C0 CONFIG6L value = 0F CONFIG6H value = E0 CONFIG7L value = 0F CONFIG7H value = 40

For example: CONFIG1L value = 3C (hex) = 0011 1100 (binary) CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)

bit 5 USBDIV=1 = USB clock source comes from the 96 MHz PLL divided by 2: USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) bit 4-3 CPUDIV1:CPUDIV0: System Clock Postscaler Selection bits For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes: 11 = 96 MHz PLL divided by 6 to derive system clock (96MHz/6=16MHz) bit 2-0 PLLDIV2:PLLDIV0= 100 = Divide by 5 (20 MHz oscillator input): PLL Prescaler Selection bits And so much for the other registers. So, for most of the registers it is not necessary to clear or to set the bits, nor even write a value to the register, but instead the appropriate directives are used, except when it is mandatory as in the following case where there is no specific directive found: movlw movwf 0x14 UCFG


bit 7 UTEYE= 0 = Eye pattern test disabled: USB Eye Pattern Test Enable bit bit 6 UOEMON= 0 = UOE signal inactive: USB OE Monitor Enable bit bit 4 UPUEN=1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0): USB On-Chip Pull-up Enable bit bit 3 UTRDIS=0 = On-chip transceiver active: On-Chip Transceiver Disable bit bit 2 FSEN=1 = Full-speed device (pull up, internal <on chip> resistor on D+): controls transceiver edge rates; requires input clock at 48 MHz: Full-Speed Enable bit Or, where it is necessary, to set a bit for a specific reason: bsf UEP0, EPSTALL; set EP0 protocol stall bit to signify Request Error


bit 0 EPSTALL = 1 Endpoint n is stalled (n = 0 <UEP0>): Endpoint Stall Enable bit(1) (EPSTALL of endpoint0 =1) The registers where no configuration is provided remain in the condition immediately after the turning on (.Value at POR).