EXPERIMENT NO 1: CLIPPING CIRCUITS

AIM

To design and test the diode clipping (single or double ended) circuits for the peak clipping
and peak detection.

COMPONENTS / APPARATUS REQUIRED


Sl. No Apparatus Range Quantity
1 AFO 1
2 VRPS Dual Supply 0 30V 1
3 CRO 1
4 Resistors 10K or 1K 1
5 Diode IN4007 2
6 Bread Board 1
7 Connecting Wires


THEORY

Clippers are networks that employ diodes to clip away portions of an input signal
without distorting the remaining part5 of the applied waveform. These clipper circuits
transfer a selected portion of the input waveform to the output diode clipping circuits are
used to prevent a waveform from exceeding some particular limit either negative or positive
or both. This is achieved by connecting the diode in serial or in parallel circuit. Variable DC
voltage is connected in the circuit to achieve required level of clipping. By using different
level DC voltages, it is possible to get different level of clipping in positive and negative side.
These clippers are also called as limiters.

PROCEDURE

1. Place the components on bread board and connect them as per the circuit diagram 1(a).

Use the wires for connection as required.
2. Switch on the signal generator and set voltage to 10V P-P and frequency to 100Hz,

3. Using CRO measure the output wave form and sees that it matches with required wave
form. Vary the DC voltage and tabulate the level of clipping.
4. Connect the input and output wave form to the two channels of the CRO and using XY

mode observe and note down the transfer characteristic.

5. Note down input & output wave form and draw it on graph.

6. Repeat this for other clipping circuits.



































EXPERIMENT NO 2: CLAMPING CIRCUITS



AIM

To design and test the clamping circuits for Positive and Negative clamping.



COMPONENTS / APPARATUS REQUIRED



Sl. No Apparatus Range Quantity
1 AFO 1
2 VRPS Dual Supply 0 30V 1
3 CRO 1
4 Resistors 100K 1
5 Diode IN4007 1
6 Capacitor 0.1F 1
7 Bread Board 1
8 Connecting Wires


THEORY

Clamper is a circuit that clamps a signal to a different dc level without changing the
appearance of the applied signal. The magnitude of R and C must be chosen such that the
time constant RC is large enough to ensure voltage across capacitor does not discharge
significantly during the interval the diode is non-conducting. By connecting suitable Dc
voltage in series with the diode, the level of swing can be varied.


PROCEDURE

1. The Circuits are wired up as shown in the circuit diagrams for each case.

2. A sinusoidal signal of 1KHz and amplitude of 10VP-P is applied as input Vi from

AFO

3. Observe the output waveform on the CRO and verify it with the given waveforms.






















EXPERIMENT NO 3: RECTIFIERS




AIM

To find the efficiency of rectifier and the ripple factor with and without capacitor filter.



COMPONENTS/ APPARATUS REQUIRED



Half wave rectifier without filter
Circuit Diagram & Waveforms

a) Without capacitor filter












Half wave Rectifier with filter
VAC (I/P) VM (O/P) VDC VRMS
RIPPER
FACTOR EFFICNEY




VAC (I/P)
VM
(O/P) VR VDC VRMS RIPPER FACTOR EFFICNEY




Full Wave Rectifier (Center Tapped) without filter






Full Wave Rectifier (Center Tapped) with filter

VAC (I/P) VM (O/P) VDC VRMS
RIPPER
FACTOR EFFICNEY



VAC (I/P)
VM
(O/P) VR VDC VRMS RIPPER FACTOR EFFICNEY




Bridge Rectifier without filter





Bridge Rectifier with filter

VAC (I/P)
VM
(O/P) VR VDC VRMS RIPPER FACTOR EFFICNEY






VAC (I/P) VM (O/P) VDC VRMS
RIPPER
FACTOR EFFICNEY




THEORY:

Half wave rectifier circuit consists of resistive load, a diode and source of ac
voltage, all connected in series. In half wave rectifier, rectifying element conducts
only during positive half cycle of input ac supply. The negative half cycles of ac
supply are eliminated from the output. The dc output waveform is expected to be a
straight line but the half wave rectifier gives output in the form of positive sinusoidal
pulses. Thus the output is called pulsating dc.
The center tapped full wave rectifier circuit is similar to a half wave
rectifier circuit, using two diodes and a center tapped transformer. Both the input
half cycles are converted into unidirectional pulsating DC.

PROCEDURE

1. The connections are made as shown in the circuit diagram.

2. An input is applied to the diode through the secondary of the transformer.

3. The output waveform is observed on the CRO.

4. The amplitude on the CRO, of the output is measured from which and is calculated.

5. Capacitor filter is connected and the amplitude of the output, the ripple voltage is noted down.

Result



Parameters Half Wave Full Wave Bridge
Ripple factor
without filter
Theoretical
Practical
Ripple factor
with filter
Theoretical
Practical
Percentage
Efficiency
Theoretical
Practical




EXPERIMENT NO 4 RESONANCE CHARACTERISTICS
Series resonance & Parallel resonance














Theory:

Series Resonant Circuit:

In a series RLC circuit there becomes a frequency point were the inductive reactance of the
inductor becomes equal in value to the capacitive reactance of the capacitor. The point at which
this occurs is called the Resonant Frequency, (
r
) and as we are analysing a series RLC circuit
this resonance frequency produces a Series Resonance circuit. Series resonance circuits are one
of the most important circuits used electronics. They can be found in various forms in mains AC
filters, and also in radio and television sets producing a very selective tuning circuit for the
receiving the different channels.






Parallel Resonant Circuit:

A parallel circuit containing a resistance, R, an inductance, L and a capacitance, C will produce a parallel resonance
(also called anti-resonance) circuit when the resultant current through the parallel combination is in phase with
the supply voltage. At resonance there will be a large circulating current between the inductor and the capacitor
due to the energy of the oscillations. A parallel resonant circuit stores the circuit energy in the magnetic field of the
inductor and the electric field of the capacitor. This energy is constantly being transferred back and forth between the
inductor and the capacitor which results in zero current and energy being drawn from the supply. This is because the
corresponding instantaneous values of I
L
and I
C
will always be equal and opposite and therefore the current drawn from
the supply is the vector addition of these two currents and the current flowing in I
R
.







Sl. No F in Hz V in Volts Sl. No F in Hz V in Volts
1 100 1 100
2 500 2 500
3 1K 3 1K
4 2K 4 2K
5 3K 5 3K
6 5K 6 5K
7 5.1K 7 5.1K
8 5.2K 8 5.2K
9 5.3K 9 5.3K
10 5.4K 10 5.4K
11 5.5K 11 5.5K
12 6K 12 6K
13 7K 13 7K
14 8K 14 8K
15 10K 15 10K




EXPERIMENT NO 6 RC-COUPLED AMPLIFIER

Aim: - To design and verify a RC coupled amplifier for the following specifications.
Av=-50, fL = 100Hz, Let VCE 2 = 5V, IC2 =2mA, VCC = 10V.


Theory:
1. Explain the RC Coupled amplifier operation. Give the equations and ideal values for different
parameters of a RC Coupled amplifier.
2. Give the design details for the RC Coupled amplifier circuit.
3. Explain the frequency response of a RC Coupled amplifier circuit.

Circuit diagram :-




Design:-
Let VCE 2=5V , IC 2=2mA ,VCC =10V. IB=20 A.
We have
4
1
VCC > VE >
10
1
VCC.
1. To find the value of RE:-
Let VE=
10
1
VCC=
10
1
10V=1V.
RE=
E
E
I
V
~
2 C
E
I
V
=
mA
V
2
1
=500O
Use RE = 470O
2. To find the value of RC:-
VCE =VCC-ICRC-IERE
RC =
CQ
E CEQ CC
I
V V V

=
mA 2
1 5 10
= 2 kO.
Use RC = 2.2 kO
3. Calculations of resistor values R1 and R2 :-
We have IR2 10IB
Let IR2 = 10IB
IR2 = 10(20*10
6 _
) = 200 A.
Also VB = VE+VBE = 1 V+0.7V
=1.7V
R2= VB/IR2
= 1.7V/200 A = 8.5 k

O
Use R2 = 10 k

O
R1 = (VCC-VB)/IR2
= (10-1.7)/ 200 A = 41.5 k

O
Use R1= 47 k

O
5. Calculation of load resistance RL:
AV= =
( )
|
|
.
|

\
|
E
L c
I
mV
R R
26
||
Substitute for RC, IE and AV
RL =850 O Use RL =820 O
6.Selection of capacitors, C1, C2, and CE
Selection of C1:
XC1 Zi/10, Where Zi = R1|| R2|| |re
R1=41.5 k

O, R2=8.5 k

O,
re = 26mV/IE ~ 26mV/IC= 12.5O
Substituting these, we have Zi=1.1 k

O
XC1
10
1 . 1 O k
XC1=
1
2
1
C f
L
H
0.11 k

O or C1 14F
Select C1 =15F
Selection of C2:
XC2
10
O
Z
where ZO =RC =2.2 k

O
XC2 =
2
2
1
fC H
C2 7.2F Select C2 =10F
Selection of CE:
XCE
10
E
R

E
fC H 2
1

10
E
R
or 2fCE
E
R
10

CE
E
fR H 2
10
CE 3.38F Select CE= 10F


Frequency Response Graph:

TABULAR COLUMN:
Vi= ------------------------ Volts
Sl No FREQUENCY(Hz) Vo(Volts) GAIN GAIN(db)
AV= VO/Vi =20log( VO/Vi)
1 50
2 100
3 300
4 500
5 750
6 1K
7 5K
8 10K
9 50K
10 100K
11 300K
12 400K
13 500K
14 600K
15 700K
16 800K
17 900K
18 1M
19 1.5M
20 2M

Input Impedance Measurement: Output Impedance Measurement

PROCEDURE:
A].Maximum Signal Handling Capacity(Vinmax):
1. Connect the circuit as shown in ckt fig.
2. The Vcc and Vin are switched on.
3. The voltage Vo is observed on the CRO.
4. The amplitude of the input is varied and the output is observed.
5. For a particular value of input voltage, the output starts clipping.
6. The voltage just before the clipping is noted down. This gives Vinmax.
7. The amplitude of input voltage is reduced.
B] Frequency Response
1. Input voltage less than the Vinmax is applied.
2. The amplitude of the input is kept constant and the frequency is varied from 50 Hz to500kHz.
3. Each time the corresponding amplitude of V0 is noted down.
4. The amplitude is reduced to zero and the supply is switched off.
5. Gain in dB is calculated using the formula, Av =20log (Vo/Vin).
6. Frequency response curve is plotted.
C] Input Impedance:
1. The amplifier circuit is rigged up.
2. The input frequency is kept constant at 1 KHz, the voltage Vin less than Vinmax is
applied.
3. The DRB is connected in series with the input as shown in the figure.
4. The DRB is varied until the output becomes half of the previous value with the same
input voltage as in step 2.
5. The DRB resistance will give the input impedance of the amplifier.
6. The input voltage is reduced and supply is switched off.
D] Output Impedance:
1. The amplifier circuit is rigged up.
2. The input frequency is kept constant at 1 KHz, the voltage Vin less than Vinmax is
applied.
3. The DRB is connected across the output terminals as shown in the figure.
4. The DRB is varied until the output becomes half of the previous value with the same
input voltage as in step 2.
5. The DRB resistance will give the output impedance of the amplifier.
6. The input voltage is reduced and supply is switched off.
RESULT:
Maximum signal handling capacity=
Midband gain of the amplifier=
Bandwidth of the amplifier=
Input impedance=
Output impedance=
















Exp No: 7 RC Phase Shift Oscillator

Aim To design and simulate a RC Phase Shift Oscillator circuit.
Component
Name Description Quantity
Transistor BC107 1
Resistors 47K
2.2K
10K
680
4.7K
1
1
1
1
2
Capacitors 10F
0.01F
1
3
DC Voltage Source 0-30V 1
CRO 20MHz 1




Circuit Diagram

Design of Amplifier Stage
Same as RC Coupled amplifier design
Vo
Vcc
+12V
C4
10uF
C3
0.01uF
C2
0.01uF
C1
0.01uF
RL
5K 90%
R1
4.7K
R4
4.7K
RE
680
R3
10K
R2
47K
RC
2.2K
Q1
BC107
Calculation of resonance frequency and Beta or feedback factor

fig: feedback network for RC oscillator
z KH = = O =

H
=
1.3 f ) equation(3 using then F, 0.01 C and 4.7K R If
) 3 (
RC 6 2
1
f

Procedure 1. Set up the amplifier part of the oscillator and test the dc condition.
Ensure that the transistor is working as an amplifier with the
required gain.
2. Connect the feedback network and observe the sine wave on the
CRO and measure its amplitude and frequency.
3. Observe the waveform at the base and collector of the transistor
simultaneously on the CRO and notice the phase shift.

Result Frequency of Oscillations =_________ KHz
Peak value of the signal=____________V.




Vin
Vo
R R
R
C C
C
Exp No: 8
HARTLEY OSCILLATOR & COLPITTS OSCILLATOR
Aim:
Design and testing for the performance of BJT Hartley Oscillator for RF range
f0 = 100 kHz
Components and Equipments:
Sl. No. Components Details Specification Qty
1. Transistor BC109 1 No

2.

Capacitors
0.1 f, 1000 pf 2 No
47f, 0.0023 f Each 1 No
3. Resistors 18K , 1.8K , 3.9K , 4700
1 K Pot

Each 1 No
4. Inductors 100 H, 1mH, 5mH Each 1 No

DC Supply, CRO with Probe

HARTLEY OSCILLATOR
Circuit Diagram:

Design
(The amplifier design is the same as that of RC coupled amplifier)
Tank circuit or feedback circuit design:-
Hartleys oscillator consists of a tank circuit having one capacitor and 2 inductors.
Given the RF range f0= 100 kHz.For Hartleys oscillator, frequency of oscillation,
f0=
C Leq t 2
1
where Leq = L1+L2
Given f0 =100 kHz. , let Leq= 1mH. C=2.5 nF.


COLPITTS OSCILLATOR
Circuit Diagram:

Design
(The amplifier design is the same as that of RC coupled amplifier)
Tank circuit or feedback circuit design:-
Frequency of oscillation for Colpitts oscillator is
f0=
Ceq L t 2
1
where Ceq =
2 1
2 1
C C
C C
+

Let C1=C2= 0.02F.
Ceq =
6
12
10 ) 04 . 0 (
10 ) 02 . 0 )( 02 . 0 (

=0.01F
We have f0 =100 kHz,
1
Then L =
4
2
f0
2
Ceq
= 1
4
2
(10000) (10
3
)
2
*0.01*10
-6
L = 0.25 mH.
PROCEDURE:
1. Rig up the circuit as shown in circuit diagram.
2. Switch on the power supply.(+Vcc)
3. Adjust potentiometer RL to obtain proper sinusoidal oscillations (CRO).
4. Measure frequency of oscillations and compare with designed values.


RESULT:
Performance of the Hartley oscillator & Colpitts oscillator is tested.
Theoretical frequency f0 = 100 kHz.
Practical frequency f0 = 1/T =_____________kHz.


Exp No: 9 RC COUPLED AMPLIFIER USING FET







TABULAR COLUMN:
Vi= ------------------------ Volts
Sl No FREQUENCY(Hz) Vo(Volts) GAIN GAIN(db)
AV= VO/Vi =20log( VO/Vi)
1 50
2 100
3 300
4 500
5 750
6 1K
7 5K
8 10K
9 50K
10 100K
11 300K
12 400K
13 500K
14 600K
15 700K
16 800K
17 900K
18 1M
19 1.5M
20 2M
PROCEDURE:
A].Maximum Signal Handling Capacity(Vinmax):
1. Connect the circuit as shown in ckt fig.
2. The Vcc and Vin are switched on.
3. The voltage Vo is observed on the CRO.
4. The amplitude of the input is varied and the output is observed.
5. For a particular value of input voltage, the output starts clipping.
6. The voltage just before the clipping is noted down. This gives Vinmax.
7. The amplitude of input voltage is reduced.
B] Frequency Response
1. Input voltage less than the Vinmax is applied.
2. The amplitude of the input is kept constant and the frequency is varied from 50 Hz to500kHz.
3. Each time the corresponding amplitude of V0 is noted down.
4. The amplitude is reduced to zero and the supply is switched off.
5. Gain in dB is calculated using the formula, Av =20log (Vo/Vin).
6. Frequency response curve is plotted.
C] Input Impedance:
1. The amplifier circuit is rigged up.
2. The input frequency is kept constant at 1 KHz, the voltage Vin less than Vinmax is applied.
3. The DRB is connected in series with the input as shown in the figure.
4. The DRB is varied until the output becomes half of the previous value with the same
input voltage as in step 2.
5. The DRB resistance will give the input impedance of the amplifier.
D] Output Impedance:
1. The amplifier circuit is rigged up.
2. The input frequency is kept constant at 1 KHz, the voltage Vin less than Vinmax is applied.
3. The DRB is connected across the output terminals as shown in the figure.
4. The DRB is varied until the output becomes half of the previous value with the same
input voltage as in step 2.
5. The DRB resistance will give the output impedance of the amplifier.
RESULT:
Maximum signal handling capacity=
Midband gain of the amplifier=
Bandwidth of the amplifier=
Input impedance=
Output impedance=



EXPERIMENT N0 10: DARLINGTON EMMITER FOLLOWER



AIM

Design of a BJT Darlington emitter follower and determine the gain, input and output
impedances.


COMPONENTS/ APPARATUS REQUIRED


CIRCUIT DIAGRAM



DESIGN OF BIAS CIRCUIT

Let Vce = 6V, Ieq=10mA (Q point of transistor Q2)
To Find Re
Then Vcc = 2Vce=2 x 6 =12 V
Ie = Ic = 10 mA

VR3 = Vcc - Vce= 12 6 = 6V

Re= VR3 / Ie = 6V / (10 mA) = 0.6K =560 (Choose)

To Find R1,R2
VR2 = Vbe1 + Vbe2 + VR3

= 0.6 + 0.6 + (Ie.Re) = 1.2 + (10x0.6) = 7.2V
Vcc = Vr1 + Vr2 VR1= Vcc VR2 = 12 7.2
R1 = VR1/ (10 (Ib1)) = 4.8 / (10 x 1 A) =
R1=480 K , USE 560K
R2= VR2 / (9 Ib) = 7.2 / (9 x 1 A) =
R2=800K , USE 1
To find Cc

PROCEDURE

1. To find Q-point: Connect the ckt without Ac supply .Set Vcc=12V.Measure the DC voltage
(using CRO/multimeter) at the (VB2), Collector (VC2) emitter (VE2) w.r.t ground. Then
determine VCE2=VC2 VE2, IC2=IE2=VE2 / RE
2. Q point = (Vce2, Ic2)

3. Connect the signal generator and apply a sine wave of peak-to-peak amplitude 1V , 1kHz
from the signal generator and note down the output wave form.
4. Gradually increases the input signal until the output signal get distorted. When this
happens slightly reduce the input signal amplitude such that output is maximum undistorted
signal. Then measure the magnitude of the input and output waveform. Calculate the Voltage
gain.
5. Find the input and output impedance as explained below

6. Connect the bootstrap circuit Rb and Cb between the emitter and base as shown in the
circuit. Repeat the steps 3 to 5
Avm = Vi/Vo

TO MEASURE Zin AND Zo

1. To measure Zin (Input Impedance)


Procedure to find Zin

1. Connect the circuit as shown in figure.

2. Set the DRB to minimum resistance (0), I/P sine wave amplitude to 1V p-p, I/P sine
wave Frequency to 10 KHz.
3. Measure Vo (p-p). Let Vo=Va

4. Increase DRB till Vo=Va/2.the corresponding DRB value gives Zin.



2. To measure Zo (Output Impedance)


PROCEDURE

1. Connect the circuit as shown in figure. Set the DRB to its maximum resistance value, I/P

sine wave Frequency to 10 KHz.

2. Measure Vo p-p, let Vo = Vb

3. Decrease DRB till Vo =Vb/2.

4.The corresponding DRB value gives Zo.


To find the current gain

Ai=Io/Ii= (Vo/Zo)/(Vi/Zin) = (Vo/Vi) * (Zin/Zo)

Current gain Ai Zin / Zo, since (Vo/Vi) = 1




TABULAR COLUMN:
Vi= ------------------------ Volts
Sl No FREQUENCY(Hz) Vo(Volts) GAIN GAIN(db)
AV= VO/Vi =20log( VO/Vi)
1 50
2 100
3 300
4 500
5 750
6 1K
7 5K
8 10K
9 50K
10 100K
11 300K
12 400K
13 500K
14 600K
15 700K
16 800K
17 900K
18 1M
19 1.5M
20 2M



RESULT

Thus the Darlingtons Emitter follower was designed and studied






Ex.No:11 VOLTAGE SERIES FEEDBACK AMPLIFIER USING BJT


AIM:
To design and test a two stage voltage series feedback amplifier using BJT and to determine
gain, frequency response, input and output impedance with and without feedback.
COMPONENTS REQUIRED:

Sl. No. Components Details Specification Qty
1. Transistor SL100 2 Nos.
2. Capacitors 0.47 f 3 Nos
10f 2 Nos
3. Resistors 12K , 2.7K , 2.2K , 560 Each 2 No
4.7 K , 100 Each 1 No
4. Variable Resistor 1K Pot 1 No.

DC Supply, Signal Generator, CRO with Probe



THEORY:

The high gain amplifier is widely used in analog circuit design and will serve as
the step to the next higher level of complex analog systems. The philosophy
behind the high gain amplifier is based on the concept of feedback. In analog
circuits we must be able to precisely define transfer function. A familiar
representation of this concept is illustrated in the block diagram below: xs + xi





A x0



_



xf



Here x ^ voltage or current

A ^ High Gain Amplifier

^ Feedback Network

xs ^ Input signal (source)

xi ^ Input signal to amplifier xf ^
Feedback signal




Frequency Response Graph:

TABULAR COLUMN:
Vi= ------------------------ Volts
Sl No FREQUENCY(Hz) With
Feedback
Without
Feedback
With
Feedback
Without
Feedback
With
Feedback
Without
Feedback
Vo(Volts) AV= VO/Vi GAIN(db)=20log( VO/Vi)
1 50
2 100
3 300
4 500
5 750
6 1K
7 5K
8 10K
9 50K
10 100K
11 300K
12 400K
13 500K
14 600K
15 700K
16 800K
17 900K
18 1M
19 1.5M
20 2M
Input Impedance Measurement: Output Impedance Measurement

PROCEDURE:
A].Maximum Signal Handling Capacity(Vinmax):
1. Connect the circuit as shown in ckt fig.
2. The Vcc and Vin are switched on.
3. The voltage Vo is observed on the CRO.
4. The amplitude of the input is varied and the output is observed.
5. For a particular value of input voltage, the output starts clipping.
6. The voltage just before the clipping is noted down. This gives Vinmax.
7. The amplitude of input voltage is reduced.
B] Frequency Response
1. Input voltage less than the Vinmax is applied.
2. The amplitude of the input is kept constant and the frequency is varied from 50 Hz to500kHz.
3. Each time the corresponding amplitude of V0 is noted down.
4. The amplitude is reduced to zero and the supply is switched off.
5. Gain in dB is calculated using the formula, Av =20log (Vo/Vin).
6. Frequency response curve is plotted.
C] Input Impedance:
1. The amplifier circuit is rigged up.
2. The input frequency is kept constant at 1 KHz, the voltage Vin less than Vinmax is
applied.
3. The DRB is connected in series with the input as shown in the figure.
4. The DRB is varied until the output becomes half of the previous value with the same
input voltage as in step 2.
5. The DRB resistance will give the input impedance of the amplifier.
6. The input voltage is reduced and supply is switched off.
D] Output Impedance:
1. The amplifier circuit is rigged up.
2. The input frequency is kept constant at 1 KHz, the voltage Vin less than Vinmax is
applied.
3. The DRB is connected across the output terminals as shown in the figure.
4. The DRB is varied until the output becomes half of the previous value with the same
input voltage as in step 2.
5. The DRB resistance will give the output impedance of the amplifier.
6. The input voltage is reduced and supply is switched off.
RESULT:
Maximum signal handling capacity=
Midband gain of the amplifier=
Bandwidth of the amplifier=
Input impedance=
Output impedance=