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FEATURES: Mixed language support Supports VHDL-93 and Verilog 2001 Native support for all HardIP blocks PPC, MGT, PCIe, etc. No special license requirements Supports AXI Bus Functional Model (BFM) Multi-Threaded compilation Post-Processing capabilities Tcl scriptable GUI and batch mode simulation run Standalone Waveform viewing capabilities Debug capabilities Waveform tracing, waveform viewing, HDL source debugging Power Analysis and optimization using SAIF Memory Editor for viewing and debugging memory elements Single click re-compile and re-launch of simulation Integrated with ISE Design Suite and PlanAhead application Easy to use - One-click compilation and simulation Hardware Cosimulation capability Offload a design or a portion of the design to hardware Accelerate RTL simulation by up to 50x Xilinx simulation libraries built-in Additional mapping or compilation not required
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Multi-language simulation fuels testbench automation, low-power, metric driven verification, and mixed-signal verification Incisive Enterprise Simulator (IES) provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization. IES is the core engine for lowpower verification working closely with Conformal LP, the digital engine for mixed-signal verification working with Virtuoso simulators, the testbench engine
for simulation acceleration with Xtreme and Palladium, and the RTL engine working with TLM verification solutions. Fuels testbench automation, analysis, and reuse for increased productivity Ensures verification quality by tracking industry-standard coverage metrics, including functional, transactional, low-power, and HDL code, plus automatic data and assertion checking Drives and guides verification with an automatically backannotated and executable verification plan Creates reusable sequences and multi-channel virtual sequences on top of a multilanguage verification environment Configures existing Universal Verification Components (UVCs) or quickly constructs all-new UVCs Enables advanced debug using SimVision for transaction-level models, SystemVerilog/e class libraries, transient mixed-signal, low-power, and traditional waveform analysis Supports e, Open Verification Library (OVL), OVM class library, emerging UVM class library, SystemC, SystemC Verification Library, SystemVerilog, Verilog, VHDL, PSL, SVA, and CPF Delivers the highest possible performance for mixed-language, mixed-signal, and low-power designs, across multiple levels of abstraction, including the ability to hot swap the RTL simulation in/out of thePalladium XP series of accelerators/emulators
7. ALDEC 8. HSPICE :
SPICE is a general-purpose circuit simulation program for nonlinear dc, nonlinear transient, and linear ac analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, lossless and lossy transmission lines (two separate implementations), switches, uniform distributed RC lines, and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFETs. The SPICE3 version is based directly on SPICE 2G.6. While SPICE3 is being developed to include new features, it continues to support those capabilities and models which remain in extensive use in theSPICE2 program. SPICE has built-in models for the semiconductor devices, and the user need specify only the pertinent model parameter values.
GATE LEVEL SIMULATORS: 1. MENTOR GRAPHICS SIMULATOR TOOLS FOR ASIC DESIGN 2. BSIM3 and BSIM4, FILETYPE - SPICE .mode, Bipolar simulation models for nmos and pmos level=9 and level=14 for spice3f5 and spice3e2 3. SYNOPSYS 4. EXPRESSO 5. FUNCTIONAL FAULT SIMULATION OF VHDL GATE LEVEL
A gate level circuit is modified to include logic gates where faults are to be injected. Values assigned to the inputs of the new additions of the circuit have the effect of injecting stuck-at faults at various lines of the original circuit. A functional model is obtained to represent the new altered circuit. This faultable model can be simulated using a standard VHDL simulator. THE SWITCH-LEVEL SIMULATION
FEATURES
Simultaneous display of analog and logic simulation results in an interactive waveform viewer both interactively during the analysis runtime and in postprocessing Easy setup of trade-off between speed and accuracy plus added-value features for design bug detection and eradication IEEE model encryption for source code protection in order to exchange data safely Simulation results calibrated against Silicon measurements Required flexibility to model the IC with its application schematics of reference, per the Application Hardware Modeling (AHM) approach, to optimize system performance as early as possible in the design cycle and before the prototyping stage Interoperability
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Compatibility with frameworks and complementary solutions (HSPICE, ModelSim, PSpice) to add new modeling and simulation capabilities to an existing design flow SMASH integrated as Laysim in Laytools suite from TexEDA Schematic-driven Layout between SLED and DW2000 from Design Workshop Technologies