AL460 Full HD FIFO Memory Datasheet

Version 1.0

2007~2009 by AverLogic Technologies, Corp.

INFORMATION FURNISHED BY AVERLOGIC IS BELIEVED TO BE ACCURATE AND RELIABLE. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY AVERLOGIC FOR ITS U SE , N O R F O R AN Y IN F R IN GE ME NTS OF PATE NTS OR O THE R RI GHT S OF T HIRD PARTIES THAT MAY RESULT FROM ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF AVERLOGIC.

Doc Number: 1-D-PMK262-0001

AL460 Full HD FIFO

Amendments
Revise Date Contents Page

08.07.01 09.06.04 09.08.06

Preliminary version 0.01 Revised Reference design schematic: XIN = 14.31818 MHz; CSEL[1:0] = VDD33 Revised Pin definitions: Pin 98 = ROINV; Pin 99 =ROEN.

Disclaimer
THE CONTENTS OF THIS DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE. AVERLOGIC TECHNOLOGIES RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. AVERLOGIC DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. CUSTOMERS ARE ADVISED TO CONSULT WITH AVERLOGIC OR ITS COMMERCIAL DISTRIBUTORS BEFORE ORDERING.

2007~2009 Copyright by AverLogic Technologies, Corp.

Version 1.0

AL460 Full HD FIFO

Table of Contents
1 2 3 4 5 6 GENERAL DESCRIPTION__________________________________________________ 4 FEATURES _______________________________________________________________ 4 APPLICATIONS ___________________________________________________________ 5 FUNCTION BLOCK DIAGRAM _____________________________________________ 5 ORDERING INFORMATION________________________________________________ 6 PIN DIAGRAM ____________________________________________________________ 6
6.1 6.2 Pin Description ____________________________________________________________________ 6 Pin Diagram ______________________________________________________________________ 9 Absolute Maximum Ratings under Free-Air Temperature _________________________ 10 Recommended Operating Conditions _____________________________________________ 10 DC Characteristics _______________________________________________________________ 10 AC Characteristics _______________________________________________________________ 11 Timing Diagrams_________________________________________________________________ 13 Power-On-Reset & Initialization __________________________________________________ 20 WRST, RRST Reset Operation ____________________________________________________ 21 Control Signals Polarity Select ___________________________________________________ 21 FIFO Write Operation ____________________________________________________________ 21 FIFO Read Operation_____________________________________________________________ 22 One Field Delay Line (The Old Data Read)________________________________________ 23 Two Frame Mode_________________________________________________________________ 24 14x14x1.4mm 128-Pin LQFP Package _________________________________________ 27 The AL460 Reference Schematic _______________________________________________ 29 General PCB Design Guideline _________________________________________________ 30

ELECTRICAL CHARACTERISTICS ________________________________________ 10

7.1 7.2 7.3 7.4 7.5

FUNCTION DESCRIPTION _______________________________________________ 20

8.1 8.2 8.3 8.4 8.5

APPLICATION NOTE _____________________________________________________ 23

9.1 9.2 10.1 11.1 11.2

10 Mechanical Drawing 128-PIN LQFP ____________________________________ 27 11 DESIGN NOTES _________________________________________________________ 29

2007~2009 Copyright by AverLogic Technologies, Corp.

Version 1.0

AL460 Full HD FIFO

1 GENERAL DESCRIPTION
The AL460 consists of 128-Mbits of memory density and can be configured as an 8M x 16-bit FIFO (first in first out) at maximum R/W operating speed of 150 MHz. The full HD FIFO can be used in a wide range of applications such as multimedia, video capture systems and many other varieties of video data buffering applications. The size and high-speed data access allow full HD video frame capture up to 1080p resolutions. The AverLogic AL460 FIFO memory provides completely independent input and output ports. The built-in address and pointer control circuits provide a straightforward bus interface to sequentially read/write memory that can reduce inter-chip design efforts. The AL460 uses high performance process technologies with extended controller functions (write mask, read skip etc.); it allows easy operation of non-linearity FIFO read/write for use in broadcasting systems, security systems, cameras and many other applications. The AL460 is designed and manufactured using state-of-the-art technologies with low power consumption AC characteristics (2.5V & 3.3V power supply) facilitating high performance and high quality applications. The chip is available in LQFP 128-pin with exposed die pad package; the small footprint allows product designers to keep board real estate to a minimum.

2 FEATURES
128-Mbit density, 8M x 16-bit configuration Supports video NTSC, PAL and HDTV up to 1080p resolution Independent 16-bit read/write operations (different I/O data rates acceptable) at a maximum speed of 150 MHz High speed synchronous sequential access Input/Output enable control Polarity Selectable 2.5V& 3.3V power supply Standard 128-pin LQFP with exposed die pad package

2007~2009 Copyright by AverLogic Technologies, Corp.

Version 1.0

AL460 Full HD FIFO

3 APPLICATIONS
HD video capture and editing systems Switcher or format converter boxes Video capture or editing systems Video data buffering for security systems Scan rate converters TBC (Time Base Correction) systems Frame synchronizers Digital video cameras Hard disk cache memory Buffer for communication systems 1080p video data stream buffering

4 FUNCTION BLOCK DIAGRAM

The internal structure of each AL460 consists of Input/Output buffers, Write Data Registers, Read Data Registers and main 8M x 16-bit memory cell array and state-of-the-art logic design that takes care of addressing and controlling the read/write data.

2007~2009 Copyright by AverLogic Technologies, Corp.

Version 1.0

5 ORDERING INFORMATION
Part number AL460A-7-PBF AL460A-13-PBF Speed Grade 150 MHz 75 MHz Package LQFP-128 LQFP-128 Power Supply +2.5V & +3.3 V +2.5V & +3.3 V Status 2009 2009

Note: AverLogic Technologies PB-free products employ special PB-free material sets; molding compounds/die that attach materials and 100% matte tin plate termination finish do not use materials containing PBB, PBDE or red phosphorus for green-product chips. AverLogic's PB-free products are MSL classified at PB-free peak reflow temperatures that meet or exceed the PB-free requirements of IPC/JEDEC J Std-020C."

6 PIN DIAGRAM
6.1 Pin Description

Write Bus Signals

Pin name Pin number I/O type Description

DI[15:0]

WEN IE

58, 56~51, 49~46, 44~41, 39 37 36

16-bit data inputs; synchronized with the WCLK clock. Data is acquired at the rising edge of WCLK clock. WEN is the write enable signal that controls the 16-bit input data write and write pointer operation IE is the data input enable signal that controls the enabling/ disabling of the 16-bit data input pins. The internal write address pointer is always incremented at the rising edge of WCLK by enabling WEN regardless of the IE level. WCLK is the write clock input pin. The write data input is synchronized with this clock. The WRST is the write rest signal that resets the write address pointer to 0. Write Frame select pin in Two Frame Mode (TFEN = H): 0: Frame 0 1: Frame 1

I I

WCLK WRST WFSEL

38 35 34

I I I

*Note: For the polarity definition of all write control signals (WEN, IE and WRST), please refer to the PLRTY pin definition and Memory Operation section for details.

Read Bus Signals

Pin name DO[15:0] Pin number 102, 104~107, 109~111, 113~115, 117~120, 122 125 126 I/O Description type O 16-bit data outputs; synchronized with the RCLK clock. Data is output at the rising edge of the RCLK clock.

REN OE

I I

RCLK RCLKO ROEN ROINV RRST RFSEL

124 123 99 98 127 128

I O I I I I

REN is the read enable signal that controls the 16-bit output data read and read pointer operation. OE is the data input enable signal that controls the enabling/ disabling of the 16-bit data output pins. The internal read address pointer is always incremented at the rising edge of RCLK by enabling REN regardless of the OE level. RCLK is the read clock input pin. The read data output is synchronized with this clock. RCLK loop-out clock ROEN is the enable signal for RCLKO output clock RCLK loop-out clock inverts control signal The RRST is the read reset signal that resets the read address pointer to 0. Read Frame select pin in Two Frame Mode (TFEN = H): 0: Frame 0 1: Frame 1

*Note: For the polarity definition of all read control signals (REN, OE, RRST,), please refer to PLRTY pin definition and Memory Operation section for details. The active states for the loop-out read clock control signals, ROEN and ROINV are also determined by PLRTY pin definitions: active High when PLRTY is GND, active Low when PLRTY is VDD.

Power/Ground Signals
Pin name VD25M Pin number 3, 5, 7, 11, 13, 17, 19, 21, 76, 78, 80, 84, 86, 90, 92, 94 9, 15, 23, 50, 74, 82, 88, 112 70 71 40, 57, 103, 121 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 45, 59~63, 73, 75, 77, 79, 81, 83, 85, 87, I/O Description type 2.5V 5% power supply for internal memory 2.5V 5% power supply for internal control logic 2.5V 5% power supply for internal PLL PLL GND 3.3V 10% I/O power supply GND

VD25 PLL25 PLLGND VD33 GND

89, 91, 93, 95, 97, 100, 101, 108, 116

Miscellaneous Signals
Pin name RSTN PLRTY I/O Description type 32 I Global reset (active Low) 33 I Select active polarity of the control signals including WEN, REN, WRST, RRST, IE, OE, ROEN and ROINV (total of 8 signals) PLRTY = VD33, active low. PLRTY = GND, active high. Note: during memory operation, the pin must be permanently connected to VD33 or GND. If PLRTY level is changed during memory operation, memory data is not guaranteed. 67 I Crystal input 68 O Crystal output 65, 66 I Crystal input frequency select pins 00 - 11.059200 MHz 01 - 20.000000 MHz 10 - 24.576000 MHz 11 14.318180 MHz * Minimum crystal frequency accuracy: 100 ppm 72 AI Reference voltage input * Please refer to External decoupling circuit application note for details 25 AI Reference voltage input 2 * Please refer to External decoupling circuit application note for details 96 I Two frame mode enable: 0 Standard FIFO Mode 1 Two Frame Mode 1 I Test pin (pull-down for normal operation) 2 I Scan mode Enable (pull-down for normal operation) 26~31, 64, 69 - No connect Pin number

XIN XOUT CSEL[1:0]

VREF

VREF2

TFEN

TEST SCAN NC

6.2

Pin Diagram

7 ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings under Free-Air Temperature

(Excessive ratings are harmful to the lifetime of the product. These are guidelines that are not yet tested.)

Parameter VD33 VD25M VD25 PLL25 VP IO TAMB Tstg 7.2 3.3V I/O Supply Voltage 2.5V Memory Voltage 2.5V Core Voltage 2.5V PLL Voltage Pin Voltage Output Current Ambient Op. Temperature Storage temperature

Rating -0.3 ~ +4.5 -0.3 ~ +3.4 -0.3 ~ +3.4 -0.3 ~ +3.4 -0.3 ~ +(VD33 + 0.3) -20 ~ +20 0 ~ +70 -40 ~ +125

Unit V V V V V mA C C

Recommended Operating Conditions

Parameter VD33 VD25M VD25 PLL25 VIH VIL 7.3 3.3V I/O Supply Voltage 2.5V Memory Voltage 2.5V Core Voltage 2.5V PLL Voltage High Level Input Voltage Low Level Input Voltage

Min 3.0 2.37 2.37 2.37 0.7VD33 0

Typ 3.3 2.5 2.5 2.5 -

Max 3.6 2.63 2.63 2.63 VD33 0.3VD33

Unit V V V V V V

DC Characteristics (VD33 = 3.3V, VD25M = VD25 = PLL25 = 2.5V; TAMB = 0 to 70C) Parameter IDD33 IDD25 IDD25M Operating Current Operating Current Operating Current Min Typ 100 185 78 Max Unit mA mA mA

* Operating condition: WCLK = RCLK = 150 MHz; Data toggle rate = 20 MHz IDD33 IDD25 IDD25M ISB33 ISB25 ISB25M VOH VOL ILI ILO RL 7.4 Operating Current Operating Current Operating Current Standby Current Standby Current Standby Current Hi-level Output Voltage Lo-level Output Voltage Input Leakage Current (No pull-up or pull-down) Output Leakage Current (No pull-up or pull-down) Input Pull-up/Pull-down Resistance -10 -10 60 VD33-0.4 0.4 +10 +10 TBA TBA TBA 4 80 25 mA mA mA mA mA mA V V A A K

* Operating condition: WCLK = RCLK = 75 MHz; Data toggle rate = 20 MHz

* Standby condition: WCLK = RCLK = 0 MHz

AC Characteristics
(VDD = 3.3V, Vss=0V, TAMB = 0 to 70C)

Parameter TWC TWPH TWPL TRC TRPH TRPL TAC TOH THZ TLZ TWRS TWRH WCLK Cycle Time WCLK High Pulse Width WCLK Low Pulse Width RCLK Cycle Time RCLK High Pulse Width RCLK Low Pulse Width Access Time Output Hold Time Output High-Z Setup Time Output Low-Z Setup Time WRST Setup Time WRST Hold Time

150 MHZ Min 6.6 2.6 2.6 6.6 2.6 2.6 3.0 Max 8.0

75 MHz (TBA) Min Max

Unit ns ns ns ns ns ns ns ns ns ns ns

0.5 2.5

ns ns

TRRS TRRH TDS TDH TWES TWEH TWPW TRES TREH TRPW TIES TIEH TIPW TOES TOEH TOPW TTR CI CO

RRST Setup Time RRST Hold Time Input Data Setup Time Input Data Hold Time WEN Setup Time WEN Hold Time WEN Pulse Width REN Setup Time REN Hold Time REN Pulse Width IE Setup Time IE Hold Time IE Pulse Width OE Setup Time OE Hold Time OE Pulse Width Transition Time Input Capacitance Output Capacitance

0.5 2.5 0.5 2.5 0.5 2.5 3.0 0.5 2.5 3.0 0.5 2.5 3.0 0.5 2.5 3.0

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: The read address needs to be at least 1,536 cycles after write address to guarantee new data read.

7.5

Timing Diagrams

cycle n

Reset cycle (s)

cycle 0

cycle 1

WCLK
T TR T WRS T WRH

WRST

T DS

T DH

DI15~0

n-1

/PLRTY=VDD

, WEN= "L"

, IE= "L"

Write Cycle Timing (Write Reset)

cycle n T WPL

cycle n+1

Disable cycle (s)

cycle n+2

WCLK
T WPH T WC T WES T WEH

WEN
T WPW T DS T DH

DI15~0

n-1

n+1

n+2

/PLRTY=VDD ,IE="L"

,WRST="H" Write Cycle Timing (Write Enable)

cycle n T WPL

cycle n+1

Disable cycle (s)

cycle 0

cycle 1

WCLK
T W PH

TWC

T WRS

T W RH

WRST

T W ES

T W EH

W EN
T W PW T DS T DH

DI15~0

n-1

n+1

/PLRTY=VDD

,IE="L" W rite Cycle Timing (W EN, W RST)

cycle n T RPL

Reset cycle (s)

cycle 0

cycle 1

RCLK
T RPH

T RRS

T RRH

RRST
T AC T OH

DO15~0

n-1

/PLRTY=VDD

,REN= "L" ,OE= "L" Read Cycle Timing (Read Reset)

cycle n T RPL

cycle n+1

Disable cycle (s)

cycle n+2

RCLK
T RPH T RC T RES T REH

REN
T RPW T AC T OH

DO15~0

n-1

n+1

n+2

/PLRTY=VDD ,OE="L"

,RRST="H" Read Cycle Timing (Read Enable)

cycle n T RPL

cycle n+1

Disable cycle (s)

cycle 0

RCLK
T RPH T RC T RRS T RRH

RRST

T RES

T REH

REN
T RPW T AC T OH

DO15~0

n-1

n+1

/PLRTY=VDD

,OE="L" Read Cycle Timing (REN, RRST)

cycle n

Reset cycle (s)

cycle 0

cycle 1

WCLK
T TR T WRS T WRH

WRST

T DS

T DH

DI15~0

n-1

/PLRTY=GND, WEN= "H",

IE= "H"

Write Cycle Timing (Write Reset)

cycle n T RPL

cycle n+1

cycle n+2

cycle n+3

cycle n+4

RCLK
T RPH T RC T OES T OEH

OE
T OPW T AC T OH T HZ Hi-Z T LZ

DO15~0

n-1

n+1

n+4

/PLRTY=VDD

,REN="L" ,RRST="H" Read Cycle Timing (Output Enable)

cycle n T WPL

cycle n+1

Disable cycle (s)

cycle n+2

WCLK
T WPH T WC T WES T WEH

WEN
T WPW T DS T DH

DI15~0

n-1

n+1

n+2

/PLRTY=GND,

IE="H",

WRST="L" Write Cycle Timing (Write Enable)

cycle n T W PL

cycle n+1

D isable cycle (s)

cycle 0

cycle 1

W CLK
T W PH

TWC

T W RS

T W RH

W RST

T W ES

T W EH

W EN
T W PW T DS T DH

D I15~0

n-1

n+1

/PLRTY =G N D , IE="H " W rite C ycle Tim ing (W E, W R ST)

cycle n T WPL

cycle n+1

cycle n+2

cycle n+3

cycle n+4

WCLK
T WPH T WC T IES T IEH

IE
T IPW

T IH

DI15~0

n-1

n+1

n+4

/PLRTY=GND,

WEN="H",

WRST="L"

Write Cycle Timing (Input Enable)

cycle n T RPL

Reset cycle (s)

cycle 0

cycle 1

RCLK
T RPH

T RRS

T RRH

RRST
T AC T OH

DO15~0

n-1

/PLRTY=GND,

REN= "H", OE= "H" Read Cycle Timing (Read Reset)

cycle n T RPL

cycle n+1

Disable cycle (s)

cycle 0

RCLK
T RPH T RC T RRS T RRH

RRST

T RES

T REH

REN
T RPW T AC T OH

DO15~0

n-1

n+1

/PLRTY=GND, OE="H" Read Cycle Timing (REN, RRST)

cycle n T RPL

cycle n+1

cycle n+2

cycle n+3

cycle n+4

RCLK
T RPH T RC T OES T OEH

OE
T OPW T AC T OH T HZ Hi-Z T LZ

DO15~0

n-1

n+1

n+4

/PLRTY=GND, REN="H",

RRST="L" Read Cycle Timing (Output Enable)

8 FUNCTION DESCRIPTION
8.1 Power-On-Reset & Initialization During system power-up, a power-on-reset is required for successful initialization of FIFO internal logic. After deactivation of its reset state, wait for Tdelay_min (2 ms) before applying any operations to ensure the FIFO is in the normal operating state. Apply a valid reset pulse of WRST and RRST after power-on-reset to guarantee Read/Write operations start at a known address (address point at zero). The following diagrams illustrate global reset and R/W reset timings at power-up with polarity equals VDD and GND

8.2 WRST, RRST Reset Operation The reset signal can be given at any time regardless of the WEN, REN and OE status. However, they still need to meet the setup time and hold time requirements with reference to the clock input. When the reset signal is provided during disabled cycles, the reset operation is not executed until cycles are enabled again. 8.3 Control Signals Polarity Select The AL460 provides the option for operating polarity on controlling signals. With this feature the application design can benefit by matching up the operation polarity between the AL460 and an existing interfacing device without additional glue logic. The operating polarity of control signals WEN, REN, WRST, RRST, IE and OE are controlled by the PLRTY signal. When PLRTY is pulled high, all 6 signals will be active low. When PLRTY is pulled low, all 6 signals will be active high. 8.4 FIFO Write Operation In the FIFO write operation, 16 bits of write data are input in synchronization with the WCLK clock. The FIFO write operation is determined by WRST, WEN, IE and WCLK signals and the combination of these signals can produce different write results. The PLRTY signal determines the activated polarity of these control signals. The following tables describe the WRITE functions under different operating polarities.

PLRTY = VDD
WRST L H H WEN L L IE L H WCLK Function Write reset. The write pointer is reset to zero. Normal Write operation. Write address pointer increases, but no new data will be written to memory. Old data is retained in memory. (Write mask function) Write operation stopped. Write address pointer is also stopped.

PLRTY = GND
WRST H L L WEN H H IE H L WCLK Function Write reset. The write pointer is reset to zero. Normal Write operation. Write address pointer increases, but no new data will be written to memory. Old data is retained in memory. (Write mask function) Write operation stopped. Write address pointer is also stopped.

8.5

FIFO Read Operation

In the FIFO read operation, 16 bits of read data are available in synchronization with the RCLK clock. The access time is stipulated from the rising edge of the RCLK clock. To ensure a valid data read, a minimum of 1.5 Kbyte data write has to occur before any read operations. The FIFO read operation is determined by RRST, REN, OE and RCLK signals; the combination of these signals could produce varying read results. The PLRTY signal could decide the activated polarity of these control signals. The following tables describe the READ functions under different operating polarities.

PLRTY = VDD
RRST L L L REN L L H OE L H L RCLK Function Read reset. The read pointer is reset to zero. Data in the address 0 is output. Read reset. The read pointer is reset to zero. Output is high impedance. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and data in the address 0 is output after RE goes low. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and output is high impedance after RE goes low.

H H H H

L L H H

L H L H

Normal Read operation. Read address pointer increases. Output is high impedance. (Data skipping function) Read address pointer is stopped. Output data is held. Read operation stopped. Read address pointer is stopped. Output is high impedance.

PLRTY = GND
RRST H H H REN H H L OE H L H RCLK Function Read reset. The read pointer is reset to zero. Data in the address 0 is output. Read reset. The read pointer is reset to zero. Output is high impedance. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and data in the address 0 is output after REN goes low. Read address pointer is stopped. Output data is held. Read address pointer will be reset to zero and output is high impedance after REN goes low. Normal Read operation. Read address pointer increases. Output is high impedance. (Data skipping function) Read address pointer is stopped. Output data is held. Read operation stopped. Read address pointer is stopped. Output is high impedance.

L L L L

H H L L

H L H L

9 APPLICATION NOTE
9.1 One Field Delay Line (The Old Data Read) As the design shown in the diagram, by applying the reset every 1-field cycle (with the common signal for WRST and RRST) and a constant read/write operation (with all WEN, REN, IE and OE tied to active status), 1 field delay line timing is shown in the timing chart below. When the difference

between the write address and the read address is 0 (the read address and the write address are the same), the old field data are read as shown in the timing chart.

Reset AL460 WRST 16-bit Input DI[15:0] IE WEN WCLK RRST DO[15:0] OE REN RCLK Clock 16-bit Output

AL460 1 Field Delay Line Diagram

Field m cycle 0 cycle 1 cycle n cycle 0

Field m + 1 cycle 1

RCLK W CLK

/R R ST /W R ST

D I1[15~0]

tAC

D O 1[15~0] /P L R T Y = V D D

0 D ata of field m

A L 460 1 F ield D elay L ine T im ing D iagram

9.2

Two Frame Mode

Two Frame buffering mechanism enables AL460 to store two complete frames simultaneously. This advantage makes it possible to process two separated frames in parallel for enhancing performance. In standard FIFO mode, the whole memory space is utilized as single block for sequential data R/W. Once Two Frame Mode is enabled (TFEN = VDD), AL460 will be configured into two 4M x 16-bit memory blocks as Frame 0 & Frame 1. Then the user can use these two separated blocks in parallel.

While data in one frame is being read, the other can be written with a new set of data. Read/Write of a desired frame is allocated via R/W frame select pins. The R/W frame selection and control manipulation are illustrated in the following diagrams.

9.3

External Decoupling Circuit

To ensure the proper operation of internal memory, an external decoupling circuit must be implemented.

10 Mechanical Drawing 128-PIN LQFP

10.1 14x14x1.4mm 128-Pin LQFP Package

11 DESIGN NOTES
11.1 The AL460 Reference Schematic
L1 1 CP1 C3 0.1uF D R1 D C4 C5 C6 VDD25_DDR 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VD D 25 0.1uF 0.1uF 0.1uF VD D 25 VD D 25 C8 C9 C11 C12 C13 C15 33pF D CSEL[0] CSEL[1] 14.31818Mhz X1 C16 33pF VDD33 1M 10uF/16V 0.1uF 1 + TWO_FRAME_EN R3 15ohm D R CLKO_INV R CLKO_EN R4 15ohm R5 15ohm DO[15] DO[14] DO[13] DO[12] DO[11] DO[10] DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] RCLK_OUT RCLK REN OE RRST 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RP3 15ohmx4 8 VDD33 7 6 5 RP5 15ohmx4 8 7 6 5 RP7 15ohmx4 VDD25 8 7 6 5 RP9 15ohmx4 8 7 6 5 VDD33 15ohm 15ohm 15ohm 15ohm 15ohm R60 R59 R58 R57 R6 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 T F EN GN D VD 25M GN D VD 25M GN D VD 25M GN D VD 25 GN D VD 25M GN D VD 25M GN D VD 25 GN D VD 25M GN D VD 25M GN D VD 25M GN D VD 25 GN D VR EF PLLGN D PLL25 NC XOU T XIN C SEL[0] C SEL[1] 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 RD_FRAME_SEL R9 15ohm T EST SC AN VD 25M GN D VD 25M GN D VD 25M GN D VD 25 GN D VD 25M GN D VD 25M GN D VD 25 GN D VD 25M GN D VD 25M GN D VD 25M GN D VD 25 GN D VR EF 2 NC NC NC NC NC NC R ST N GND ROINV ROEN GND GND DO[15] VD33 DO[14] DO[13] DO[12] DO[11] GND DO[10] DO[9] DO[8] VD25 DO[7] DO[6] DO[5] GND DO[4] DO[3] DO[2] DO[1] VD33 DO[0] RCLKO RCLK REN OE RRST RFSEL C1 C2 L2 0.1uF 2 BEAD/DIP 2 BEAD/DIP D VDD25 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 D

U2 AL460
128LQFP

NC GND GND GND GND GND DI[15] VD33 DI[14] DI[13] DI[12] DI[11] DI[10] DI[9] VD25 DI[8] DI[7] DI[6] DI[5] GND DI[4] DI[3] DI[2] DI[1] VD33 DI[0] WCLK WEN IE WRST WFSEL PLRTY

VDD33

VDD25

VDD33

RP4 15ohmx4 1 8 2 7 3 6 4 RP6 15ohmx4 5 1 8 2 7 3 6 4 5 RP8 15ohmx4 1 8 2 7 3 6 4 5 RP10 15ohmx4 1 8 2 7 3 6 4 5 RP12 15ohmx4 1 8 2 7 3 6 4 5

DI[15] DI[14] DI[13] DI[12] DI[11] DI[10] DI[9] DI[8] DI[7] DI[6] DI[5] DI[4] DI[3] DI[2] DI[1] DI[0] WCLK WEN IE WRST

R7 15ohm WR_FRAME_SEL R8 15ohm PLRTY

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

VDD33 4.7K VD D 25 VD D 25 VD D 25 R 61 AL460_RSTN C22 C23 C24 0.1uF 0.1uF 0.1uF C26 C28 0.1uF 0.1uF C29 C30 C31 0.1uF 0.1uF 0.1uF C34 0.1uF D D D C33 1nF BEAD 2 + + C35 10uF/16V D D C36 0.1uF C25 C27 C32 C37 0.1uF 0.1uF 0.1uF 0.1uF D D D C7 0.1uF D C10 0.1uF D C14 1 0.1uF D D D L18 BEAD 2 C17 10uF/16V D D C18 0.1uF D C19 0.1uF D C20 0.1uF D C21 0.1uF VDD25_DDR D L17 VDD25 1 TEST SCAN_EN

VDD33

GND

11.2 General PCB Design Guideline The AL460 is available in 128-pin LQFP with thermal exposed die pad package. It has a rectangular metallic terminal exposed on the bottom surface of the package body. The corresponding PCB lands need to be designed to fit well within the PCB assembly process capabilities. The actual manufacturing capability, SMT process, and product specification need to be considered in addition to Averlogics guideline for optimizing PCB design.
PCB Thermal Pad Design

For enhanced thermal, electrical, and board level performance, the exposed pad on the package must be soldered to the PCB using a corresponding thermal pad on the board. The key effort is to guarantee reliable solder joints by matching the land pattern to the AL460 terminal pattern. The package cross section is illustrated in the figure in the Section, Cross Section and Thermal Land Pattern (below). The thermal pad should be the approximate size of the exposed pad on the LQFP E-PAD package; using die pad size as the maximum thermal pad size is recommended, and should be solder mask defined. Land pattern design for lead attachment on the PCB should be the same as the conventional, nonthermally/electrically enhanced packages. To maximize the electrical and thermal performance, connecting thermal pad to inner and/or bottom ground planes of the PCB by vias is required. The thermal vias should connect to the internal ground plane with complete connection around the entire circumference of the plated through hole. The designer should ensure electrical correctness when connecting copper planes to the thermal pad. Vias with diameters with 0.3 mm or less, and 1 mm via spacing are recommended. The number of vias should be application specified and dependent upon power dissipation and electrical conductivity requirements. The thermal and electrical analysis is recommended to determine the minimum number needed. To avoid device failure due to overheating, the heat flow path through the PCB should be unobstructed. Do not place large or high power consumption components on the reverse side of PCB board that overlaps with the AL460A footprint.
Solder Masking Consideration

There are two basic types of solder pads used, Solder Mask defined style (SMD): The copper metal pad is larger than the solder mask opening above this pad. Thus the pad area is defined by the opening in the solder mask.

 Non-Solder mask defined style (NSMD): around each copper metal pad there is solder mask clearance. Dimensions and tolerances of the solder mask clearance have to be specified, such that no overlapping of the solder pad by the solder mask occurs The NSDM pads are recommended over SMD pads due to the tighter tolerance on copper etching compared to solder masking. NSDM also provides a larger copper pad area and allows the solder to anchor to the edges of the copper pads thus providing improved solder joint reliability.
Cross Section and Thermal Land Pattern

Bottom View and Cross Section of E-PAD LQFP-128

Grounding

Analog and digital circuits are separated within the AL460 chip. To minimize system noise and prevent digital system noise from entering the analog portion, a common ground plane for all devices, including the AL460, is recommended. All the connections to the ground plan should have a very short lead. The ground plane should be solid, not cross-hatched.
Power Planes

The analog portion of the AL460 and any associated analog circuitry should have their own power plane, referred to as the analog power plane (PLL25). The analog power plane should be connected to the digital power plane (VDD25) at a single point through a low resistance ferrite bead. The digital power plane should provide power to all digital logic on the PCB board, and the analog power plane should provide power to all of the AL460 analog power pins and relevant analog circuitry. The digital power plane should not be placed under the AL460 chip, the voltage reference or other analog circuitry. Capacitive coupling of digital power supply noise from this layer to the AL460 and its related analog circuitry can degrade signal integrity.

Power Supply Decoupling

Power supply connection pins should be individually decoupled. The decoupling capacitors should be placed as close as possible to the AL460. The ground connection of the capacitor should go straight to the ground plane through a via placed immediately adjacent to the pad. Ideally, the ground connection should be through 2 vias, one placed on either side of the pad. For the best results, use 0.1F ceramic chip capacitors. Lead lengths should be minimized. The power pins should be connected to the bypass capacitors before being connected to the power planes. 22F capacitors should also be used between the AL460 power planes and the ground planes to control low-frequency power ripple.
Digital Signal and Clock Interconnect

Digital signals to the AL460 should be isolated as much as possible from other analog circuitry. These signals should not overlap the analog power plane. If this is not possible, coupling can be minimized by routing the digital signal at a 90 degree angle across the analog signals. The 16-bit digital input bus, DI, should have the same trace length; it also applies to DO, the output digital bus. The high frequency clock reference or crystal should be handled carefully. Jitter and noise on the clock will degrade the data integrity. Keep the clock paths to the AL460 as short as possible to reduce the amount of noise picked up.

CONTACT INFORMATION

Averlogic Technologies Corp. E-mail: sales@averlogic.com.tw URL: http://www.averlogic.com.tw

Averlogic Technologies, Inc. E-mail: sales@averlogic.com URL: http://www.averlogic.com