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A term paper submitted for the partial fulfillment of the course ECE 202

Table of contents: Page No. (From- To)

S. No.

Contents

1.

Introduction of PLDs

2.

Advantages of PLDs

3.

Types of PLDs

4.

Programmable Logic Array

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5.

Programmable Array Logic

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6.

References

1.

INTRODUCTION[1][4]

A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a circuit it must be programmed, that is, reconfigured. PLDs were first introduced in the 1970s. In fixed-function logic circuits (e.g. SSI, MSI, LSI, VLSI & ULSI), a specific logic function is contained in the IC package when it is purchased and it can never be changed. PLDs are another category of logic devices in which the logic function is programmed by the user and in some cases can be reprogrammed many times. The function provided by each of the 7400-series parts is fixed and cannot be tailored to suit a particular design situation. This fact, coupled with the limitation that each chip contains only a few logic gates, makes these chips inefficient for building large logic circuits. It is possible to manufacture chips that contain relatively large amounts of logic circuitry with structure that is not fixed. It is a general purpose chip for implementing logic circuitry & contains a collection of logic circuit elements that can be customized in different ways. A PLD can be viewed as a black box that contains logic gates and programmable switches. The programmable switches allow the logic gates inside the PLD to be connected together to implement whatever logic circuit is needed.

Fig 1.1(CPLD)
2.

ADVANTAGES OF PLDS[1][4]

In many applications the PLD has replaced the hard-wired fixed-function logic devices. However, fixed-function logic is still important and will be around for a long time but in more limited applications. The advantages of PLDs are:
I.

Increased Integration: the package count of the design can be reduced while simultaneously increasing the features offered by the product. Lower Power: CMOS and fewer packages combine to reduce power consumption. Improved Reliability: Lower power plus fewer interconnections and package translate into greatly improved system reliability.

II. III.

IV.

Lower Cost: PLDs reduce the inventory cost too.

V.

Easier to Change: With certain PLDs, logic designs can be readily changed without rewiring of replacing components

VI.

Easier To Use: Generally, a PLD can be implemented faster than one using fixedfunction ICs once the required programming language is mastered.

VII.

Another advantage of PLDs over fixed-function logic devices is that many more logic circuits can be stuffed into a much smaller area with PLDs.

TYPES OF PLDs[1][b]
The three major types of programmable logic are SPLD, CPLD & FPGA. Each major type generally has several manufacturer- specific subcategories.

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SPLDs: Simple programmable logic devices are the least complex form of PLDs. An SPLD can typically replace several fixed-function SSI or MSI devices and their interconnections. The SPLD was the first type of programmable logic available. An SPLD consists of an array of AND gates & OR gates that can be programmed to achieve specified logic functions. A few categories of SPLD are listed below:
a) PAL: Programmable Array Logic. b) PLA: Programmable Logic Array. c) GLA: Generic Array Logic. d) PROM: Programmable read-only memory.

II.

CPLDs: Complex programmable logic devices have a much higher capacity than SPLDs permitting more complex logic circuits to be programmed into them.

Fig 3.1(CPLD)
III.

FPGAs: Field- programmable gate arrays are different from SPLDs & CPLDs in their internal organization and have the greatest logic capacity. FPGAs consist of an array of anywhere from sixty-four thousands of logic-gate groups that are sometimes called logic blocks.

3.

PROGRAMMABLE LOGIC ARRAY[1][2][a][b]

Several types of PLDs are commercially available. The first developed was the Programmable Logic Array (PLA). Based on the idea that logic functions can be realized in sum-of-products, a

PLA comprises a collection of AND gates that feeds a set of OR gates. A programmable logic array (PLA) is a programmable device used to implement combinational logic In digital circuit theory, combinational logic is a type of digital logic which is implemented by Boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the circuits.

Fig 4.1

The general structure of a PLA is depicted in the figure given below:

Fig 4.2 As shown in the figure, the PLAs inputs x1..xn pass through a set of buffers(which provide both the true value and complement of each input) into a circuit block called an AND plane, or AND array. The AND plane produces a set of product terms P1..Pk. Each of these terms can be configured to implement any AND function of x1..xn. The product terms serve as the inputs to an OR plane, which produces the outputs f1.fm. A more detailed diagram of PLA is given below

Fig 4.3

Fig 4.4

The diagram shows a PLA with three inputs, four product terms, and two outputs. Each AND gate in the AND plane has six inputs, corresponding to the true and complemented versions of the three input signals. Each connection to an AND gate is programmable; a signal that is connected to an AND gate is indicated with a wavy line, and a signal that is not connected to the gate is shown with a broken line. The circuit is designed in such a way that any unconnected AND-gate input do not affect the output of the AND gate. The AND gate that produces P1 is shown connected to the inputs x1 & x2. Hence P1=x1. x2. Similarly, P2=x1 .x3, P3= x1.x2.x3 & P4= x1.x3. Programmable connections also exist for the OR plane. Output f1 is connected to the product terms P1, P2, and P3. It therefore realizes the function f1= x1. x2 + x1 .x3 + = x1.x2.x3 . Similarly there is the output for f2. Commercially available PLAs come in much larger sizes. Typical parameters are 16 inputs, 32 product terms, and 8 outputs. The PLA is efficient in terms of the area needed for its implementation on an integrated circuit chip. For this reason, PLAs are often included as part of larger chips, such as microprocessor. EXAMPLE: Given a group of functions. F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A Step 1: Minimize functions Functions already in minimized form. Step 2: Look for common product terms: A B, B C, A C, B C, A

Step 3: PLA table with Shared Product Terms. Product term AB BC AC BC A A 1 1 1 Inputs B 1 0 0 C 1 0 0 F0 0 0 0 1 1 Outputs F1 F2 1 1 0 0 1 0 0 1 0 0 F3 0 1 0 0 1

Step 4: Draw PLA diagram.

Fig 4.4

4.

PROGRAMMABLE ARRAY LOGIC[3][5][a]

In a PLA both the AND & OR planes are programmable. Historically, the programmable switches presented two difficulties for manufactures of these devices: they were hard to fabricate correctly, and they reduced the speed-performance of circuits implemented in the PLAs. These drawbacks led to the development of a similar device in which the AND plane is programmable, but the OR plane is fixed. Such a chip is known as Programmable Array Logic (PAL) device. Because they are simpler to manufacture, and thus less expensive than PLAs, and offer better performance, PALs have become popular in practical applications. Another disadvantage of the PLA was longer delays due to the additional fusible links that result from using two programmable arrays and more circuit complexity. The PAL is the most common one-time programmable (OTP) logic devices and is implemented with bipolar technology (TTL or ECL). The PAL consists of a programmable array of AND gates that connects to a fixed array of OR gates. This structure allows any sum-of-products (SOP) logic expression with a defines number of variables to be implemented. A programmable array is essentially a grid of conductors forming rows and columns with a fusible link at each cross point. Each fused cross point of a row and column is called a cell and is the programmable element of a PAL. Each row is connected to the input of an AND gate & is each column is connected to an input variable or its complement. By using the presence or absence of

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fused connections created by programming, any combination of input variables or complements can be applied to an AND gate to form any desired product term.

Fig 5.1 Fig 5.2[7]

HISTORY Before PALs were introduced, designers of digital logic circuits would use small-scale integration (SSI) components, such as those in the 7400 series TTL (transistor-transistor logic) family; the 7400 family included a variety of

logic building blocks, such as gates (NOT, NAND, NOR, AND, OR), multiplexers (MUXes) and demultiplexers (DEMUXes), flip flops (D-type, JK, etc.) and others. One PAL device would typically replace dozens of such "discrete" logic packages, so the SSI business went into decline as the PAL business took off. PALs were used advantageously in many products, such as minicomputers.

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PALs were not the first commercial programmable logic devices; Signetics had been selling its field programmable logic array (FPLA) since 1975. These devices were completely unfamiliar to most circuit designers and were perceived to be too difficult to use. The FPLA had a relatively slow maximum operating speed (due to having both programmableAND and programmableOR arrays), was expensive, and had a poor reputation for testability. Another factor limiting the acceptance of the FPLA was the large package, a 600-mil (0.6", or 15.24 mm) wide 28-pin dual inline package (DIP).

Fig 5.3[6]

A circuit diagram to show the PAL is shown below:

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5. REFERENCES
WEBSITES

1. http://en.wikipedia.org/wiki /Programmable_logic_device http://en.wikipedia.org/wiki /Programmable_ Logic _Array

2.

http://en.wikipedia.org/wiki /Programmable_Array_Logic
3.

http://cset.sp.utoledo.edu/e et3350/lesson1.html
4.

http://www.absoluteastrono my.com/topics/Programmable_Arr ay_Logic

5.

http://www.fys.uio.no/studi er/kurs/fys4260/fig2-14.jpg
6.

http://nomadicresearchlabs. com/store/images/components/PA L20L8.jpg

7.

a.

BOOKS

Floyd L; Jain R. P. , Digital Fundamentals, Pearson Education, Ed 8, 2008, Page-502 to 510 Bains G.S.;Walia M.S., Digital Circuits and Logic Design, PBS publication, Ed 2,2010, Page269 to 272
b.