M.V.S.R.

ENGINEERING COLLEGE

DESIGN & SIMULATION LAB-II

NOT GATE
Aim: To design, simulate and synthesize NOT gate using Verilog HDL.
Apparatus Required: Cadence tools: Incisive, RTL Compiler (180nm Technology library).
Theory: NOT gate is one of the basic logic gates. The NOT gate consists of one input and
one output. A CMOS NOT gate comprises of a PMOS that is connected to Vdd and a NMOS
connected to ground. When the input is logic 1 then PMOS goes OFF (open circuit) and
NMOS goes ON (short circuit) and the output is connected to ground giving output as logic
0. When the given input is logic 0, PMOS goes ON and NMOS goes OFF thereby
connecting output to Vdd and the output obtained is logic 1.
Code:
module inv(y,a);
input a;
output y;
assign y=~a;
endmodule
Netlist obtained after synthesizing using RTL Compiler:
module inv(y, a);
input a;
output y;
wire a;
wire y;
INVXL g2(.A (a), .Y (y));
endmodule

M.E. (ES & VLSI DESIGN) II-SEM

2451-11-744-010

M.V.S.R. ENGINEERING COLLEGE

DESIGN & SIMULATION LAB-II

Area Report:
Instance
Cells Cell Area Net Area Wireload
------------------------------------------------------------------------inv
1
2
0
<none>
(D)
(D) = wireload is default in technology library

Power Report:
Leakage
Dynamic
Total
Instance
Cells
Power(nW) Power(nW)
Power(nW)
--------------------------------------------------------------------------------------inv
1
4.684
18.689
23.373

Timing Report:
Pin

Type

Fanout
Load Slew Delay Arrival
(fF)
(ps)
(ps) (ps)
----------------------------------------------------------------------------------a
in port
1
1.2
0
+0
0R
g2/A
+0
0
g2/Y INVXL
1
0.0
3
+13
13 F
y
out port
+0
13 F
----------------------------------------------------------------------------------Timing slack : UNCONSTRAINED
Start-point : a
End-point : y

Gates Report:
Gate Instances Area
Library
--------------------------------------INVXL
1 2.117 slow_normal
--------------------------------------total
1 2.117

Type Instances Area Area %

-------------------------------inverter
1 2.117 100.0
-------------------------------total
1 2.117 100.0

Conclusion: The NOT gate has been designed, simulated and synthesized using Cadence
tools (180nm Tech. Library).

M.E. (ES & VLSI DESIGN) II-SEM

2451-11-744-010

M.V.S.R. ENGINEERING COLLEGE

DESIGN & SIMULATION LAB-II

NAND GATE
Aim: To design, simulate and synthesize NAND gate using Verilog HDL.
Apparatus Required: Cadence tools: Incisive, RTL Compiler (180nm Technology library).
Theory: In digital electronics, a NAND gate (Negated AND or NOT AND) is a logic
gate which produces an output that is false only if all its inputs are true. A LOW (0) output
results only if both the inputs to the gate are HIGH (1); if one or both inputs are LOW (0), a
HIGH (1) output results. The NAND gate is significant because any boolean function can be
implemented by using a combination of NAND gates. This property is called functional
completeness.
Code:
module nandgate(y,a,b);
input a,b;
output y;
nand na1(y,a,b);
endmodule
Netlist obtained after synthesizing using RTL Compiler:
module nandgate(y, a, b);
input a, b;
output y;
wire a, b;
wire y;
NAND2XL g1(.A (b), .B (a), .Y (y));
endmodule

M.E. (ES & VLSI DESIGN) II-SEM

2451-11-744-010

M.V.S.R. ENGINEERING COLLEGE

DESIGN & SIMULATION LAB-II

Area Report:
Instance Cells Cell Area Net Area Wireload
---------------------------------------------------nandgate

<none> (D)

(D) = wireload is default in technology library

Power Report:
Leakage
Dynamic
Total
Instance
Cells
Power(nW) Power(nW)
Power(nW)
--------------------------------------------------------------------------------------nandgate
1
4.971
36.760
41.731

Timing Report:
Pin

Type

Fanout
Load Slew Delay Arrival
(fF)
(ps)
(ps) (ps)
----------------------------------------------------------------------------------a
in port
1
1.1
0
+0
0R
g1/B
+0
0
g1/Y NAND2XL
1
0.0
30
+27
27 F
y
out port
+0
27 F
----------------------------------------------------------------------------------Timing slack : UNCONSTRAINED
Start-point : a
End-point : y

Gates Report:
Gate Instances Area
Library
--------------------------------------NAND2XL
1 2.822 slow_normal
----------------------------------------total
1 2.822

Type Instances Area Area %

-------------------------------logic
1 2.822 100.0
----------------------------total
1 2.822 100.0

Conclusion: The NAND gate has been designed, simulated and synthesized using Cadence
tools (180nm Tech. Library).

M.E. (ES & VLSI DESIGN) II-SEM

2451-11-744-010

M.V.S.R. ENGINEERING COLLEGE

DESIGN & SIMULATION LAB-II

FULL ADDER
Aim: To design, simulate and synthesize FULL ADDER using Verilog HDL.
Apparatus Required: Cadence tools: Incisive, RTL Compiler (180nm Technology library).
Theory: A one-bit full adder is a device with three single bit binary inputs (A, B, Cin) and
two single bit binary outputs (Sum, C-out). Having both carry in and carry out capabilities,
the full adder is highly scalable and found in many cascaded circuit implementations. It can
be seen that the full adder can be trivially constructed with two half adders. The full adder
can also be decomposed into the following logical relationships:

Code:
module fulladder(s, co, a, b, c);
input a, b, c;
output s, co;
halfadder ha1(w1, w2, a, b);
halfadder ha2(s, w3, w1, c);
or (co, w3, w2);
endmodule
module halfadder(s, c, a, b);
input a, b;
output s, c;
xor (s, a, b);
and (c, a, b);
endmodule
Netlist obtained after synthesizing using RTL Compiler:
module halfadder(s, c, a, b);
input a, b;
output s, c;
wire a, b;
wire s, c;
ADDHXL g17(.A (b), .B (a), .S (s), .CO (c));
endmodule
module halfadder_1(s, c, a, b);
M.E. (ES & VLSI DESIGN) II-SEM

2451-11-744-010

M.V.S.R. ENGINEERING COLLEGE

DESIGN & SIMULATION LAB-II

input a, b;
output s, c;
wire a, b;
wire s, c;
ADDHXL g17(.A (b), .B (a), .S (s), .CO (c));
endmodule
module fulladder(s, co, a, b, c);
input a, b, c;
output s, co;
wire a, b, c;
wire s, co;
wire w1, w2, w3;
halfadder ha1(w1, w2, a, b);
halfadder_1 ha2(s, w3, w1, c);
OR2XL g2(.A (w3), .B (w2), .Y (co));
Endmodule
Area Report:
Instance
Cells Cell Area
Net Area
Wireload
---------------------------------------------------------------------------------fulladder
3
25
0
<none> (D)
ha2
1
11
0
<none> (D)
ha1
1
11
0
<none> (D)
(D) = wireload is default in technology library

Power Report:
Leakage
Dynamic
Total
Instance
Cells Power(nW) Power(nW) Power(nW)
-----------------------------------------------------------------------------fulladder
3
68.654
440.312
508.966
ha1
1
28.860
170.259
199.119
ha2
1
28.585
171.952
200.537
Timing Report:
Pin

Type

Load Slew Delay Arrival

(fF) (ps) (ps) (ps)
---------------------------------------------------------------------------b
in port
1
1.9
0
+0
0R
ha1/b
M.E. (ES & VLSI DESIGN) II-SEM

Fanout

2451-11-744-010

M.V.S.R. ENGINEERING COLLEGE

DESIGN & SIMULATION LAB-II

g17/A
g17/S
ADDHXL
1
2.3
ha1/s
ha2/a
g17/B
g17/CO
ADDHXL
1
1.1
ha2/c
g2/A
g2/Y
OR2XL
1
0.0
co
out port
-----------------------------------------------------Timing slack : UNCONSTRAINED
Start-point : b
End-point : co

92

+0
0
+131 131 F

41

+0
131
+102 233 F

38

+0
233
+112 345 F
+0
345 F

Gates Report:
Gate Instances Area
Library
----------------------------------------ADDHXL
2 21.168 slow_normal
OR2XL
1 3.528 slow_normal
----------------------------------------total
3 24.696

Type Instances Area Area %

-----------------------------logic
3 24.696 100.0
-----------------------------total
3 24.696 100.0

Conclusion: The NOT gate has been designed, simulated and synthesized using Cadence
tools (180nm Tech. Library).

M.E. (ES & VLSI DESIGN) II-SEM

2451-11-744-010