ABSTRACT:_ A finite state machine (FSM) or simply a state machine, is a model of behavior composed of a finite number of states, transitions

between those states, and actions.It is like a "flow graph" where we can see how the logic runs when certain conditions are met. In this aricle I have implemented a Mealy type state machine in VHDL.The state machine bubble diagram in the below figure shows the operation of a four-state machine that reacts to a single input "input" as well as previous-state conditions. programlibrary ieee;

use IEEE.std_logic_1164.all; entity mealy is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end mealy; architecture behavioral of mealy is type state_type is (s0,s1,s2,s3); --type of state machine. signal current_s,next_s: state_type; --current and next state declaration. begin process (clk,reset) begin if (reset='1') then current_s <= s0; --default state on reset. elsif (rising_edge(clk)) then current_s <= next_s; --state change. end if; end process; --state machine process. process (current_s,input) begin case current_s is when s0 => --when current state is "s0" if(input ='0') then

output next_s else output next_s end if; when s1 if(input output next_s else output next_s end if;

<= '0'; <= s1; <= '1'; <= s2;

=>; --when current state is "s1" ='0') then <= '0'; <= s3; <= '0'; <= s1;

when s2 => --when current state is "s2" if(input ='0') then output <= '1'; next_s <= s2; else output <= '0'; next_s <= s3; end if;

when s3 => if(input output next_s else output next_s end if; end case; end process;

--when current state is "s3" ='0') then <= '1'; <= s3; <= '1'; <= s0;

end behavioral;

Depending upon the input and current state the next state is changed.And at the rising edge of the clock, current state is made equal to next state.A "case" statement is used for jumping between states. The code was synthesised using Xilinx XST and the results are shown below: -------------------------------------------------------States Transitions Inputs Outputs Clock Reset Reset type Reset State Power Up State Encoding Implementation 4 8 1 4 clk (rising_edge) reset (positive) asynchronous s0 s0 Automatic LUT

--------------------------------------------------------Optimizing FSM on signal with Automatic encoding. ------------------State | Encoding ------------------s0 | 00 s1 | 01 s2 | 11 s3 | 10 ------------------Minimum period: 0.926ns (Maximum Frequency: 1080.030MHz) Minimum input arrival time before clock: 1.337ns Maximum output required time after clock: 3.305ns

Maximum combinational path delay: 3.716ns