8 1 Adders

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8. Design of Adders
J. A. Abraham
60 Department
of Electrical and Computer Engineering The University of Texas at Austin EE 382M.7 VLSI I Fall 2011
September 21, 2011
80
ECE Department, University of Texas at Austin
Lecture 8. Design of Adders
J. A. Abraham, September 21, 2011
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Single-Bit Addition
Full Adder
mm 40 60
Half Adder S =AB Cout = A B

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S =ABC 80 100 Cout = M AJ(A, B, C)
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60 A
0 0 1 80 1
B 0 1 0 1
Cout 0 0 0 1
S 0 1 1 0
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Cout 0 0 0 1 0 1 1 1
S 0 1 1 0 1 0 0 1
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Full Adder Design I

Brute force implementation from equations S = mm B C 40 A 60 80 Cout = M AJ(A, B, C)
100 120
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Full Adder Design II

Factor S in terms of Cout
mm S = A B C + (A + B + C) Cout 80 Critical path 40 usually C 60 Cout in ripple adder 100 is to 120
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Layout of Full Adder

mm 40 60 80 100 120
Clever layout circumvents usual line of diusion

Use wide transistors on critical path Eliminate output inverters 40
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Full Adder Design III

Complementary Pass Transistor Logic (CPL)
mm Slightly faster, but more area 40 60 80 100 120
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Ripple Carry Adder

mm 40 60 80 100 120
Simplest design: cascade full adders
Critical path goes from Cin to Cout Design full adder to have fast carry (small delay for carry signal) 40
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Deal with Inversions to Speed Up Carry Path

mm 60 Critical path 40 passes through majority 80 gate Built from minority + inverter Eliminate inverter and use inverting full adder 40 100 120
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Carry Propagate Adders

mm 40 60 80 100 120
N-bit adder called CPA

Each sum bit depends on all previous carries How do we compute all these carries quickly? 40
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Carry Propagate, Generate, Kill (P, G, K)

For a full adder, dene what happens to carries Generate: Cout = 1, independent of C mm 40 60 80
G=AB 100 120
Propagate: Cout = C
P =AB
Kill: Cout = 0, independent of C 40

K =AB
Generate and Propagate for groups spanning i:j Gi:j = Gi:k + Pi:k Gk1:j 60 Pi:j = Pi:k Pk1:j Base Case
80 Gi:i Gi = Ai Bi , Pi:i Pi = Ai Bi , G0:0 = G0 = Cin P0:0 = P0 = 0
Sum: Si = Pi Gi1:0
ECE Department, University of Texas at Austin Lecture 8. Design of Adders J. A. Abraham, September 21, 2011 9 / 32
PG Logic
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Ripple Carry Adder Revisited in the PG Framework

Gi:0 = Gi + Pi Gi1:0
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Ripple Carry PG Diagram

tripple = tpg + (N 1)tAO + txor
mm 40 60 80 100 120
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PG Diagram Notation
mm 40 60 80 100 120
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Carry-Skip Adder
mm 40 60 80 100 120
Carry-ripple is slow through all N stages Carry-skip allows carry to skip over groups of n bits
Decision based on n-bit propagate signal 40
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Carry-Skip PG Diagram
mm 40 60 80 100 120
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For k n-bit groups (N = nk) tskip = tpg + [2(n 1) + (k 1)] tAO + txor
Variable Group Size

Delay grows as O( N ) mm
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Carry-Lookahead Adder (CLA)

mm 40 60 80 100 120
Carry-lookahead adder computes Gi:0 for many bits in parallel Uses higher-valency cells with more than two inputs
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CLA PG Diagram
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Higher Valency Cells
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Carry-Select Adder
mm
Trick for critical paths dependent on late input X

40 60 80 Precompute two possible outputs for X = 0, 1 Select proper output when X arrives
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Carry-select adder precomputes n-bit sums for both possible carries into n-bit group
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Carry-Increment Adder
Factor initial PG and nal XOR out of mm 40 carry-select tincrement = tpg + [(n 1) + (k 1)] tAO + txor
40 60 80 100 120
Variable Group Size 60
Buer non-critical signals80 reduce to branching eort

Tree Adders
Tree structures can be used to speed up computations Look using 2-input XOR-gates120 mm at computing the XOR of 8 bits 80 40 60 100
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If lookahead is good for adders, lookahead across lookahead! 80

Recursive lookahead gives O(log N) delay
Many variations on tree adders

Brent-Kung Adder
mm 40 60 80 100 120
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Sklansky Adder
mm 40 60 80 100 120
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Kogge-Stone Adder
mm 40 60 80 100 120
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Tree Adder Taxonomy

mm 40 60 80 100 120
Ideal N-bit tree adder would have

40 L = log N logic levels Fanout never exceeding 2 No more than one wiring track between levels Logic levels: L + l Fanout: 2f + 1 Wiring tracks: 2t
Describe adder with 3-D taxonomy (l, f, t)
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Known tree adders sit on plane dened by l + f + t = L 1
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Tree Adder Taxonomy, Contd

mm 40 60 80 100 120
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Han-Carlson Adder
mm 40 60 80 100 120
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Brent-Kung Adder
mm 40 60 80 100 120
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Knowles [2,1,1,1] Adder

mm 40 60 80 100 120
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Ladner-Fischer Adder
mm 40 60 80 100 120
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Tree Adder Taxonomy Revisited

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Summary of Adders
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Adder architectures oer area/power/delay tradeos Choose the best one for your application Architecture
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Classication
Ripple Carry Carry-skip(n=4) Carry-inc.(n=4) 60 Brent-Kung Sklansky Kogge-Stone

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(L-1,0,0) (0,L-1,0) (0,0,L-1)
Logic levels N 1 N/4 + 5 N/4 + 2 2log2 N 1 log2 N log2 N
Max. fanout 1 2 4 2 N/2+1 2
Tracks 1 1 1 1 1 N/2
Cells N 1.25N 2N 2N 0.5N log2 N N log2 N
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8 1 Adders

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8 1 Adders

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mm

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Half Adder S =AB Cout = A B

S =ABC 80 100 Cout = M AJ(A, B, C)

ECE Department, University of Texas at Austin

J. A. Abraham, September 21, 2011

Full Adder Design I

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Full Adder Design II

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Layout of Full Adder

Clever layout circumvents usual line of diusion

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Full Adder Design III

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Ripple Carry Adder

Simplest design: cascade full adders

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Deal with Inversions to Speed Up Carry Path

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Carry Propagate Adders

N-bit adder called CPA

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Carry Propagate, Generate, Kill (P, G, K)

Kill: Cout = 0, independent of C 40

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Ripple Carry Adder Revisited in the PG Framework

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Ripple Carry PG Diagram

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Variable Group Size

ECE Department, University of Texas at Austin

Lecture 8. Design of Adders

J. A. Abraham, September 21, 2011

Carry-Lookahead Adder (CLA)