IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO.

1, JANUARY 2003

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Single-Inductor Multiple-Output Switching Converters With Time-Multiplexing Control in Discontinuous Conduction Mode
Dongsheng Ma, Student Member, IEEE, Wing-Hung Ki, Member, IEEE, Chi-Ying Tsui, Member, IEEE, and Philip K. T. Mok, Senior Member, IEEE

AbstractAn integrated single-inductor dual-output boost converter is presented. This converter adopts time-multiplexing control in providing two independent supply voltages (3.0 and 3.6 V) using only one 1- H off-chip inductor and a single control loop. This converter is analyzed and compared with existing counterparts in the aspects of integration, architecture, control scheme, and system stability. Implementation of the power stage, the controller, and the peripheral functional blocks is discussed. The design was fabricated with a standard 0.5- m CMOS n-well process. At an oscillator frequency of 1 MHz, the power conversion efficiency reaches 88.4% at a total output power of 350 mW. This topology can be extended to have multiple outputs and can be applied to buck, flyback, and other kinds of converters. Index TermsCross regulation, discontinuous conduction mode (DCM), pulsewidth modulation (PWM), single-inductor dual-output (SIDO) converter, single-inductor multiple-output (SIMO) converter, time-multiplexing (TM) control.

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I. INTRODUCTION

ITH THE proliferation of battery-operated portable applications such as personal digital assistants and mobile phones, minimizing power consumption becomes one of the most important design criteria. It has been shown that voltage scaling and effective power management are the most effective ways in reducing the power consumption for digital systems [1]. Recent works showed that having multiple supply voltages can further reduce the power consumption at different design abstraction levels [2][7]. In [3], an energy-efficient high-level scheduling and allocation algorithm exploiting multiple supply voltages was proposed. In [4], system-level memory power optimization technique using multiple supply voltages was discussed. Gate- and system-level power reduction techniques utilizing multiple supply voltages were presented in [5], [6], and [7]. In these works, it is assumed that multiple supply voltages are available on-chip. Yet, details of the supply voltage generation were not discussed. Traditional on-chip dcdc converters only provide one supply voltage for the core of the chip [8]. These designs cannot be directly adapted to systems that require

(b) Fig. 1. Isolated multiple-output converters. (a) Forward converter. (b) Flyback converter.

Manuscript received March 12, 2002; revised August 6, 2002. This work was supported in part by the Hong Kong Research Grant Council under Grant CERG HKUST 6209/01E. The authors are with the Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Hong Kong, China (e-mail: eemds@ee.ust.hk). Digital Object Identifier 10.1109/JSSC.2002.806279

multiple supply voltages. To reduce the number of power and ground pins and to have a clean power supply, an on-chip dcdc converter that can provide multiple output voltages is desirable for these applications. In this paper, we address the issues of designing an on-chip single-inductor multiple-output (SIMO) dcdc converter. Conventional implementation of a dcdc converter that has output voltages may consist of independent converters, secondary windings or employ a transformer that has to distribute energy into the various outputs (isolated multiple-output converter) [Fig. 1(a) and 1(b)] [9], [10]. The first method requires too many components, including controllers and power devices, and this will increase the system cost. The second method does not allow individual outputs to be

0018-9200/03$17.00 2003 IEEE

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Fig. 3. Proposed SIDO converter. Fig. 2. Two boost converters with interleaving inductor currents in DCM.

precisely controlled and has a big limitation for the applications of multiple voltage supply scaling. In addition, leakage inductance and cross coupling among windings cause a serious cross-regulation problem. Moreover, both methods require at inductors or windings, which may be too bulky and least costly. In [11], a multiple-output architecture was proposed which combines the control loops of converters into a single one. Multiple inductors are still needed and the reduction in external components is very small. In this paper, we introduce a new single-inductor dual-output (SIDO) dcdc converter [12]. Only a single inductor is required for providing two different output voltages. Using a novel timemultiplexing (TM) control scheme, the converter only needs one controller to regulate all the outputs. Compared with other designs, both on-chip and off-chip components are reduced significantly. Implementation issues such as synchronous rectification, controller design, current detection, dead-time buffer, and ringing suppression techniques are also addressed. The design of a SIDO boost converter has been fabricated using a standard 0.5- m CMOS n-well process. Experimental results verify the validity of the design. The topology can easily be extended to give multiple outputs and to implement buck and flyback converter architectures. The remainder of the paper is organized as follows. Section II describes the basic architecture and control strategy of the proposed converter. Section III discusses the implementation details of the design. Section IV presents experimental results and Section V concludes our research efforts. II. SIMO BOOST CONVERTER A. Architecture and Control Strategy Consider two conventional boost converters A and B working at the same switching frequency. If both converters are working in the discontinuous conduction mode (DCM), a possible scheme of their inductor currents could be as shown in Fig. 2. , the inductor current ramps For Converter A, during , up and the inductor is charged with a voltage of is the duty ratio, is the switching period and where is the voltage of the source. During , ramps down , and during , stays zero. with A similar scheme also applies to Converter B. Obviously, if and , the two inductor currents can be alternately assigned to occupy different parts of the switching cycle without affecting each other. Hence, a SIDO converter can be obtained as shown in Fig. 3. The subconverters A and B of the SIDO converter share the inductor and the switch . The working principle is best de-

Fig. 4. Timing diagram of the SIDO converter.

Fig. 5. Converter presented in [13].

scribed with reference to the timing diagram shown in Fig. 4. Let and be the complementary phases of the same dura, is opened and no current flows into the tion. During . Then, is closed first. The inductor current inoutput expires, which is determined by the output of creases until , is opened and is closed an error amplifier. During . A zero current to divert the inductor current into the output detector senses the inductor current, and when it goes to zero, , and is opened again. The inductor the converter enters . Here, , and satisfy current stays zero until the requirements that (1) (2) , the inductor current is multiplexed into the During . Similar switching action repeats for subconverter B output and the two outputs are regulated alternately. Similar switching converter topologies have also been reported [13][16]. However, in [13] and [14], power diodes are and to prevent the inductor current added in series with from going negative (Fig. 5). Besides almost doubling the number of power devices, the addition of the diodes lowers the

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efficiency significantly, which is unacceptable for low-voltage applications. The converter in [13] works at the boundary of continuous conduction mode (CCM) and DCM and the converter in [15] works in CCM. Both of the converters suffer serious cross regulation (Section II-C). [14] shows three control schemes, all of which employ hysteretic control. For the first scheme, if both outputs drop at the same time, only one output could be charged up immediately, while the other has to wait until the first output surpasses its upper bound voltage. If a large load change occurs at the second output during this dead-time period, its voltage drop could be tremendous and lead to a very large ripple voltage. In the worst case, the converter may fail to be regulated. For the second and third schemes, if the converter operates in CCM, cross-regulation problem occurs as in [13] and [15]. The design in [16] is, in fact, a special case of [14]. Therefore, it suffers similar problems on large load changes and cross regulation. In addition, since the error signals are extracted based on the differential and common mode voltages of the two outputs, the converter requires two control loops. B. Design Considerations Next, our proposed converter is considered. Let the conver. Volt-second balsion ratio of subconverter A be ance of subconverter A gives (3) The conversion ratio is thus given by (4) For a boost converter, the load current is equal to the averaged diode current. Hence, from Fig. 4, a routine analysis gives (5) where is the switching frequency. The average power of subconverter A is given by (6) , and subconMaximum power occurs when verter A works at the boundary of DCM and CCM. The maximum duty ratio, maximum load current, and maximum power are then given by (7) (8) (9) Similar results apply to subconverter B. The total output power is less than , where

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(b) Fig. 6. (a) Inductor current in the first scheme of [13]. (b) Inductor current in the second scheme of [13].

C. Cross Regulation For a multiple-output converter with stable outputs, each output should be independently regulated. If the output voltage of a subconverter is affected by the change of load of another subconverter, cross regulation occurs. In the worst case, the overall converter could become unstable. The following discussion compares the performance of the control schemes in [13] with our suggested scheme. The two control schemes in [13] require the converter to operate at the boundary of CCM and DCM (Fig. 6). For the first scheme, the inductor current assumes the form as shown . Depending on the load, in Fig. 6(a), with is not equal to , and the converter does not in general, operate with a fixed switching frequency. Moreover, analysis shows that (11) and are the equivalent load resistances at the two while and , as well as outputs, respectively. This means that and , are interdependent. The consequence is that a load will affect not only , but also at change at the output the same time, and, thus, cross regulation occurs. For the second scheme, the inductor current is charged to a for a duration of , peak value. It is then discharged into before the inductor current reaches zero. The remaining charge during until the inductor current is is then transferred to zero. The relationship between and is given by (12) Again, the subconverters run at a variable switching frequency and according to the loads, and the interdependence of causes severe cross regulation between the two outputs. Analysis on the design in [14] gives similar results. Different from the above, the proposed SIDO converter employs TM control and works in the DCM. The converter switches at a fixed frequency and the inductor current goes to zero after discharging into each output. A load change at will change both and , but as long as ,

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Fig. 7.

Error amplifier with pole-zero compensation.

the energy transfer for is given by

will remain unaffected. In fact,

(13) and not on which depends only on verter does not exhibit cross regulation. D. Loop Gain Analysis and Compensation Since subconverters A and B are decoupled from each other, they can be considered as two independent converters. Without going into the arguments of modeling, we make use of the result derived in [17][19], which is accurate enough for our purpose. is given by The loop gain of subconverter , with
Fig. 8. Frequency responses of the converter with pole-zero compensation.

. Hence, the con-

(14)

is the gain of the error amplifier, which consists where is the conof the op-amp and the compensation network, trol-to-output transfer function, is the scaling factor, , is the peak-to-peak voltage of the oscillator is the filtering capacitance, is the equivalent ramp, , and is the equivalent load series resistance (ESR) of resistance. The low-frequency pole at moves as changes. The strategy of compensation is to ensure that the converter would be stable for all possible load changes. By using the pole-zero compensation network shown in Fig. 7, the corresponding transfer function, assuming an infinity gain of the op-amp, is

Fig. 9. Simulated frequency responses of the proposed converter.

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shown in Fig. 8. The control-to-output transfer function changes as changes (Fig. 8), and combines with to (Fig. 8). To engive the overall loop gain introduced by sure stability in the worst case, the zero and is placed at the lowest possible pole frequency of ) in (14), which corresponds to the lightest load, i.e., when the load resistance is of the compensation the largest. The high-frequency pole and is placed at the frequency of the network caused by in the control-to-output zero response curve caused by the ESR of the filtering capacitor. Hence, the values of the components are given by (16) (17)

, and a second which has a first pole at 0, a zero at . The zero is at a lower frequency in pole at is magnitude than the second pole, and the Bode plot of

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(b) Fig. 10. (a) SIMO converter with

N outputs. (b) Timing diagram of the converter with N outputs having unbalanced loads.
TABLE I COMPARISON OF MULTIPLE-OUTPUT CONVERTER ARCHITECTURES

(18) is the gain of the compensation network at the where is the crossover crossover frequency of the loop gain, and frequency which is related to the bandwidth of the converter. Fig. 9 shows the simulated loop gain with compensation of this design.
Fig. 11. SIDO flyback converter.

E. Topological Extensions With TM control, this converter can be extended to have outputs [Fig. 10(a)], when nonoverlapping phases are assigned to the corresponding outputs accordingly. Also, these phases do not need to have equal duty ratios [Fig. 10(b)].

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Fig. 12.

Block diagram of the proposed SIDO converter.

Fig. 13.

Schematic of CMOS current detector using transistor scaling.

Their duty ratios could be assigned according to corresponding load requirements at their outputs. As a summary, Table I compares the architectural features outputs, the of the converters discussed above. To achieve proposed SIMO converter needs only one inductor, one control loop and the minimum number of power devices. Hence, it is a cost-effective topology for power management systems. Moreover, this design can be extended to realize SIMO converters with buck and/or flyback subconverters to fulfill different system requirements [20], [21]. As an example, Fig. 11 shows the power stage of a SIDO flyback converter. III. SYSTEM IMPLEMENTATION A. Controller Fig. 12 shows the block diagram of the SIDO converter. The are implemented by power transistors switches , , and , , and , respectively. The two output voltages and are scaled and fed into their respective error ampli, the switch is closed and the output fiers. During
Fig. 14. Measured V with reference to the inductor current.

voltage of the error amplifier is sampled by the pulsewidth modulation (PWM) generator to determine the duty ratio for the output . During , the switch is on and

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(b) Fig. 15. (a) Block diagram of dead-time control buffer. (b) Currents in the inverter without delay elements.

the switch is off. The duty ratio for is determined in a similar fashion. Note that many of the functional blocks in the control loop are time shared, which reduces the complexity of the controller. B. Synchronous Rectification and Zero-Current Sensing For a switching converter, one of the switches is usually implemented as a diode to simplify the control circuitry and to automatically block the reverse current. Now, let the switches and of Fig. 3 be replaced by diodes with the anodes connected to the inductor. Without using switches, the inductor curand and will charge up rent cannot differentiate between in the steady both outputs at the same time and gives

state. This is the reason why a transistor is added in series to each of the diode in [13]. However, for low-voltage applications, the turn-on voltages of the diodes seriously degrade the efficiency. To improve the efficiency, synchronous rectification is adopted. Freewheeling diodes are replaced by transistors and with low on-resistance (Fig. 12). Two zero-current sensors A and B sense the currents flowing into the outputs and , respectively. They are implemented by voltage . Because the comparators. Consider the case for converter works in DCM, the inductor current tends to go . The bidirectional switch negative at the end of cannot block reverse current as a diode does, and when current sensor A detects a zero inductor current, the power transistor

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(b) Fig. 16. (a) Ringing suppression circuit. (b) Simulated results on node X without/with ringing suppression circuit.

is then turned off to prevent the current from flowing . back to the source. Similar action applies to the switch The present design uses PMOS power transistors to replace the diodes. For a boost converter, the two output voltages are both . The substrate of larger than the supply voltage. Let the switches and the supply voltage of the dead-time control buffer should be connected to the highest voltage of the system so that the switches can be fully turned on and off to avoid leakage currents. C. Current Detector The current detector is used to sense the inductor current and help to prevent a large current from damaging the power devices. Existing techniques include using a current transformer or in series with a power device. The first a sensing resistor method is expensive and has cross-coupling and electromagnetic interference (EMI) problems, while the second method has ). large conduction loss ( Fig. 13 introduces a CMOS current-sensing circuit using transistor scaling, which is a modified version of a BiCMOS coun-

terpart [22]. The transistors and constitute a current mirror in sinking equal currents into two identical NMOS tranand . If the transistors are well matched, the voltsistors and are equal, forcing the drain ages at the sources of , and to be equal. and work as voltages of two switches controlled by complementary control signals and , respectively. The node X is connected to the drain of in Fig. 12. Once is turned the NMOS power transistor 1 at the same time), is also turned on with on (with . In this case, and have the same dc biasing voltis proportional to that ages. Therefore, the current through according to the scaling ratio . of is designed to be much smaller than , and . The is scaled down by power loss by the sensing resistor times. When is shut off (and 1), is switched on in draining the current to ground to keep the current mirror with reference to the active. Fig. 14 shows the measured , the inductor current on the fabricated chip. During every is linearly proportional to the inductor voltage drop of current . Its power consumption is less than 20 W while the converter provides a 550-mW output power.

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Fig. 17.

Chip micrograph.

Fig. 18.

Inductor current of the converter in the steady state.

D. Dead-Time Control To achieve low on-resistances, the power transistors of the in Fig. 12 should not be turned converter are large. Hence, or is conducting to avoid large shooton when either through current that would greatly degrade the efficiency and cause large glitches in the inductor current and output voltages. A dead-time control circuitry is, thus, needed [Fig. 15(a)]. The power transistors are driven by large buffers. By adding a resistor in the driving inverter, the PMOS ( ) of the driven inverter can be turned off prior to the turn-on of the NMOS ( ) during a 1 to 0 transition, and shoot-through current of the buffer can also be avoided. A similar mechanism applies to the and as 0 to 1 transition. The resistor is realized by shown in Fig. 15(a). Fig. 15(b) shows the currents of the inverter simulated by Hspice with and without these delay elements. With the delay elements, only one transistor (NMOS or PMOS) is conducting during logic transitions and no shoot-through currents occurs. E. Ringing Suppression Since the converter works in DCM, there are time intervals and the that all power transistors are off. The inductor then form an oscillatory circuit as shown parasitic capacitor in Fig. 16(a). Large ringing occurs at node X, causing large switching noise and EMI. The present design incorporates a ringing suppression circuit [Fig. 16(a)] similar to that discussed in [23]. When all power transistors are off, the inductor is shorted to break the oscillation loop. The voltages at node X with and without ringing suppression circuitry are shown in Fig. 16(b). IV. EXPERIMENTAL RESULTS The SIDO boost converter was fabricated with a standard 0.5- m CMOS n-well process. Fig. 17 shows the chip micrograph of the converter. Power transistors are connected to multiple pads in parallel to achieve low parasitic resistance. is split into two parts for easy The NMOS transistor routing. Fig. 18 shows the inductor current of the converter
Fig. 20. The two outputs with reference to the inductor current.

Fig. 19.

Voltage at node X.

in the steady state, which correlates well with our simulated waveform. Fig. 19 shows the waveform at Node X of the converter. The duty ratios at alternate cycles are those of the individual subconverters. When all the switches are off, Node X

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(a) (a)

(b) Fig. 21. (a) The two outputs with a dynamic load at V . (b) The two outputs with a dynamic load at V .

settles to or quickly and smoothly, demonstrating that ringing due to DCM operation has been effectively suppressed. The two output voltages, 3 and 3.6 V, are shown in Fig. 20 with reference to the inductor current. Fig. 21 illustrates that the converter is not susceptible to cross regulation. The output current of subconverter A is 75 mA, and that of subconverter B is 25 mA. An electronic load provided by HP6063B is connected to the output of subconverter B. The load current steps from 0 to 50 mA at a frequency of 1 KHz and a duty ratio of 0.5. The slew rate of the load current is set at 0.083 A/ s. Measurement results show that the load change in subconverter B has little effect on the output of subconverter A, and vice versa, thus verifying the analysis in Section II-C. Fig. 21 also shows that both outputs could recover to the steady-state values changes, the within 250 s. Fig. 22(a) shows that when inductor current of subconverter A (the lower side of ) rises accordingly, while that of subconverter B (the higher side of ) remains unchanged. The close-up view of Fig. 22(a) is shown in Fig. 22(b) in revealing the changes of the inductor current in detail. A similar testing setup can be used to measure load regulation. Fig. 23 shows the efficiency of the converter versus the two output loads. Although the parasitic resistance of the inductor is 125 m and the capacitor ESRs are 80 m or more, the converter achieves high efficiency over a wide range. mW The maximum efficiency 88.4% is measured at mW. As load currents increase, conduction loss and

(b) Fig. 22. (a) The inductor current with a dynamic load at one output. (b) Close-up view of (a).

Fig. 23.

Efficiency of the proposed SIDO converter.

dominates. As load currents decrease, switching loss dominates. In both cases, the efficiency drops. Table II summarizes the performance of the converter.

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TABLE II PERFORMANCE SUMMARY

V. CONCLUSION A SIDO boost converter with TM control was presented. Compared to existing designs, the converter requires fewer inductors, power devices, and control loops, which is suitable for portable applications and system-on-chips (SOCs). System implementation issues were discussed. Experimental results demonstrate the functionality and show good performance of the design on voltage regulation, power efficiency, and cross-regulation suppression. The SIDO converter provides a cost-effective solution in designing on-chip power management systems and realizing voltage scheduling techniques.

[8] J. Goodman, A. P. Dancy, and A. P. Chandrakasan, An energy/security scalable encryption processor using an embedded variable voltage DC/DC converter, IEEE J. Solid-State Circuits, vol. 33, pp. 17991809, Nov. 1998. [9] M. Brown, Practical Switching Power Supply Design. San Diego, CA: Academic, 1990. [10] R. W. Erickson, Fundamentals of Power Electronics. Boston, MA: Kluwer, 1999. [11] A. P. Dancy, R. Amirtharajah, and A. P. Chandrakasan, High-efficiency multiple-output dc-dc conversion for low-voltage systems, IEEE Trans. VLSI Syst., vol. 8, pp. 252263, June 2000. [12] D. Ma, W.-H. Ki, C.-Y. Tsui, and P. K. T. Mok, A 1.8 V single-inductor dual-output switching converter for power reduction techniques, in Dig. Tech. Papers IEEE VLSI Symp. Circuits, June 2001, pp. 137140. [13] T. Li, Single inductor multiple output boost regulator, U.S. Patent 6 075 295, June 2000. [14] D. Goder and H. Santo, Multiple output regulator with time sequencing, U.S. Patent 5 617 015, Apr. 1997. [15] Y. Ma and K. M. Smedley, Switching flow-graph nonlinear modeling method for multistate-switching converters, IEEE Trans. Power Electron., vol. 12, pp. 854861, Sept. 1997. [16] M. W. May, M. R. May, and J. E. Willis, A synchronous dual-output switching dc-dc converter using multibit noise-shaped switch control, in Dig. Tech. Papers IEEE Int. Soild-State Circuits Conf., Feb. 2001, pp. 358359. [17] R. D. Middlebrook and S. Cuk, A general unified approach to modeling dc-to-dc converters in discontinuous conduction mode, in Proc. IEEE PESC77, 1977, pp. 3657. [18] J. Sun, D. M. Mitchell, M. F. Greuel, P. T. Krein, and R. M. Bass, Modeling of PWM converters in discontinous conduction modeA reexamination, in Proc. IEEE PESC98, 1998, pp. 615622. [19] V. Tam, Loop gain simulation and measurement of PWM switching converters, M. Phil. thesis, The Hong Kong Univ. Sci. Technol., Hong Kong, China, 1999. [20] D. Ma, W.-H. Ki, C. Y. Tsui, and P. K. T. Mok, A family of single-inductor multiple-output switching converters with bipolar outputs, in Proc. IEEE Int. Symp. Circuits and Systems, vol. 3, May 2001, pp. 301304. [21] W.-H. Ki and D. Ma, Single-inductor multiple-output switching converters, in Proc. IEEE PESC, vol. 1, June 2001, pp. 226231. [22] W.-H. Ki, Current sensing technique using MOS transistors scaling with matched bipolar current sources, U.S. Patent 5 757 174, May 26, 1998. [23] S.-H. Jung, N.-S. Jung, J.-T. Hwang, and G.-H. Cho, An integrated CMOS DC-DC converter for battery-operated systems, in Proc. IEEE PESC99, 1999, pp. 4347.

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[1] J. Rabaey and M. Pedram, Low Power Design Methodologies. Boston, MA: Kluwer, 1996. [2] Y.-H. Lu and G. De Micheli, Comparing system level power management policies, IEEE Des. Test Comput., vol. 18, pp. 5360, Mar. 2001. [3] J.-M. Chang and M. Pedram, Energy minimization using multiple supply voltages, IEEE Trans. VLSI Syst., vol. 5, pp. 436443, Dec. 1997. [4] T. Ishihara and K. Asada, A system level memory power optimization technique using multiple supply and threshold voltages, in Proc. Asian and South Pacific Design Automation Conf., Jan. 2001, pp. 456461. [5] Y.-J. Yeh, S. Y. Kuo, and J. Y. Jou, Converter-free multiple-voltage scaling techniques for low-power CMOS digital design, IEEE Trans. Computer-Aided Design, vol. 20, pp. 172176, Jan. 2001. [6] K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanazawa, M. Ichida, and K. Nogami, Automated low-power technique exploiting multiple supply voltages applied to a media processor, IEEE J. Solid-State Circuits, vol. 33, pp. 463472, Mar. 1998. [7] M. Johnson and K. Roy, Scheduling and optimal voltage selection for low power multi-voltage DSP datapaths, in Proc. IEEE Int. Symp. Circuits and Systems, vol. 3, May 1997, pp. 21522155.

Dongsheng Ma (S00) received the B.Sc. degree with highest honors as an Excellent Graduate Student and the M.Sc. degree, both in electronic science, from Nan Kai University, Tianjin, China, in 1995 and 1998, respectively. He is currently working toward the Ph.D. degree at The Hong Kong University of Science and Technology, Hong Kong, China. His research interests include integrated power management system designs, low-voltage analog and mixed-signal integrated circuit designs, control methodology, and modeling of power electronics systems. Mr. Ma is a recipient of an STMicroelectronics Ltd. Scholarship, Motorola Ltd. Scholarship, Guang Hua Foundation Scholarship, and Hua Wei Scholarship for academic and research excellence. He also won a Distinguished Paper Award in the IEEE (Hong Kong) 2000 Student Paper Contest.

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Wing-Hung Ki (S86M92) received the B.Sc. degree from the University of California, San Diego, in 1984, the M.Sc. degree from the California Institute of Technology, Pasadena, in 1985, and the Engineer and Ph.D. degrees from the University of California, Los Angeles, in 1990 and 1995, respectively, all in electrical engineering. He joined Micro Linear Corporation, San Jose, CA, in 1992, as a Senior Design Engineer in the Department of Power and Battery Management, working on the design of power converter controllers. He then joined The Hong Kong University of Science and Technology, Hong Kong, China, in 1995, where he is currently an Associate Professor in the Department of Electrical and Electronic Engineering. His research interests include design and modeling of switch-mode power converters, charge pumps, low dropout regulators, switched-capacitor circuits, and analog decoding circuits. Dr. Ki was the recipient of the Asia Innovator Award of the Year 19971998 granted by EDN Asia.

Philip K. T. Mok (S86M95SM02) received the B.A.Sc., M.A.Sc., and Ph.D. degrees in electrical and computer engineering from the University of Toronto, Toronto, ON, Canada, in 1986, 1989, and 1995, respectively. While at the University of Toronto, he was a Teaching Assistant in both the Electrical Engineering and Industrial Engineering Departments from 1986 to 1992. He taught courses in circuit theory, IC engineering, and engineering economics. He was also a Research Assistant in the Integrated Circuit Laboratory, University of Toronto, from 1992 to 1994. In January 1995, he joined the Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Hong Kong, China, as an Assistant Professor. His research interests include semiconductor devices, processing technologies and circuit designs for power electronics and telecommunications applications, with current emphasis on power integrated circuits, low-voltage analog integrated circuits, and RF integrated circuits design. Dr. Mok received the Henry G. Acres Medal, the W.S. Wilson Medal, and a Teaching Assistant Award from the University of Toronto, and the Teaching Excellence Appreciation Award twice from The Hong Kong University of Science and Technology.

Chi-Ying Tsui (M95) received the B.S. degree in electrical engineering from the University of Hong Kong, Hong Kong, China, in 1982, and the Ph.D. degree in computer engineering from the University of Southern California, Los Angeles, in 1994. In 1994, he joined the Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Hong Kong, China, where he is currently an Associate Professor. His research interests focus on designing VLSI architectures for high-speed networks and low-power multimedia and wireless applications, designing power management circuits and techniques for embedded portable devices, and developing VLSI CAD algorithms for low-power applications. Dr. Tsui received the Best Paper Award from the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS in 1995 and supervised the Best Student Paper Award of the 1999 IEEE ISCAS. He has served on the technical program committee of a number of conferences and symposiums, including ILSPED, ASP-DAC, and the IEEE VLSI Symposium.