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I.
INTRODUCTION
Rapid growth in semiconductor technology has led to shrinking of feature sizes of transistors using deep submicron (DSM) process. As MOS transistors enter deep submicron sizes, undesirable consequences regarding power consumption arise. Until recently, dynamic or switching power component dominated the total power dissipated by an IC. Voltage scaling is perhaps the most effective method to decrease dynamic power due to the square law dependency of digital circuit active power on the supply voltage. As a result, this demands a reduction of threshold voltage to maintain performance. Low threshold voltage results in an exponential increase in the sub-threshold leakage current. On the other hand as technology scales down, shorter channel lengths result in increased sub-threshold leakage current through an off transistor. Therefore, in DSM process static or leakage power becomes a considerable proportion of the total power dissipation. For these reasons, static power consumption, i.e. leakage power dissipation, has become a significant portion of total power consumption for current and future silicon technologies.
denotes carrier mobility ,Cox is the gate oxide capacitance per unit area, W and L denote the width and effective length of the transistor, K is the Boltzmann constant, T is the absolute temperature, and q is the electrical charge of an electron. In addition, VTH is the zero biased threshold voltage, _ is body effect coefficient, _ denotes the drain-induced barrier lowering (DIBL) coefficient, n is the slope shape factor subthreshold swing coefficient. [1]
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Fig. 1: Tackling leakage techniques (a: MTCMOS- b: SCCMOS -c: Forced Stack) Another technique, which is similar to MTCMOS power gating, is Super Cutoff CMOS (SCCMOS). As seen from (1), the sub-threshold leakage is dependent on the VGS. According to Fig.1(b) by using slight negative voltage gate, the sub-threshold current reduces exponentially The key difference with MTCMOS is that the sleep transistors have the same low threshold voltage. Because of using low VTH sleep transistors the additional delay caused by high VTH sleep transistors can be reduced during active mode. Although this scheme can improve the performance of the circuit, like MTCMOS, it can't save the circuit logic state during standby mode, so the technique results in destruction of circuit logic state [7]. Another approach used for leakage power reduction in active mode is the stack technique which has shown in fig.1( c). Narendra et al. studied the effectiveness of the stack effect. Stack effect or Self-Reverse bias effect is the phenomenon where leakage current decreases due to two or more series transistors that are turned off .Equation 1 shows dependence of the sub-threshold current to the voltages of all the four terminals. Transistor stacking technique exploits the dependence of ISUB on the source terminal voltage. According to (1) with the increase of the Vs of the transistor, transistor, the sub-threshold leakage current reduces exponentially. This would happen due to the following reasons: The Gate-to-Source voltage ( VGS ) would reduce and if the input applied is grounded, it would turn negative .This would reduce SUB I exponentially Threshold voltage increases due to body effect. The DIBL coefficient decreases due to lower drain to source potential thereby further reducing leakage. However, the forced stack technique cannot save power consumption in standby mode [8]-[9]-[10].
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Fig. 2: Multi purpose technique (a:Active mode- b:Standby mode) pull-up network. Similarly, to maintain a value of 0 in standby mode, transmission gate in parallel to the NMOS sleep transistors is the only source of GND to the pull-down network
V. SIMULATION RESULT
Simulations have been performed using HSPICE in 65 nanometer (nm) standard CMOS technology at room temperature; with supply voltage 0.7v to estimate power consumption. We use the BSIM4 model of Berkeley Predictive Technology Model (BPTM) parameters for the technologies 65 nanometer (nm) standard CMOS technology [11]-[12]-[13]. 1-bit full adder (Fig.3) and NAND circuit are chosen to compare our technique to the other techniques: MTCMOS, SCCMOS and Forced stack. Dynamic power is measured with a random input vector changing every clock cycle.
Fig. 3: Resulting waveform of 1 bit full adder The resulting waveforms,Va,Vb,Vc according to Fig.4 are asserted cyclically for 500ns and the average power dissipated measured by HSPICE during this period recorded as dynamic power .We measure sub-threshold current by varying V(a) and V(b) to sub-threshold voltage from 0 to 0.18 volt and V(c)=0.7v as dc source. In this condition average current has been measured during 0 to 500ns.
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According to simulation result in this method there is a 1333-time, 1466-time and 2-time decrease compared to MTCMOS, SCCMOS and Stack respectively during active mode, and a 5- time _ 11.36-time decrease compared to MTCMOS and SCCMOS during standby mode, But because of adding additional transistors to circuit dynamic power has increased in all approaches .The above-mentioned points can be seen in the following charts in fig.4.
VI. CONCLUSION
There are various points that must be taken in to account low-power design which include the style of logic, the technology used, the logic implemented and trade off. After analyzing various leakage reduction techniques, it can be concluded that there is a strong correlation between the three performance metrics: leakage power, dynamic power and propagation delay. In this paper, it presented an effective technique to low leakage power VLSI design. The proposed approach focuses on reducing sub-threshold current during active and standby mode of circuit unlike MTCMOS which can reduce its during standby mode and unlike forced stack which can reduce its during active mode.
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REFERENCES
[1] [2] [3] [4] [5] International Technology Roadmap for Semiconductors, 2007. T.SAKURAI ,Perspective of Low Power VLSI_s,IEICE Transaction, vol.E87.no.4,pp.429-436, April 2004. Borisav Jovanovic, Milunka Damnjanovic, Proceeding. 54th ETRAN Conference, , June 7-10, 2010 Donji Milanovac Dhananjay E. Upasani, Sandip B. Shrote, Pallavi S.Deshpande , Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits, International journal of computer application,vol.7,no.5,pp.1-4,septamber 2010. Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., and Yamada, J. 1-V, Power Supply High-Speed Digital Circuit Technology with Multi-threshold-Voltage CMOS, IEEE Journal of Solid-State Circuits, vol.30, no.8, pp.847-854, August 1995. Kao, J. T., and Chandrakasan, A. P. Dual-Threshold Voltage Techniques for Low-power Digital Circuits, IEEE Journal of SolidState Circuits, vol.35, no.7, pp.1009-1018,July 2000. Kawaguchi, H., Nose, K., and Sakurai, T. A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Pico ampere Stand-By Current, IEEE Journal of Solid State Circuits vol.35,n.10 pp.1498-1501, October 2000. Park, J. C., and Mooney III, V. J. Sleepy Stack Leakage Reduction.Very Large Scale Integration (VLSI) Systems, IEEE Transactions ,vol.14,no.11, pp.1250-1263, November 2006. B.S. Deepaksubramanyan and Adrian Nunez EECS Department,Syracuse University , Analysis of Subthreshold Leakage Reduction inCMOS Digital Circuits, Proceeding of the 13TH NASA VLSISymposium Post Fall, IDAHO, USA, June 2007. M. Iijima, K. Seto, M. Numa,Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation, journal of computers, vol. 3, no. 5,pp.3
1.
K Sridhar is doing his Ph.D. research in area of Image Processing and he completed his B.Tech ECE from Vijay Rural Engineering & Technology, M.Tech from Mahaveer Institute Of Science And Technology,,Hyderabad. Currently he working as Asst Prof at JNTUH affiliated college, having 6 years of experience in Academic has guided many students. His research areas include Image Processing, Wireless Networks and Computer Networks.
2.
Narayana Rao Latchupatula B.Tech ECE from Avanthi College of Engineering & Technology, Vishakhapatnam M.Tech VLSI SD from Kshatriya College of Engineering, Armoor Currently he working as Asst Prof at JNTUH affiliated college, having 5 years of experience in Academic has guided many students. His interest areas include Mobile Communication, VLSI, Embedded System, Signal Processing
3.
Santosh Amshala B.Tech ECE from Vijay Rural Engineering & Technology, M.Tech ECE from Vijay Rural Engineering & Technology. Currently he working as Asst Prof at JNTUH affiliated college, having 4 years of experience in Academic has guided many students. His interest areas include Mobile Computing, Embedded System ,VLSI Design.
4. Mohd. Saleem Uddin done B.Tech ECE from Kshatriya College of Engineering, M.Tech ECE from Vijay Rural Engineering & Technology. Currently he working as Asst Prof at JNTUH affiliated college, having 2years of experience in Academic. His interest areas include Mobile Communication, VLSI, Embedded System, Signal Processing.
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