2012

Memory Management
Memory Management In Computer Organization
This Mini Books Contain the short description about the Memory Management and different Memory Management Techniques which may be useful for the Beginner IT Professionals

Amrit Razz Shrestha 8/27/2012

About The Author

Hello Every One i am Amrit Razz Shrestha, i am very happy to upload my second book related to Information Management. I am a information management student and currently studing In Bachlor In Informtion Management, 4th Semester. This is part of Research/ Project work on subject Computer Organization which i did. I hope this book will be helpful for you all...... Please send me ur feedback at amrit_razz@live.com [This email address is my facebook address too, you can add me and send me your feedback here too]. I am waiting for ur feedback so that i can upload even better content in future for You!! Thats my Promise!! Thank you!! Author Amrit Razz Shrestha

Introduction

Memory Management In operating system for a personal computer the procedure for optimizing the use of RAM (Random Access Memory) is called Memory Management. These procedure includes selectively storing data, monitoring it carefully and freeing memory when data is no longer needed. Most current operating system optimize RAM usage on their own ; some older operating system such as early version of MSDOS require the use of third party utilizes to optimize RAM usage and necessitated that the user be more knowledgeable about how the operating system and applications used memory.

Memory Management Program A program use to store data and program in system memory, monitor their use and reassign the free space following their execution is called Memory Management Program or A program that uses hard disk space as an extension of the random access memory(RAM) is called Memory Management Program.

Memory Management Unit The hardware that supports the mapping of virtual memory address to physical memory address is simply Memory management Unit. In most of the modern microcomputers, the memory management unit is built into the CPU chip. In some systems, the memory management unit provides interfacing between the microprocessor and memory. This type of memory management unit is typically responsible for address multiplexing and in the case of DRAMs the refresh cycle.

Memory Hierarchy
Register

Cache Memory

Main Memory

Auxiliary Memory
Fig: Pyramid Showing the Memory Hierarchy in Computer System

Process of separating memory into different hierarchal levels is called Memory Hierarchy. Memory Hierarchy helps in high speed and low cost operations in the computer system. Different hierarchal levels include CPU registers Cache Memory Main Memory Auxiliary Memory To this point in our study of systems, we have relied on a simple model of a computer system as a CPU that executes instructions and a memory system that holds instructions and data for the CPU. In our simple model, the memory system is a linear array of bytes, and the CPU can access each memory location in a constant amount of time. While this is an effective model as far as it goes, it does not reflect the way that modern systems really work. In practice, a memory system is a hierarchy of storage devices with different capacities, costs, and access times. CPU registers hold the most frequently used data. Small, fast cache memoriesnearby the CPU act as stagingareas for a subset of the data and instructions stored in the relatively slow main memory. The main memory stages data stored on large, slow disks, which in turn often serve as staging areas for data stored on the disks or tapes of other machines connected by networks.

Memory hierarchies work because well-written programs tend to access the storage at any particular level more frequently than they access the storage at the next lower level. So the storage at the next level can be slower, and thus larger and cheaper per bit. The overall effect is a large pool of memory that costs as much as the cheap storage near the bottom of the hierarchy, but that serves data to programs at the rate of the fast storage near the top of the hierarchy. As a programmer, we need to understand the memory hierarchy because it has a big impact on the performance of our applications. If the data we r program needs are stored in a CPU register, then they can be accessed in zero cycles during the execution of the instruction. If stored in a cache, 1 to 30 cycles. If stored in main memory, 50 to 200 cycles. And if stored in disk tens of millions of cycles! Here, then, is a fundamental and enduring idea in computer systems: If we understand how the system moves data up and down the memory hierarchy, then we can write we are application programs so that their data items are stored higher in the hierarchy, where the CPU can access them more quickly.

Cache Memory Cache Memory, in computer science, a portion of a computers random access memory (RAM) that is set aside for temporary storage of information. A disk cache does not hold entire files like a RAM disk (a portion of memory that acts as if it were a separate disk drive). Instead, a disk cache is used to hold information that has recently been requested from disk or has been written to disk. For example, a program might need to read the same portions of a data file repeatedly from disk. If the required information remains in a disk cache, access time is considerably reduced, as the program does not have to wait for the disk drive mechanism to fetch the information from disk each time it is required. The portion of the computers RAM that is used for a disk cache can be part of the disk drive itself. This is called a hard disk cache, or buffer. Alternatively, general purpose RAM can be reserved for use by the disk drive (sometimes called a soft disk cache). In operation, hard disk caches are more effective but they are also more expensive. A soft disk cache works by storing the most recently accessed data in the RAM cache. When the program needs to gain access to this data, the operating system checks to see whether it is in the cache or not. If it is, there is no need to access the disk and the data is retrieved from the cache. The main benefit of a cache is that computer performance is much enhanced. A computer can access data from RAM much faster than it can from disk. In order to further enhance performance, many cache systems also try to predict what data will be requested next, so that they can put that data into the cache ready for when it is needed.

Types of Mapping Procedure

The transfer of data from the main memory to cache memory is referred as Mapping Procedure. Three types of Mapping Procedure are of Practical interest when considering the organization of the cache memory. 1. Associative Mapping 2. Direct Mapping 3. Set Associative mapping

Associative Mapping
The memory mapping techniques that stores address and the content of the memory word is called Associative mapping. This permits any location in cache to store any word from the main memory. It is fastest and most flexible mapping technique. Any location in cache can store any word from main memory.A CPU address is placed in the argument register and the associative memory is searched for matching address.If the mapping address is found, corresponding data is send to CPU, if no match found, the main memory is accessed for the word.The address-data pair is transferred to the associative cache memory.If the cache is full, the address-data pair must be replaced using FIFO policy. The diagram shows the three words presently stored in the cache. Thecpu address of 15 bit is placed in the argument register and the associative memory is searched for a matching address. If the address is found the corresponding 12 bit data is read and send to the CPU. If no match occurs, the main memory is accessed for the word. The address data pair is then transferred to the associative cache memory. For the replacement of the data from cache memory, FIFO policy is used.

Direct Mapping
Associative memories are expensive compared to random-access memories because of the added logic associated with each cell. The CPU address of 15 bits is divided into two fields. The nine least significant bits tag field constitutes the index field and the remaining six bits form the tag field. The figure shows that main memory needs an address that includes both the tag and the index bits. The number of bits in the index field is equal to the number of address bits required to access the cache memory. In the general case, there are 2k words in cache memory and 2" words in main memory. The n-bit memory address is divided into two fields: k bits for the index field and n - k bits for the tag field. The direct mapping cache organization uses the n-bit address to access the main memory and the k-bit index to access the cache. Each word in cache consists of the data word and its associated tag. When a new word is first brought into the cache, the tag bits are stored alongside the data bits. When the CPU generates a memory request, the index field is used for the address to access the cache. The tag field of the CPU address is compared with the tag in the word read from the cache.

Fig: Addressing relationships between main and cache memories.

Fig: Direct mapping cache organization. If the two tags match, there is a hit and the desired data word is in cache. If there is no match, there is a miss and the required word is read from main memory. It is then stored in the cache together with the new tag, replacing the previous value. The disadvantage of direct mapping is that the hit ratio can drop considerably if two or more words whose addresses have the same index but different tags are accessed repeatedly. However, this possibility is minimized by the fact that such words are relatively far apart in the address range (multiples of 512 locations in this example.) To see how the direct-mapping organization operates, consider the numerical example shown in Fig. The word at address zero is presently stored in the cache (index = 000, tag = 00, data = 1220). Suppose that the CPU now wants to access the word at address 02000. The index address is 000, so it is used to access the cache. The two tags are then compared. The cache tag is 00 but the address tag is 02, which does not produce a match. Therefore, the main memory is accessed and the data word 5670 is transferred to the CPU. The cache word at index address 000 is then replaced with a tag of 02 and data of 5670. The direct-mapping example just described uses

a block size of one word. The same organization but using a block size of 8 words is shown in figure.

Fig: Direct mapping cache with block size of 8 words. The index field is now divided into two parts: the block field and the word field. In a 512-word cache there are 64 blocks of 8 words each, since 64 x 8 = 512. The block number is specified with a 6-bit field and the word within the block is specified with a 3-bit field. The tag field stored within the cache is common to all eight words of the same block. Every time a miss occurs, an entire block of eight words must be transferred from main memory to cache memory. Although this takes extra time, the hit ratio will most likely improve with a larger block size because of the sequential nature of computer programs.

Set Associative Mapping

It was mentioned previously that the disadvantage of direct mapping is that two words with the same index in their address but with different tag values cannot reside in cache memory at the same time. A third type of cache organization, called set-associative mapping, is an improvement over the direct-mapping organization in that each word of cache can store two or more words of memory under the same index address. Each data

word is stored together with its tag and the number of tag-data items in one word of cache is said to form a set. An example of a set-associative cache organization for a set size of two is shown in Figure. Each index address refers to two data words and their associated tags.Each tag requires six bits and each data word has 12 bits, so the word length is 2(6 + 12) = 36 bits. An index address of nine bits can accommodate 512 words. Thus the size of cache memory is 512 x 36. It can accommodate 1024 words of main memory since each word of cache contains two data words. In general, a set-associative cache of set size k will accommodate k words of main memory in each word of cache.

Fig: Two-way set-associative mapping cache. The octal numbers listed in Figure are with reference to the main memory contents illustrated in previous figure. The words stored at addresses 01000 and 02000 of main memory are stored in cache memory at index address 000. Similarly, the words at addresses 02777 and 00777 are stored in cache at index address 777. When the CPU generates a memory request, the index value of the address is used to access the cache. The tag field of the CPU address is then compared with both tags in the cache to determine if a match occurs. The comparison logic is done by an associative search of the tags in the set similar to an associative memory search: thus the name "set-associative." The hit ratio will improve as the set size increases because more words with the same index but different tags can reside in cache. However, an increase in the set size increases the number of bits in words of cache and requires more complex comparison logic. When a miss occurs in a set-associative cache

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and the set is full, it is replacement necessary to replace one of the tag-data items with a new value. The most algorithms common replacement algorithms used are: random replacement, first-in, first- out (FIFO), and least recently used (LRU). With the random replacement policy the control chooses one tag-data item for replacement at random. The FIFO procedure selects for replacement the item that has been in the set the longest. The LRU algorithm selects for replacement the item that has been least recently used by the CPU. Both FIFO and LRU can be implemented by adding a few extra bits in each word of cache.

In computing, virtual memory is a memory management technique developed for multitasking kernels (kernels are a bridge between applications and the actual data processing done at the hardware level. The kernel's responsibilities include managing the system's resources (the communication between hardware and software components).)This technique virtualizes a computer architecture's various forms of computer data storage (such as random-access memory and disk storage), allowing a program to be designed as though there is only one kind of memory, "virtual" memory, which behaves like directly addressable read/write memory (RAM). Virtual memory is a concept used in some large computer systems that permit the user to construct programs as though a large memory space were available, equal to the totality of auxiliary memory. Most computers today dont have enough amount of RAM to run all of the programs that most users expect to run at once.For example, if you load the operating system, an email program, a Web browser and word processor into RAM simultaneously, 32 megabytes is not enough to hold it all. If there were no such thing as virtual memory, then once you filled up the available RAM your computer would have to say, "Sorry, you cannot load any more applications. Please close another application to load a new one." With virtual memory, what the computer can do is look at RAM for areas that have not been used recently and copy them onto the hard disk. This frees up space in RAM to load the new application.

Virtual Memory

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Because this copying happens automatically, you don't even know it is happening, and it makes your computer feel like is has unlimited RAM space even though it only has 32 megabytes installed. Because hard disk space is so much cheaper than RAM chips, it also has a nice economic benefit. Virtual memory is a feature of an operating system that enables a process to use a memory (RAM) address space that is independent of other processes running in the same system, and use a space that is larger than the actual amount of RAM present, temporarily relegating some contents from RAM to a disk, with little or no overhead. In a system using virtual memory, the physical memory is divided into equally-sized pages. The memory addressed by a process is also divided into logical pages of the same size. When a process references a memory address, the memory manager fetches from disk the page that includes the referenced address, and places it in a vacant physical page in the RAM. Subsequent references within that logical page are routed to the physical page. When the process references an address from another logical page, it too is fetched into a vacant physical page and becomes the target of subsequent similar references. If the system does not have a free physical page, the memory manager swaps out a logical page into the swap area - usually a paging file on disk (in Windows XP: pagefile.sys), and copies (swaps in) the requested logical page into the now-vacant physical page. The page swapped out may belong to a different process. There are many strategies for choosing which page is to be swapped out. (One is LRU: the Least Recently Used page is swapped out.) If a page is swapped out and then is referenced, it is swapped back in, from the swap area, at the expense of another page. Virtual memory enables each process to act as if it has the whole memory space to itself, since the addresses that it uses to reference memory are translated by the virtual memory mechanism into different addresses in physical memory. This allows different processes to use the same memory addresses - the memory manager will translate references to the same memory address by two different processes into different physical addresses. One process generally has no way of accessing the memory of another process. A process may use an address space larger than the available physical memory, and each reference to an address will be translated into an existing physical address. The bound on the amount of memory that a process may actually address is the size of the swap area, which may be smaller than the addressable space. (A process can have an address space of 4GB yet actually use only 2GB, and this can run on a machine with a page file of 2GB.) The size of the virtual memory on a system is smaller than the sum of the physical RAM and the swap area, since pages that are swapped in are not erased from the swap area, and so take up two pages of the sum of sizes. Usually under Windows, the size of the swap area is 1.5 times the size of the RAM. Virtual memory makes application programming easier by hiding fragmentation of physical memory; by delegating to the kernel the burden of managing the memory hierarchy (eliminating the need for the program to handle overlays explicitly); and, when each process is run in its own dedicated address space, by obviating the need to relocate program code or to access memory with relative. Virtual memory is an integral part of computer architecture; implementations require hardware support, typically in the form of a memory management unit built into the CPU. While not necessary, emulators and virtual

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machines can employ hardware support to increase performance of their virtual memory implementations.Consequently, older operating systems, such as those for the mainframes of the 1960s, and those for personal computers of the early to mid-1980s (e.g. DOS) generally have no virtual memory functionality.

Address space and Memory space

The purpose of virtual memory is to enlarge the address space, the set of addresses a program can utilize. An address used by a programmer will be called a virtual address, and the set of such address the address space. An address in main memory is called a location or physical address. The set of such location is called the memory space. Thus the address space is the set of addresses generated by programs as they reference instructions and data; the memory space consists of the actual main memory location directly addressable for processing. The address space is allowed to be larger than the memory space in computers with virtual memory. In a multiprogramming computer system, programs and data are transferred to and from auxiliary memory and main memory based on demands imposed by the CPU. Suppose that program 1 is currently being executed in the CPU. Program 1 and a portion of its associated data are moved from auxiliary memory into main memory as shown in below figure.

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Portions of programs and data need not be in contiguous locations in memory since information is being moved in and out, and empty spaces may be available in scattered locations in memory. The address field of an instruction code has a sufficient number of bits to specify all virtual addresses.CPU will reference instructions and data with a address bit, but the information at this address must be taken from physical memory because access to auxiliary storage for individual words will be prohibitively long. Following figure is the mapping table:
Virtual address Memory Mapping Table Main Memory

Virtual address register (20

Main memory address register (15 bits)

Memory table buffer register

Main Memory buffer register

The mapping is dynamic operation, which means that every address us translated immediately as a word is referenced by CPU. The mapping table may be stored in a separate memory as shown is above figure or in main memory. In the first case, an additional memory unit is required as well as one extra memory access time. In the second case, the table takes space from main memory and two accesses to memory are required with the program running at half speed. A third alternative is to use an associative memory.

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Address Mapping Using Pages

When the system's RAM is too busy, the computer's processor moves the processes that are idle to space on the hard drive. This is known as paging, and the files that are created in the virtual memory space are called page files.As the computer's RAM becomes free, the processor moves the page files out of the virtual memory space into RAM. The memory management unit (MMU) is responsible for keeping track of where these files are relocated. This connecting of virtual addresses to physical address is called address mapping. Part of the MMU's memory contains a table for mapping addresses. This table is known as the translation look-aside buffer (TLB). This helps the processor keep track of page files as they are swapped to the physical memory. Paging is one of the popular memory management schemes to implement such virtual memory management. Paging stipulates that main memory is partitioned into frames of sufficiently small sizes. The table implementation of the address mapping is simplified if the information in the address space and the memory space are each divided into groups of fixed size. The physical memory us broken down into groups of equal size called blocks, which may range from 64 to 4096 words each. The term page refers to groups of address space of the same size. A page refers to the organization of address space, while a block refers to the organization of memory space.

Consider a computer with an address space of 8k and a memory space of 4k. If we split each into groups of 1k words we obtain eight pages and four blocks as shown in below figure.

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The mapping from address space to memory space is facilitated if each virtual address is considered to be represented by two numbers: a page number address and a line within the page. In a computer with 2p words per page, P bits are used to specify a line address and the remaining high-order bits of the virtual address specify the page number. In the example of the above figure, a virtual address has 13 bits. Since each page consists of 210 = 1024 words, the high-order three bits of virtual address will specify one of the eight pages, and the low-order 10 bits give the line address within the page. The organization of the memory mapping table in a paged system is shown in the given figure.

The memory-page table consists of eight words, one for each page. The address in the page table denotes the page number and the content of the word gives the block number where that page is stored in main memory. The table shows that pages 1,2,5, and 6

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are now available in main memory block 3,0,1 and 2 respectively. A presence bit in each location indicates whether the page has been transferred from auxiliary memory into main memory. A 0 in presence bit indicates that this page is not available in main memory. The CPU references a word in memory with a virtual address of 13 bits. The three high-order bits of the virtual address specify a page number and also an address for the memory-page table. The content of the word in the memory page table at the page number address is read out into the memory table buffer register. If the presence bit is a 1, the block number thus read is transferred to the two high-order bits of the main memory address register. The line number from the virtual address is transferred into the 10 low-order bits of the memory address register. A read signal to main memory transfers the content of the word to the main memory buffer register ready to be used by the CPU. If the presence bit in the word read from the page table is 0, it signifies that the content of the word referenced by the virtual address does not reside in main memory. A call to the operating system is then generated to fetch the required page from auxiliary memory and place it into main memory before resuming computation.

Page Replacement

A virtual memory system is a combination of hardware and software techniques. The page replacement system consists of: 1. Which page in main memory ought to be removed to make room for a new page 2. When a new page is to be transferred from auxiliary memory to main memory 3. Where the page is to be placed in main memory. When a program starts execution, one or more pages are transferred into main memory and the page table is set to indicate their position. The program is executed from main memory until it attempts to reference a page that is still in auxiliary memory. This condition is called page fault. When page fault occurs, the execution of the present program is suspended until the required page is brought into main memory. When a page fault occurs in a virtual memory system, it signifies that the page referenced by the CPU is not in main memory. A new page is then transferred from auxiliary memory to main memory. If main memory is full, it would be necessary to remove a page from a memory block to make room for the new page. The policy for choosing pages to remove is determined from the replacement algorithm that is used. The replacement policies are based on the way the processes use page frames. Common replacement algorithms used are the following: 1. FIFO policy: This policy simply removes pages in the order they arrived in the main memory. Using this policy we simply remove a page based on the time of its arrival in the memory. Each time a page is loaded into memory, its identification number is pushed into a FIFO stack. When a new page must be loaded, the page least recently

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brought is removed. The page to be removed is easily determined because its identification number is at the top of the FIFO stack. 2. LRU policy: LRU expands to least recently used. This policy is more difficult to implement but has been more attractive on the assumption that the least recently used page is a better candidate for removal than the least recently loaded page as in FIFO. This policy suggests that we remove page whose last usage us farthest from current time. When a page is referenced, its associated counter is set to zero. At fixed intervals of time, the counters associated with all page presently in memory are incremented by 1. The least recently used page is the page with the highest count. The counters are often called aging registers, as their count indicates their age, that is , how long ago their associated pages have been referenced.

Memory Management Hardware

A memory management system is a collection of hardware and software procedures for managing the various programs residing in memory. Here we are concerned with the hardware unit associated with the memory management system. The basic components of a memory management unit are: 1. A facility for dynamic storage relocation that maps logical memory references into physical memory addresses 2. A provision for sharing common programs stored in memory by different users 3. Protection of information against unauthorized access between users and preventing users from changing operating system functions The fixed page size used in the virtual memory system causes certain difficulties. It is more convenient to divide programs and data into logical parts called segments. A segment is a set of logically related instructions or data elements associated with a given name. Segments may be generated by the programmer or by the operating system. The sharing of common programs is an integral part of multiprogramming system. The third issue in multiprogramming is protecting one program from unwanted interaction with another. An example of unwanted interaction is one user's unauthorized copying of another user's program. The address generated by a segmented program is called a logical address. This is similar to a virtual address except that logical address space is associated with variable -length segments rather than fixed-length pages. The logical address may be larger or equal to the physical memory address as in virtual memory. Each segment has protection information associated with it. Shared programs are placed in a unique segment in each user's logical address space so that single physical copy can be shared. The function of the memory

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management unit is to map logical addresses into physical addresses similar to the virtual memory mapping concept.

Segmented Page Mapping

Like paging, segmentation is also a scheme which supports virtual memory. The property of logical space is that it uses variable-length segments. The length of each segment is allowed to grow and contract according to the needs of the program being executed. One way of specifying the length of a segment is by associating with it a number of equal-size pages.In a segmented memory management system the blocks to be replaced in main memory are potentially of unequal length and correspond to program and data ``segments.'' A program segment might be, for example, a subroutine or procedure. A data segment might be a data structure or an array. In both cases, segments correspond to logical blocks of code or data. Segments, then, are ``atomic,'' in the sense that either the whole segment should be in main memory, or none of the segment should be there. The segments may be placed anywhere in main memory, but the instructions or data in one segment should be contiguous, as shown in Figure:

Fig: A segmented memory organization Using segmented memory management, the memory controller needs to know where in physical memory is the start and the end of each segment. When segments are replaced, a single segment can only be replaced by a segment of the same size, or by a

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smaller segment. After a time this results in a ``memory fragmentation'', with many small segments residing in memory, having small gaps between them. Because the probability that two adjacent segments can be replaced simultaneously is quite low, large segments may not get a chance to be placed in memory very often. In systems with segmented memory management, segments are often ``pushed together'' occasionally to limit the amount of fragmentation and allow large segments to be loaded. This organization appears to be efficient because an entire block of code is available to the processor. Also, it is easy for two processes to share the same code in a segmented memory system; if the same procedure is used by two processes concurrently, there need only be a single copy of the code segment in memory. (Each process would maintain its own, distinct data segment for the code to access, however.) Segmented memory management is not as popular as paged memory management, however. In fact, most processors which presently claim to support segmented memory management actually support a hybrid of paged and segmented memory management, where the segments consist of multiples of fixed size blocks.

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Conclusion

Memory management is the act of managing computer memory. The essential requirement of memory management is to provide ways to dynamically allocate portions of memory to programs at their request, and freeing it for reuse when no longer needed. This is critical to the computer system. Several methods have been devised that increase the effectiveness of memory management. Virtual memory systems separate the memory addresses used by a process from actual physical addresses, allowing separation of processes and increasing the effectively available amount of RAM using paging or swapping to secondary storage. The quality of the virtual memory manager can have an extensive effect on overall system performance. So the field of memory management is very large, complex and time consuming to research and difficult to apply to practical implementations.

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Bibliography

M. Morris Mano , Computer system Architecture, Third Edition, Prentice Hall of India Hays, J. F , Computer Architecture and Organization, Second Edition, McGraw Hill William Stalling, Computer Organization And Architecture 7th Edition http://en.wikipedia.org/wiki/Computer_architecture/Memory_Organization

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