Abhishek
Department of Electrical and Computer Engineering
University of Toronto
September 5, 2012
Abhishek Incremental Power Grid Verication 1 / 32
Outline
1
Introduction
Vectorless Verication
Incremental Grid Verication
Contributions
2
Background
RC Grid Verication
RLC Grid Verication
Model Order Reduction
3
Proposed Approach
Efcient Bounds
Macromodeling
Results
4
Extensions
Dimensionality Reduction
Chip Power Model
5
Conclusions
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Introduction Vectorless Verication
The Need
Modern integrated circuits (IC) designs are susceptible to supply
voltage uctuations:
Reduced supply voltage levels
Increase in active and leakage currents
Traditional verication ows based on circuit simulation has
serious drawbacks:
Number of traces to cover the space of voltage drops is intractable
Require complete knowledge of current waveforms
Grid verication should be done early in the design ow
Solution:
A vectorless and early power grid verication approach
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Introduction Vectorless Verication
Constraintsbased Verication
Vectorless approach based on partial current specications
Current constraints are used to capture uncertainty about circuit
behavior
Grid verication is reduced to nding worstcase voltage drop over
all possible currents satisfying the constraints
Two types of constraints:
Local constraints: upper bounds on individual current sources
Global constraints: upper bounds on sums of groups of currents
Combined together, local and global constraints form a feasible
space of currents F
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Introduction Incremental Grid Verication
Motivation
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Grid verication requires solving a linear program (LP) for every
node
Verication of the entire grid can become overkill:
Large size of modern power grids
Design changes made to local region of previously veried grid
need to be analyzed
Cases like IP reuse, where a portion of grid need not be veried
Incremental Power Grid Verication becomes a necessity!!!
Introduction Incremental Grid Verication
Introducing Incremental Verication
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User identies part of the grid,
that need not be veried,
referred to as subgrid
Verication is required for nodes
outside the subgrid, also known
as external nodes
Nodes inside the subgrid can
either be port or internal nodes:
Port nodes connect the
subgrid to external nodes
All other subgrid nodes are
internal nods
Introduction Contributions
Incremental Vectorless Verication
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A technique for incremental vectorless verication for R grids
was proposed by Kouroussis et al. [ICCAD 05]
In this work, incremental vectorless verication is extended to
the transient case through the following two contributions:
Efcient computation of upper bounds on worstcase voltage
drops at internal nodes
Macromodeling of the internal grid section by:
Adapting multiport Nortons theorem proposed in HiPRIME by
Lee et al. [TCAD 05] to our verication framework
Combining moment matchingbased reduction by Liao and
Dai [ICCAD 95] with node eliminationbased reduction proposed
by B. Sheehan [TCAD 07] to reduce the resultant passive RC
circuit
Background RC Grid Verication
Grid Model
Abhishek Incremental Power Grid Verication 8 / 32
g
c
g
g
c
g g
g
g
c c
V
dd
i
(s,1)
(t)
c
g
c
g g g
g
c c c
g g
c
g g g
c c
g
i (t)
(s,2)
System equation:
Gv(t ) +C
v(t ) = i (t )
Background RC Grid Verication
Verication
Applying a nitedifference approximation to RC system equation:
Av(t ) =
C
t
v(t t ) + i (t )
where
A = G+
C
t
An upper bound on the worstcase voltage drop vector was
proposed by Ferzli et al. [ICCAD 07]:
v
ub
=
_
I +G
1 C
t
_
V
a
where V
a
is the worstcase voltage drop vector at t = t in the
special case when i (t ) = 0, t 0 and is expressed as:
V
a
= emax
i F
(A
1
i )
with emax being an operator to perform elementwise
maximization of its vector argument.
Abhishek Incremental Power Grid Verication 9 / 32
Background RLC Grid Verication
Grid Model
Abhishek Incremental Power Grid Verication 10 / 32
g
i
(s,1)
(t)
g
l g
c
g g
g
V
dd
g
l g
l
c
g g
c c i (t)
(s,2)
c
g g
c c c
l g
g g
c
g g
c c c
g
System equations:
Gv(t ) +C
v(t ) Mi (t ) = i
s
(t )
M
T
v(t ) +L
i (t ) = 0
Background RLC Grid Verication
Verication
The RLC grid can be transformed into a reduced circuit by
eliminating the inductive branch currents as proposed by Abdul
Ghani et al. [TCAD 11]
v(t ) = D
1
Ev(t t ) +D
1
i
s
(t )
where D =
_
G+
C
t
+M
L
t
1
M
T
_
and E =
_
C
t
+M
G
_
To compute the bounds at innity, upper and lower bounds on
voltage drops for r time steps ahead in time are computed and are
given by:
w
r
= w
r 1
+ eopt
i
s
F
[(D
1
E)
r 1
D
1
i
s
]
The upper and lower bounds at innity are now given by:
_
v
ub
()
v
lb
()
_
= (I R)
1
w
r
where R is composed of N and elementwise absolute values of
the entries in N.
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Background Model Order Reduction
RC MOR
A large RC interconnect network is partitioned into smaller
subnetworks
Admittance matrix looking into the ports is approximated using the
rst two order moments as:
Y(s) M
0
+M
1
s
where M
0
and M
1
are zero and rstorder moment matrices
respectively
A 2 model is constructed between each pair of ports by matching
the moments:
Circuit between pair of ports is synthesized using Tmodel
Porttoground elements are modeled using parallel RC model
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Background Model Order Reduction
Node Elimination (TICER)
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The reduction is based on the time
constant of a node
_
N
=
C
N
G
N
_
where C
N
and G
N
are respectively, the sums of
capacitances and conductances incident
on the node.
If
N
is less than a userspecied value of
time constant, the node is removed as
follows:
If nodes i and j were connected to node
N by conductances g
iN
and g
jN
, insert a
conductance
_
g
iN
g
jN
G
N
_
between i and j
If node i had a capacitor c
iN
and j had a
resistor g
jN
, insert a capacitor
_
c
iN
g
jN
G
N
_
between i and j
port  i
C
R
ij2
R
ij1
ij
port  j
Tmodel
ii
port  i R
ii
C
parallel RC model
Proposed Approach Efcient Bounds
Estimating Internal Nodes Voltage Drops
Partitioned system equation:
_
_
G
11
G
12
0
G
T
12
G
22
G
23
0 G
T
23
G
33
_
_
_
_
v
ext
(t )
v
prt
(t )
v
int
(t )
_
_
+
_
_
C
ext
0 0
0 C
prt
0
0 0 C
int
_
_
_
_
v
ext
(t )
v
prt
(t )
v
int
(t )
_
_
=
_
_
i
s,ext
(t )
i
s,prt
(t )
i
s,int
(t )
_
_
An upper bound on v
ub
can be found as:
v
ub
_
I +G
1 C
t
_
_
_
I
ext
0 0
0 I
prt
0
0 T
T
A
1
int
_
_
emax
i
s
F
_
_
v
ext
(t )
v
prt
(t )
i
s,int
(t )
_
_
Because emax
i
s
F
(i
s,int
(t )) = i
L,int
(vector of local constraint values
for internal current sources), computing an upper bound on v
ub
requires:
Solving LPs for external and port nodes,
Standard system solve
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Proposed Approach Macromodeling
Norton Equivalent Current Sources
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To nd Norton equivalent currents at port nodes that will
replace the internal current sources:
Disconnect the subgrid from rest of the grid
Connect each port node to ground
Evaluate current owing through short circuits
Proposed Approach Macromodeling
Modied Grid
System equation for the isolated subgrid with port nodes
connected to ground:
G
33
v
int
(t ) +C
int
v
int
(t ) = i
s,int
(t )
Current through port node to ground will be given by:
i
(t ) = G
23
v
int
(t )
Using the special case used to dene V
a
, the voltage at time
t = t in this modied grid will be given by:
v(t ) = A
1
Ji
s
(t )
where
J =
_
_
I
ext
0 0
0 I
prt
T
0 0 0
_
_
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Proposed Approach Macromodeling
Reducing the Passive Subgrid
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After moving internal current sources to port nodes, we are left
with a passive RC internal network:
To reduce the passive network:
RC MOR to give porttoport connections using Tmodel and
parallel RC model
Node elimination on every new internal node generated by the
Tmodel
Conductance values smaller than a threshold are removed by
setting those entries to 0
Proposed Approach Macromodeling
Verication after Macromodeling
New system matrices:
G =
_
_
G
11
G
12
0
G
T
12
G
22
G
23
0
G
T
23
G
33
_
_
,
C =
_
_
C
ext
0 0
0
C
prt
0
0 0
C
int
_
_
Reduced size:
n = n
ext
+ n
prt
+
n
int
Voltage at time t = t for the reduced grid:
v(t ) =
A
1
Ji
s
(t )
Upper bound on worstcase voltage drop:
v
ub
=
_
I +G
1 C
t
_
_
_
I
ext
0 0
0 I
prt
0
0 T
T
A
1
int
_
_
_
_
emax
i
s
F
(
v
ext
(t ))
emax
i
s
F
(
v
prt
(t ))
i
L,int
_
_
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Proposed Approach Results
Experimental Setup
A C++ implementation was written to test the proposed approach
Test grids were generated from user specications:
Grid dimensions
Metal layers, pitch and width per layer
Supply voltage sites and current source distribution
Consistent with 1.1 V 65nm CMOS technology
SPAI (Abdul Ghani et al. [DAC 09]) was used to compute
approximate inverse
Computations were done using a 2.6 GHz Linux machine with
24Gb of RAM
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Proposed Approach Results
Experimental Results
1
= 0.1mV
2
= 0.01mV = 5ps = 5 10
3
F =
_
i
s
: i
s
F, for which i
s
= (
Ji
s
)
_
where = n
ext
+ n
prt
and the notation 
v
ub
=
_
I +G
1 C
t
_
_
_
I
ext
0 0
0 I
prt
0
0 T
T
A
1
int
_
_
_
emax
i
F
(
A
1

s
)
i
L,int
_
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Extensions Dimensionality Reduction
Dening
F
1
= 0.1mV
2
= 0.01mV = 5ps = 5 10
3
w
r ,prt
_
=
_
w
r 1,ext
w
r 1,prt
_
+ eopt
i
r t
[((
D
1
E)
r 1
D
1
)
s
]
_
w
r ,int ,max
_
A
1
int
C
int
t
_
r 1
A
1
int
i
L,int
+T
T
r t
w
r ,prt ,max
w
r ,int ,min
T
T
r t
w
r ,prt ,min
_
where i
s
is the vector of modied current source conguration,
r t
is an approximation for the new feasible space at t = r t
with the transformation matrix given by:
T
r t
= G
23
_
A
1
int
C
int
t
_
r 1
A
1
int
A
int
T
T
r t
=
C
T
int
t
T
T
(r 1)t
T
r t
can be computed iteratively by using the above relation
Abhishek Incremental Power Grid Verication 28 / 32
Extensions Chip Power Model
Experimental Results
1
= 0.1mV
2
= 0.01mV = 5ps = 5 10
3