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1. INTRODUCTION

Microelectronics relates to the study and manufacture (or micro fabrication) of very small electronic designs and components, usually in the micrometre-scale or even smaller. These devices are mainly made from semiconductor materials. These include transistors, capacitors, resistors and diodes; inductors are excluded for practical purposes. An integrated circuit or monolithic integrated circuit (also referred to as IC chip or microchip) is an electronic circuit manufactured by lithography, or the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material. Although other materials can be used, ICs are usually fabricated on wafers of single-crystal silicon. The basic idea of IC fabrication is to implement several devices at micron level on a silicon wafer so as to reduce the size of the overall circuit drastically and in a way such that the devices perform accurately within the circuit. The number of devices that can be added to the silicon wafer depends on the number of active zones created on the wafer by the IC fabrication steps. Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. It is a technology that can be harnessed for various applications covering analog, digital and mixed signal electronics. As an effect of advances in the world of computers, there has been a dramatic proliferation of tools that can be used to design VLSI circuits. Alongside, obeying Moore's law, the capability of an IC has increased exponentially over the years, in terms of computation power, utilisation of available area and yield. The combined effect of these advances is that people can now put diverse functionality into the IC's, opening up new frontiers. Examples are embedded systems, where intelligent devices are put inside everyday objects, and ubiquitous computing where small computing systems are incorporated at very minute levels.

2. EVOLUTION OF ICS
The invention of the transistor by William B. Shockley, Walter H. Brattain and John Bardeen of Bell Telephone Laboratories was followed by the development of the Integrated Circuit (IC). The very first IC emerged at the beginning of 1960 and since that time there have already been four generations of ICs: SSI (small scale integration), MSI (medium scale integration), LSI (large scale integration), and VLSI (very large scale integration). Now we are beginning to see the emergence of the fifth generation, ULSI (ultra large scale integration) which is characterized by complexities in excess of 3 million devices on a single IC chip. Further miniaturization is still to come and more revolutionary advances in the application of this technology must inevitably occur.

A few important dates: 1947: John Bardeen, Walter Brattain and William Schokley at Bell Laboratories, built the first working point contact transistor (Nobel Prize in Physics in 1956) 1958: Jack Kylby built the first integrated circuit flip flop at Texas Instruments (Nobel Prize in Physics in 2000) 1925: Julius Lilienfield patents the original idea of field effect transistors 1935: Oskar Heil patents the first MOSFET 1963: Frank Wanlass at Fairchild describes the first CMOS logic gate (nMOS and pMOS)

Over the past several years, Silicon CMOS technology has become the dominant fabrication process for relatively high performance and cost effective VLSI circuits. The revolutionary nature of this development is indicated by the way in which the number of transistors integrated in circuits on a single chip has grown as indicated in figure below.

FIG: 2.1

Moores Law : In 1963 Gordon Moore predicted that as a result of continuous miniaturization transistor count would double every 18 months. His prediction is popularly known as Moores Law.

3. ADVANTAGES OF INTEGRATED CIRCUITS OVER DISCRETE CIRCUITS

The integrated circuits offer numerous advantages over discrete circuits. A few of them are:

1. Extremely small size- thousand times smaller than discrete circuits. 2. Very small weight owing to miniaturised circuit. 3. Very low cost because of simultaneous production of hundreds of similar circuits on a small silicon wafer. 4. More reliable because of elimination of soldered joints and needs for fewer interconnections. 5. Low power consumption because of their smaller size. 6. Easy replacement as it is more economical to replace them than to repair them. 7. Increased operating speeds because of absence of parasitic capacitance effect. 8. Close matching of components and temperature coefficient because of bulk production in batches. 9. Improve functional perform as more complex circuits can be fabricated for achieving better characteristics. 10. Greater ability of operating at extreme temperature. 11. Suitable for small signal operation because of no chance of stray electrical pickup as various components of IC and located very close to each other on a silicon wafer. 12. No component project above the chip surface in an IC as all the components are formed within the chip.

4. LIMITATIONS OF INTEGRATED CIRCUITS

The integrated circuits have a few limitations. They are:

1. In an IC the various components are part of a small semiconductor chip and the individual components cannot be removed or replace, therefore if any components of an IC fails then the whole IC has to be replaced by a new one. 2. Limited power rating as it is not possible to manufacture high power ICs. 3. Need of connecting inductors and transformers exterior to semiconductor chip as it is not possible to fabricate inductors and transformers on the semiconductor chip surface. 4. Operations as low voltage as ICs function at fairly low voltage. 5. Quite delicate in handling at these cannot withstand rough handling or excessive heat. 6. Need for connecting capacitor exterior to the semiconductor chip as it is neither convenient nor economical to fabricate capacitance exceeding 30pF. 7. Low temperature coefficient is difficult to achieve. 8. Difficult to fabricate an IC with low noise. 9. Large value of saturation resistance of transistor. 10. Voltage dependence of capacitors and resistors. 11. The diffusion process and other related procedure used in fabrication process are not good enough to permit a price control of the parameter values for the circuit elements.

5. MOS TRANSISTOR

The MOS Field Effect Transistor (MOSFET) is the fundamental building block of MOS and CMOS digital integrated circuits. Compared to the bipolar junction transistor (BJT), the MOS transistor occupies a relatively smaller silicon area, and its fabrication involves fewer processing steps. These technological advantages, together with the relative simplicity of MOSFET operation, have helped make the MOS transistor the most widely used switching device in LSI and VLSI circuits.

5.1. ADVANTAGES OF MOS OVER BJT

1. BJT is current control device but MOS is a voltage control device. 2. The BJT makes use of the injection of minority carriers across a forward biased junction while MOS depends on the control of the junction depletion width under reverse bias. 3. MOS can easily be placed in parallel but bipolar cannot unless external emitter resistors are added. The external resistance generates additional efficiency and voltage drop losses. 4. In BJT "thermal runaway" occurs easily but in FET it never occurs. 5. BJT operates by the injection and collection of minority carriers, in this device both holes and electrons take part in conduction so this device is called bipolar device but MOS is a majority carrier device so it is called unipolar device. 6. FET is smaller in size than BJT of same rating. That means at the place of 10 BJT we can use 90 FETs. So area consumption is less. 7. BJT is unilateral device as emitter is very heavily doped compared to collector, hence emitter and collector cannot be interchanged and current flows only in one direction. On the other hand MOSFET is bilateral device as source and drain can be interchanged and so current flows in both directions. 8. In BJT current flow is due to diffusion while in MOSFET current flows due to drift.

9. In BJT the collector junction resistance decreasing (collector current increasing) with temperature raise. Due to the higher temperature & current transistor will damage quickly. In FET drain resistance increasing (drain current decreasing) with increasing temperature. Due to this property it will not damage easily. We can say from the above two statements FET is more temperature stable. FET can use in higher temperature applications. 10. The MOS transistors have higher input impedance compared to that of a BJT.And also from integration point of view MOS transistors provides higher packing density compared to BJT. So ICs made by MOS transistor can be smaller. 11. MOSFETs are less noisy than BJTs. In an electronics context noise refers to random interference in a signal. When a transistor is used to amplify a signal the internal processes of the transistor will introduce some of this random interference. BJTs generally introduce more noise into the signal than MOSFETs. This means MOSFETs are more suitable for signal processing applications or for voltage amplifiers. 12. MOSFETs have higher input impedance than BJTs. The input impedance is a measure of the resistance of the input terminal of the transistor to electrical current. When designing voltage amplifiers it is desirable for the input resistance to be as high as possible. Therefore MOSFETs are more widely used in the input stage of voltage amplifiers. 13. Unlike Bipolar junction transistor, an FET virtually needs no input current. Field effect devices are controlled by an electric field (or voltage) and give extremely high input impedance and this is considered as one of the most important advantages over BJTs.

5.2. MOS TRANSISTOR STRUCTURE

FIG: 5.1: Basic n-channel MOSFET Stucture

The basic structure of an n-channel MOSFET is shown in figure above. Although the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B) terminals, the body (or substrate) of the MOSFET often is connected to the source terminal( internally ) making it a three-terminal device. MOSFETS are of two types mainly enhancement type (E-MOSFET) and depletion type (DE-MOSFET). A MOS transistor which has no conducting channel region at zero gate bias is called an enhancement-type MOSFET. If a conducting channel already exists at zero gate bias the device is called a depletion-type MOSFET.

5.3. MOS TRANSISTOR OPERATION

SOURCE

DRAIN

n+

CHANNEL LENGTH ,L

n+

SUBSTRATE ( Si)

FIG: 5.2: Physical Structure of an n- channel enhancement type MOSFET

The basic structure of an n-channel E-MOSFET is shown in figure above. It is a four terminal device which consists of a p type substrate , in which two n + diffusion regions , the drain and the source are formed. The surface of the substrate region between the drain and the source is covered with a thin oxide layer, and the metal (or polysilicon) gate is deposited on top this gate dielectric. The two n+ regions will be the current conducting terminals of this device. the device structure is completely symmetrical with respect to the drain and source regions; the different roles of these two regions will be defined only in conjunction with the applied terminal voltages and the direction of the current flow. A conducting channel will eventually be formed through applied gate voltage in the section of the device between the drain and the source diffusion regions. The distance between the drain and source diffusion regions is the channel length L, and the lateral extent of the channel (perpendicular to the length dimension) is the channel width W. Both the charnel length and the channel width are important parameters which can be used to control some of the electrical properties of the MOSFET. The thickness of the oxide layer covering the channel region, tOX is also an important parameter.

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In a MOSFET with p-type substrate and with n+ source and drain regions, the channel region to be formed on the surface is n-type. Thus, such a device with p-type substrate is called an nchannel MOSFET. In a MOSFET with n-type substrate and with p+ source and drain regions, on the other hand, the channel is p-type and the device is called a p-channel MOSFET.

FIG: 5.3: Circuit Symbol Of n and p type enhancement type MOSFET

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5.4. CHANNEL FORMATION IN MOSFET (N-CHANNEL)

FIG: 5.4: The Process of Channel Formation

(a) Formation of the Depletion Region (b), (c) Formation of the Inversion Layer

Depletion Layer Formation

When a small positive gate to source voltage is supplied to the gate electrode, a positive charge induced in the gate electrode, inducts the same amount of negative charge at the oxide silicon interface (P-body region, which is underneath the gate oxide). The holes here are pushed into the semiconductor bulk by an electric field. It exposes the negatively charged acceptors and a depletion layer is formed.

Formation Of inversion Layer

As the positive gate to source voltage increases (refer to Figure (b), (c)) the depletion region becomes wider towards the body, and begins to drag the free electrons to the interface. These free electrons are created by thermal ionization. The free holes, created with free electrons, are pushed into the semiconductor bulk. The holes that have not been pushed into

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the bulk are neutralized by the electrons that have been dragged by the positive charge of the holes from the n+ source. If the supplied voltage keeps increasing, the density of the free holes of the body, and the free electrons of the interface becomes equal. At this point, the free electron layer is called an INVERSION LAYER. This inversion layer enables the current flow as it becomes the conductive pass(=channel) of the MOSFETs drain and source. Threshold voltage: The gate-to-source voltage, at which the inversion layer is formed, is called threshold voltage, Vth.

5.5. CURRENT-VOLTAGE CHARACTERISTICS OF A MOSFET

5.5.1. Output characteristics:

Plot of ID versus VDS for several values of VGS.

FIG: 5.5: Output Characteristics on n-channel MOSFET

The output characteristics can be divided into three regions: OHMIC REGION: A constant resistance region. If the drain-to-source voltage is zero, the drain current also becomes zero regardless of gateto-source voltage.This region is at the left side of the VGS VGS(th) = VDS boundary line(VGS VGS(th) > VDS > 0). Even if the drain current is very large, in this region the power dissipation is maintained by minimizing VDS(on).

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SATURATION (OR ACTIVE) REGION: A constant current region. It is at the right side of the VGS VGS(th) =VDS boundary line. Here, the drain current differs by the gatetosourcevoltage, and not by the drain-to-source voltage. Hence, the drain current is called saturated.

CUT-OFF REGION: When the gate-to-source voltage,VGS is lower than the threshold voltage Vth , then the drain current I D =0 for any VDS . The values of the corresponding drain currents (as observed from the curve) are For saturated stste: Id=[ nCOXW(Vgs Vth)2] /(2L) For non-saturated state: Id=[ nCOXW{2(Vgs Vth)Vds-Vds2}] /(2L)

5.5.2. TRANSFER CHARACTERISTICS

Plot of ID versus VGS (NMOS)

FIG: 5.6.(a): Transfer Characteristics Of n-type MOSFET

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Plot of ID versus VGS (PMOS)

FIG: 5.6.(b): Transfer Characteristics Of P-type MOSFET

The transfer characteristic relates drain current (ID) response to the input gate-source driving voltage (VGS). Since the gate terminal is electrically isolated from the remaining terminals (drain, source, and bulk), the gate current is essentially zero, so that gate current is not part of device characteristics. The transfer characteristic curve can locate the gate voltage at which the transistor passes current and leaves the OFF-state. This is the device threshold voltage (Vtn).

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6. IC FABRICATION
There are 5 major steps in the process of IC fabrication: 1. Cleaning. 2. Oxidation. 3. Photolithography. 4. Diffusion. 5. Metallization.

6.1.

CLEANING

The main aim of this process is to remove any type of impurities that may be present in the silicon wafer. There are basically two ways of carrying out this process: Acid process cleaning. Plasma dry cleaning.

The most common impurities that may be present in the sample are Dust particles Oil and grease Inorganic compounds. Organic compounds (Acidic or alkaline). Oxides (SiO2).

To verify that the wafer is properly cleansed or not, the Hydrophobicity of the wafer has to be tested. A clean wafer is hydrophobic, i.e.: water particles do not stick to its surface.

6.2.

OXIDATION

After the process of Cleaning, the next process which is implemented is Oxidation. There are basically two oxidation processes: Wet oxidation - Wet oxidation is non-uniform but fast and gives inferior oxides compared to dry oxidation. Field oxides can be made using wet oxidation. Dry oxidation - Dry oxidation is uniform but slow and gives better oxides compared to wet oxidation. Gate oxides can be made using wet oxidation.

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6.3.

PHOTOLITHOGRAPHY

Photolithography (also termed "optical lithography" or "UV lithography") is a process used in micro fabrication to selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photo mask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate. A series of chemical treatments then either engraves the exposure pattern into, or enables deposition of a new material in the desired pattern upon, the material underneath the photo resist.

Si-wafer

Si-wafer coated with oxide layer

Active zone (designed by photolithography)

The prime requirements for this process are

Mask: Lithographic photomasks are typically transparent fused silica blanks covered with a pattern defined with a chrome metal-absorbing film. A set of photomasks , each defining a pattern layer in integrated circuit fabrication, is fed into a photolithography stepper or scanner, and individually selected for exposure. Photoresist: It is light sensitive ,acid resistant organic polymer when exposed to UV rays, exposed areas become soluble so that they are no longer resistant to etching solvents. There are two types of photoresist which are used industrially:

I.

Positive photoresist-It is less sensitive to light compared to negative PR. They are initially insoluble but become soluble when exposed to UV light. Negative photoresist- : It is more sensitive to light. They are initially soluble and become insoluble after exposure to UV light.

II.

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Diagrammatically, the steps of Photolithography are as shown below:

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FIG:6.1 : Flow Process Of Photolithography

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6.4.

DIFFUSION

FIG:6.2 : Diffusion Process

The diffusion process begins with the highly polished silicon wafer being placed in a furnace having a concentration impurity made up of impurity atoms which yield the desired electrical characteristics. The concentration of impurity atoms is diffused into the wafer and is controlled by controlling the temperature of the furnace and the time that the silicon wafer is allowed to remain in the furnace. This process is termed as DOPING. When the wafer has been uniformly doped, the fabrication of semiconductor devices may begin. For n-type, Phosphorus oxy-chloride (POCl3) is used and for P-type, the compound used is Boron nitrite. Generally Boron nitrite is more preferred over POCl3 because of the nature of POCl3 is that it is very volatile and explosive and hence, it has to be stored in ice. Such problems do not arise with boron-nitrite. ION IMPLANTATION: It is a process in which dopant ions are implanted into the Si substrate by means of an ion beam. Here implantation energy lies between 1Kev and 1 Mev. The advantage of ion implantation is precise control and lower processing temperature compared with those of other diffusion process.

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6.4.1. REQUIREMENTS FOR DIFFUSION:

Temperature- It depends on the type of the boron-cake (solid boron-nitrite). Experimentally, the particles of boron are ejected from the boron-cake at a high temperature Gases- O2 and N2

6.4.2. STEPS OF DIFFUSION:

PREDIP: In this process, N2 is applied which takes the boron from the boron nitrite and deposits it in the gap between the silicon crystals. Due to this, the upper part of the wafer comprises of the boron particles while Si accumulates in the lower part. The whole process is carried out in N2 ambient atmosphere.

FIG: 6.3 :PREDIP

DIVING: Firstly, the boron cake is removed from the furnace. Then at a high temperature, O2 is applied. Silicon pushes the boron particles downwards trying to react with the O2. Even though a simultaneous reaction does not take place between the Si and O2, Boron silicate forms by the mutual reaction of boron, oxygen and silicon.

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FIG: 6.4 : DIVING

The boron silicate forms a layer over the wafer. ETCHING: In this step, the boron silicate layer is removed from the wafer. Finally, a wafer is obtained which is P-type on one side and N-type on the other side.

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6.4.3. VERIFICATION OF P-TYPE/N-TYPE: HOT PROBE METHOD

FIG: 6.5 :Hot Probe Method

The two multimeter probes are made to touch the silicon wafer such that both the positive and negative ends are close to each other. A voltmeter is connected between both the ends of the multimeter. A hot probe (eg: a soldering iron) is brought in contact with the positive probe of the multimeter. As a result the contact surface of the multimeter and wafer heats up, kinetic energy of the holes at the proximity of the positive terminal increases and they get deflected, creating a vacuum. Electrons immediately accumulate the vacuum and due to this motion a current is developed. By observing the direction of the current, the type of the dopant on either side of the wafer can be determined. If the voltmeter shows positive voltage, it indicates N-type dopant in the wafer and if the voltmeter shows a negative voltage, it indicates P-type dopant.

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6.5. METALLIZATION
Metallization means creation of metallic contacts on the wafer of silicon, which is P-type on one side and N-type on the other side. Generally Aluminium (Al) is used as a metal contact on the P-type as it is a good ohmic conductor with the P-type and it shows a linear V-I curve. Similarly, Silver (Ag) is used as a metallic contact for N-type as silver is a good ohmic conductor with silicon wafer and shows a linear V-I characteristic curve.

The process of depositing metal contact over the silicon wafer is termed as VACUUM EVAPORATION SYSTEM. Vacuum is required in metallization for two reasons: To avoid forming of oxides by the metal, since oxides are insulators. To ensure that the mean path is free. There are four types of processes in Metallization: THERMAL EVAPORATION- It is used for metals having low melting point (like Al, Ag, Au etc.) ELECTRON BEAM- It is used for metals having high melting point (like Tungsten, Mo, Si etc.) Here, a cathode ray tube is used as a source of electron. The electrons are deflected by applying a strong magnetic field and then bombarded over the sample.

RF (RADIO FREQUENCY) - It is generally used to diffuse bimetal or metal oxide over the silicon wafer. Electrons are directly bombarded from cathode on to the anode (bimetal) which then deposits on the wafer.

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PLASMA- It is used to deposit compounds over the silicon wafer. A plasma tube having a vacuum of 10-1 to 10-2 torr is used. An inert gas like argon is passed inside the tube and high voltage is applied facilitating the flow of particles from the positive region to the negative region. Both compounds which are to be deposited on the wafer are in the gaseous form, which react and deposits over the sample.

Eg: N2O+SiH4 (silane)

SiNO3 (silicon nitrite)

In all the processes mentioned above, the basic steps of operation are similar. The only thing that differs is the power supply.

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7. FABRICATION OF THE MOS TRANSISTOR

The above five steps are implemented in the fabrication of MOS transistor as shown in the flow diagram below: (for NMOS)

Deposition of SiO2 (field oxide)

Chemical etching

Thin oxide (gate oxide forms)

FIG:7.1: Process Flow For The Fabrication Of n-type MOSFET ( cont..)

27 Deposition of polysilicon layer

Patterning and etching to form transistor gates

Etching of polysilicon layer to form source and drain junctions

Ion implantation

FIG:7.1: Process Flow For The Fabrication Of n-type MOSFET ( cont..)

Surface covered by insulating SiO2 28 layer

Patterning of insulating layer to provide gate, drain contacts

Surface covered with evaporated aluminium to form interconnects

Patterning and etching of metal layer, completing the interconnections

FIG:7.1: Process Flow For The Fabrication Of n-type MOSFET

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8. SCALING OF MOSFETS
The design of high-density chips in MOS VLSI (Very Large Scale Integration) technology requires that the packing density of MOSFETs used in the circuits is as high as possible and, consequently, that the sizes of the transistors are as small as possible. The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to as Scaling.

8.1.

BENEFITS OF MOSFET SCALING

Computing power has increased dramatically over the decades, enabled by significant advances in silicon integrated circuit (IC) technology led by the continued miniaturization of the MOS transistor. The rapid progress in the semiconductor industry has been driven by improved circuit performance and functionality together with reduced manufacturing costs. While Moores Law only describes the rate of increase in transistor density, reduction of the physical MOS device dimensions has improved both circuit speed and density in the following ways: a. Circuit operational frequency increases b. Chip area decreased, enabling higher transistor density and cheaper ICs. c. Switching power density made constant, allowing lower power per function or more circuits at the same power.

8.2.

TYPES OF SCALING:

There are two basic types of size-reduction strategies: full scaling (also called constant-field scaling) and constant voltage scaling.

8.2.1. FULL SCALING (CONSTANT-FIELD SCALING):

This scaling option attempts to preserve the magnitude of internal electric fields in the MOSFET, while the dimensions are scaled down by a factor of S. To achieve this goal, all potentials must be scaled down proportionally, by the same scaling factor. The aspect ratio of W/L however, remains fixed. The effect on various physical quantities after scaling is as depicted below:

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Quantity
Channel Length Channel width Gate Oxide Thickness Junction Depth Power Supply Voltage Threshold Voltage Doping Densities

Before Scaling
L W tox xj VDD Vth NA ND

After Scaling
L/ =L/S W/ = W/S tox/ = tox /S xj/ = xj /S VDD/ = VDD / S Vth/ = Vth / S NA / = S.NA ND/ = S. ND

Due to the change in above physical quantities, the gate oxide capacitance per unit area, is changed as follows.

Since all terminal voltages are scaled down by the factor S as well, the linear-mode drain current and saturation mode drain current of the scaled MOSFET can now be found as:

Since the drain current flows between the source and the drain terminals, the instantaneous power dissipated by the device (before scaling) can be found as:

After scaling, the power becomes:

This significant reduction of the power dissipation is one of the most attractive features of full scaling.

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8.2.2. CONSTANT-VOLTAGE SCALING:

While the full scaling strategy dictates that the power supply voltage and all terminal voltages are scaled down proportionally with the device dimensions, this scaling is not very practical. The circuitry may require certain voltage levels for all input and output voltages, which in turn would necessitate multiple power supply voltages and complicated level shifter arrangements. For these reasons, constant-voltage scaling is usually preferred over full scaling. In constant-voltage scaling, all dimensions of the MOSFET are reduced by a factor of S, as in full scaling. The power supply voltage and the terminal voltages, on the other hand, remain unchanged. The following tables show the effect of constant voltage scaling on different device characteristics:

Quantity
Dimensions Voltages

Before Scaling
W, L ,tox ,xj VDD

After Scaling
W/ = W/S Remain Unchanged Increases by S2 NA / = S2 . NA ND/ = S2. ND Cox / = S.Cox ID/ =S. ID P/ =S.P P/ / Area/ = S3 .( P/ Area )

Doping Densities

NA , ND

Oxide Capacitances Drain Current Power dissipation Power Density

Cox ID P P/Area

The constant-voltage scaling increases the drain current density and the power density by a factor of S3. This large increase in current and power densities may eventually cause serious reliability problems for the scaled transistor. As the device dimensions are systematically reduced through full scaling or constant- voltage scaling, various physical limitations become increasingly more prominent, and ultimately restrict the amount of feasible scaling for some device dimensions. Consequently scaling may be carried out on a certain subset of MOSFET dimensions in many practical cases.

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9. SHORT-CHANNEL EFFECTS

The MOSFET scaling i.e. .reduction in the dimensions of the MOSFET has led to some disadvantageous phenomena termed as the SHORT CHANNEL EFFECTS. A MOS transistor is called a short-channel device if its channel length is on the same order of magnitude as the depletion region thicknesses of the source and drain junctions. Alternatively, a MOSFET can be defined as a short-channel device if the effective channel length is approximately equal to the source and drain junction depth. The short-channel effects are attributed to two physical phenomena: 1. The limitation imposed on electron drift characteristics in the channel, 2. The modification of the threshold voltage due to the shortening channel length. In particular five different short-channel effects can be distinguished: 1. Drain-induced barrier lowering(DIBL) and punch-through 2. GIDL (gate induced drain leakage) 3. Velocity saturation 4. Impact ionization 5. Hot electron Effect. 6. Surface scattering. 7. Gate oxide tunneling.

9.1.

Drain-Induced Barrier Lowering (DIBL) And Punch-through

It occurs mainly due to two reasons: proximity and penetration. The current flow in the channel depends on creating and sustaining an inversion layer on the surface. If the gate bias voltage is not sufficient to invert the surface, i.e., VGS < Vth, the carriers (electrons) in the channel face a potential barrier that blocks the flow. Increasing the gate voltage reduces this potential barrier and, eventually, allows the flow of carriers under the influence of the channel electric field. This simple picture becomes more complicated in small-geometry MOSFETs, because the potential barrier is controlled by both the gate-to-source voltage VGS and the drain-to- source voltage VDS. If the drain voltage is increased, the potential barrier in the channel decreases, leading to drain-induced barrier lowering (DIBL). The reduction of the potential barrier eventually allows electron flow between the source and the drain, even if the

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gate-to-source voltage is lower than the threshold voltage. The channel current that flows under these conditions (VGS < Vth) is called the sub-threshold current. Again in small-geometry MOSFETs, the channel length is on the same order of magnitude as the source and drain depletion region thicknesses. For large drain-bias voltages, the depletion region surrounding the drain can extend farther toward the source, and the two depletion regions can eventually merge. This condition is termed punch-through. The gate voltage loses its control upon the drain current and the current rises sharply once punch-through occurs. This can cause permanent damage to the transistor by localized melting of material, punchthrough is obviously an undesirable condition, and should be prevented in normal circuit operation.

9.2.

GIDL (Gate Induced Drain Leakage)

GIDL refers to a phenomenon in which junction breakdown occurs at a much lower drain voltage than in normal cases. The breakdown is caused by gate induced high electric field in the gate-to-drain overlap region. This high electric field in the overlap region causes tunneling of electrons from valence band to conduction band releasing energy resulting in the formation of electron hole pairs. The electrons travel to the drain terminal decreasing the drain current considerably while the holes go towards the ground terminal creating an undesirable substrate leakage current (IB).

9.3.

Velocity Saturation

The performance of short-channel devices is also affected by velocity saturation, which reduces the transconductance in the saturation mode. At low E-field, the electron drift velocity in the channel varies linearly with the electric field intensity. However, as field intensity increases above 104 V/cm, the drift velocity tends to increase more slowly, and approaches a saturation value of vde(sat)=107 cm/s at around 300 K. Thus for short channel devices velocity saturation is reached at lower values of VDS (drain source voltage).

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FIG: 9.1:

9.4.

Impact Ionization

Another undesirable short-channel effect, especially in NMOS, occurs due to the high velocity of electrons in presence of high longitudinal fields that can generate electron-hole pairs by impact ionization, that is, by impacting on silicon atoms and ionizing them. It happens as follow: normally, most of the electrons are attracted by the drain, while the holes enter the substrate to form part of the parasitic substrate current. Moreover, the region between the source and the drain can act like the base of an npn transistor, with the source playing the role of the emitter and the drain that of the collector. If the aforementioned holes are collected by the source, and the corresponding hole current creates a voltage drop in the substrate, the normally reversed-biased substrate-source pn junction will conduct appreciably. Then electrons can be injected from the source to the substrate, similar to the injection of electrons from the emitter to the base. They can gain enough energy as they travel toward the drain to create new eh pairs. The situation can worsen if some electrons generated due to high fields escape the drain field to travel into the substrate, thereby affecting other devices on a chip.

9.5.

Hot Electron Effect

Another problem, related to high electric fields, is caused by so-called hot electrons. These high energy electrons can enter the oxide, where they can be trapped, giving rise to oxide charging that can accumulate with time and degrade the device performance by increasing Vth and affect adversely the gates control on the drain current. Inside the substrate, the carriers dissipate energy during successive relaxation. This energy (kinetic energy) heats up the carriers due to vibrations generating electron-hole pairs which are either collected at drain or at the substrate. These effects cause a leakage current to flow in the MOS, which is not desirable.

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FIG: 9.2: Hot Electron effect

9.6.

Surface Scattering

As the channel length becomes smaller due to the lateral extension of the depletion layer into the channel region, the longitudinal electric field component increases, and the surface mobility becomes field-dependent. Since the carrier transport in a MOSFET is confined within the narrow inversion layer, and the surface scattering (that is the collisions suffered by the electrons that are accelerated toward the interface by ex) causes reduction of the mobility, the electrons move with great difficulty parallel to the interface, so that the average surface mobility, even for small values of ey, is about half as much as that of the bulk mobility.

FIG: 9.2: Surface Scattering

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9.7.

Gate Oxide Tunnelling

According to conventional physics, if Eo is the energy of the electron and Vo is the voltage of the potential barrier, and if Eo< qVo, the electron cannot penetrate the voltage barrier. But in quantum dimensions, the electron can tunnel through the barrier if the barrier dimensions are comparable to the De-broglies wavelength even if Eo < qVo. This is called the Tunnelling effect. Hence if the source and drain are too close, then due to close proximity, the electrons tunnel through the potential barrier and causes a leakage current even before threshold voltage is reached.

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10. CMOS TECHNOLOGY IN VLSI DESIGN

Complementary metaloxidesemiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication. Frank Wanlass patented CMOS in 1967. The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips. CMOS circuits are constructed in such a way that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation

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10.1. Basic Application: CMOS Inverter

When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output therefore registers a high voltage. On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an ON (low resistance) state, allowing the output to drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage. In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behaviour of input and output, the CMOS circuits' output is the inverse of the input.

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FIG:10.1 : Voltage Transfer Characteristic Curve (CMOS Inverter)

I.

Initially input voltage is less than the threshold voltage of NMOS, so only PMOS is in ON state. This occurs in the linear region of the curve.

II.

Gradually the input voltage is increased and at a point when, input voltage=NMOS threshold, both PMOS and NMOS are on and NMOS is in saturation state. Voltage starts decreasing and a point is reached for input voltage V IL (input low) for which (dVout /dVin) = -1. This point is called the Critical Point.

III.

As voltage further decreases, PMOS goes into saturation. Hence, both PMOS and NMOS are in saturation at this instance. At point VM, both the input and output voltages are equal and a maximum current is obtained for the inverter, though temporarily.

IV.

Voltage decreases even further and NMOS start operating in the linear region of the curve. PMOS is still saturated. Another critical point is obtained for VIH (input high) at which (dVout /dVin) = -1.

V.

At point VOL (output low), NMOS is in linear region and PMOS goes into cutoff region.

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10.2.

A FEW LOGIC GATES USING CMOS

A) AND GATE

=A.B

B) OR GATE

=A+B

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C) XOR GATE

OUT =Abar.B + A.Bbar

D) BUFFER

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11. VLSI TECHNOLOGY

The number of transistors/gates that can fit in to the semiconductor die dictates the complexity of the functionality that the device can perform. The important factors that fuel the research in VLSI technology can be summarized as below: Increased functionality Higher reliability Small footprint Very low power consumption Increased speed of operation Re-programmability( except ASIC devices) Mass production Low cost Extensive use in higher IC designing processes like Embedded systems.

VLSI is thus a technology that can be harnessed for various applications covering analog, digital and mixed signal electronics. The current trend is to reduce the entire system design to a single chip solution called as system on chip (SOC). VLSI designs are mainly classified into three categories: 1. Analog: Small transistor count precision circuits such as amplifiers, data converters, filters, phase locked loops, sensors etc. 2. ASICS (Application specific integrated circuits): Progress in the fabrication of IC's has enabled us to create fast and powerful circuits in smaller and smaller devices. This also means that we can pack a lot more of functionality into the same area. The biggest application of this ability is found in the design of ASIC's. These are IC's that are created for specific purposes - each device is created to do a particular job, and do it well. The most common application area for this is DSP - signal filters, image compression etc. 3. SOC (Systems on a chip): These are highly complex mixed signal circuits (digital and analog all on the same chip). A network processor chip or a wireless radio chip is an example of an SOC.

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12. FUTURE PROSPECTS OF VLSI TECHNOLOGY

There have been many notable developments in the field of VLSI technology which has played a major role in improving the efficiency as well as vast reduction in the size of the ICs. The characteristics of a good MOSFET are that the threshold voltage (Vth), drain voltage and channel mobility is considerably low. The offstate leakage current (Ioff), the onstate current (Ion), channel conductance (gd) and transconductance (gm) are high. With recent developments in the field of IC fabrication, the undesirable short channel effects can now be minimised up to a certain extent. Performance boosters and mobility boosters help to suppress the short channel effects. Three of the most important examples are:

13. Gate engineering: Here a multigate structure is put into use. The gate is an all-round structure which is wrapped around the channel on both sides. Due to this structure, the electrons are restricted in a direction from source to drain only, thus giving a highly elevated drain-source current.

14. Channel engineering: Here suitable materials are introduced in the channel to improve the mobility of electrons across the source and drain.

15. Substrate engineering: It incorporates the use of SOI (silicon on insulator). A silicon channel layer is grown on a layer of oxide. Junction capacitance is absent in such a configuration, leading to the problems like heating effects and higher capacitance on improper biasing. To cope up with such issues, the concept of Halo doping is used where the source and drain are doped with suitable impurities.

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13.CONCLUSION

Microelectronics is defined as that area of technology associated with and applied to the realization of electronic systems made of extremely small electronic parts or elements. Application of Microelectronics has evolved from the primitive vacuum tubes and solid state devices to the ICs of modern age which are used in almost every electronic circuit today. The first semiconductor chips held two transistors each. Subsequent advances added more and more transistors, and as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known as small-scale integration (SSI), improvements in technology led to development of devices with hundreds of logic gates, known as mediumscale integration (MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and billions of individual transistors. As of early 2008, billion-transistor processors are commercially available. This is expected to become more commonplace as semiconductor fabrication moves from the current generation of 65 nm processes to the next 45 nm generations (while experiencing new challenges such as increased variation across process corners).

LARGE-SCALE INTEGRATION (LSI) and its developed version, VERY LARGE-SCALE INTEGRATION (VLSI) are the results of improvements in microelectronics production technology. In VLSI, a variety of circuits can be implanted on a wafer resulting in further size and weight reduction. ICs in modern computers, such as home computers, may contain the entire memory and processing circuits on a single substrate, containing over 2,000 logic gates or greater than 64,000 bits of memory. VLSI technology may be moving toward further radical miniaturization with introduction of NEMS (nanoelectromechanical system) technology.

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14.REFERENCES
1. Sung Mo Kang and Yusuf Leblebici ,(1996). CMOS Integrated Digital Circuits: Analysis And Design. U.S: McGraw Hill Higher Education. 2. J.B.Gupta(2010).Electronics Devices and Circuits.India : Katson . 3. Douglas A.Pucknell , Kamran Eshraghian.(2009). Basic VLSI Design. India : PHI Learning.