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INDEX S.NO 1.0 1.1 1.2 1.3 1.4 2.0 3.0 3.1 3.2 3.3 3.4 3.5 3.5.

1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 4.0 4.1 Introduction Abstract Existing system limitations Proposed system limitations Applications List of components used in the system Inverter Mosfet Mosfet operation Mosfet structure and channel formation Modes of operation of mosfet Mosfet types Dual gate mosfet Depletion mode mosfet NMOS logic Power mosfet DMOS RHBD mosfets Peripheral interface controller(PIC) Core architecture PAGE NO 3 4 4 4 4 5 5 6 10 11 13 17 17 18 19 20 21 22 22 23

4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 5.0 6.0 7 .0 8.0 9.0 9.1 9.2 10.0 10.1

Data space (RAM) Code space Word size Stacks Instruction set Performance Advantages Instruction set Compiler development Family core architectural differences Baseline core devices (12-bit) Bridge rectifier Driver circuit Filters Transformers Three phase a.c. motor Squirrel cage rotor Operation Traction Factors affecting traction

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THREE PHASE AC MOTOR USING MOSFET FOR TRACTION APPLICATIONS

1. INTRODUCTION: 1.1ABSTRACT

In this project, a Three Phase A.C motor using MOSFET is proposed. A.C Motor is the most widely used motors for appliances, industrial control, and automation. They are robust, reliable, and durable. When the power is supplied to an induction motor at the recommended specifications, it runs at its rated speed. However, many applications need variable speed operations. Recently, electronic power and control systems have matured to allow these components to be used for motor control in place of mechanical gears. These electronics not only control the motors speed, but can improve the motors dynamic and steady state characteristics. In addition, electronics can reduce the systems average power consumption and noise generation of the motor.

1.2 EXISTING SYSTEM LIMITATIONS: Traditional Induction motor control is complex due to its nonlinear characteristics. Ac motor control by using inverter is impossible. Wound DC motor is preferred in past because they were easier to control.

1.3 PROPOSED SYSTEM LIMITATIONS: Low maintenance cost It is a flexible design which allows innovations and newer technologies to be incorporated easily without incurring extra costs or necessitating changes in basic design. Fully Self-protected against faults.

1.4 APPLICATIONS: Electrical Traction. Industrial control Application. Automation.

Speed control of AC motor.

2 COMPONENTS USED IN THE PROJECT

INVERTER USING MOSFET PIC TRANSFORMERS THREE PHASE A.C. MOTOR DRIVER CIRCUIT FOR PULSE GENERATION (TRIGGERING) BRIDGE RECTIFIER FILTERS BATTERY FOR STORAGE PURPOSE

3 INVERTER: A power inverter, or inverter, is an electrical device that changes direct current (DC) to alternating current (AC); the converted AC can be at any required voltage and frequency with the use of appropriate transformers, switching, and control circuits. Solid-state inverters have no moving parts and are used in a wide range of applications, from small switching power supplies in computers, to large electric utility high-voltage direct current applications that transport bulk power. Inverters are commonly used to supply AC power from DC sources such as solar panels or batteries. The inverter performs the opposite function of a rectifier.

In this project we are using MOSFET based inverter:

Fig.3.1.three phase inverter using MOSFETs

3.1 MOSFET: The metaloxidesemiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a transistor used for amplifying or switching electronic signals. Although the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B) terminals, the body (or substrate) of the MOSFET often is connected to the source terminal, making it a three-terminal device like other field-effect transistors. When two terminals are connected to each other (short-circuited) only three terminals appear in electrical diagrams. The MOSFET is by far the most common transistor in both digital and analog circuits, though the bipolar junction transistor was at one time much more common.

Fig.3.2. (a) MOSFET showing gate, drain and source (b) MOSFET pictured with match stick for scale In enhancement mode MOSFETs, a voltage drop across the oxide induces a conducting channel between the source and drain contacts via the field effect. The term "enhancement mode" refers to the increase of conductivity with increase in oxide field that adds carriers to the channel, also referred to as the inversion layer. The channel can contain electrons (called an n-MOSFET or n-MOS), or holes (called a p-MOSFET or p-MOS), opposite in type to the substrate, so n-MOS is made with a p-type substrate, and p-MOS with an n-type substrate .In the less common depletion mode MOSFET, described further later on, the channel consists of carriers in a surface impurity layer of opposite type to the substrate, and conductivity is decreased by application of a field that depletes carriers from this surface layer. The 'metal' in the name MOSFET is now often a misnomer because the previously metal gate material is now often a layer of poly-silicon (polycrystalline silicon). Aluminum had been the gate material until the mid-1970s, when poly-silicon became dominant, due to its capability to form self-aligned gates. Metallic gates are regaining popularity, since it is difficult to increase the speed of operation of transistors without metal gates. Likewise, the 'oxide' in the name can be a misnomer, as different dielectric materials are used with the aim of obtaining strong channels with applied smaller voltages.

Fig.3.3. showing layers of MOSFET

A cross section through an n-MOSFET when the gate voltage VGS is below the threshold for making a conductive channel; there is little or no conduction between the terminals source and drain; and the switch is off. When the gate is more positive, it attracts electrons, inducing an n-type conductive channel in the substrate below the oxide, which allows electrons to flow between the n-doped terminals; and the switch is on.

Fig.3.4. characteristics of drain current and gate-source voltage Simulation result for formation of inversion channel (electron density) and attainment of threshold voltage (IV) in a nanowire MOSFET. Note that the threshold voltage for this device lies around 0.45 V. The Metal oxide field effect transistor is used for amplifying or switching electronic signals. Although the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B) terminals. The body (or substrate) of the MOSFET often is connected to the source terminal, making it a three-terminal device like other field-effect

transistors. When two terminals are connected to each other (short-circuited) only three terminals appear in electrical diagrams. The MOSFET is by far the most common transistor in both digital and analog circuits, though the bipolar junction transistor was at one time much more common.

In enhancement mode MOSFETs, a voltage drop across the oxide induces a conducting channel between the source and drain contacts via the field effect. The term "enhancement mode" refers to the increase of conductivity with increase in oxide field that adds carriers to the channel, also referred to as the inversion layer. The channel can contain electrons (called an n-MOSFET or n-MOS), or holes (called a p-MOSFET or p-MOS), opposite in type to the substrate, so n-MOS is made with a p-type substrate, and p-MOS with an n-type substrate. In the less common depletion mode MOSFET, described further later on, the channel consists of carriers in a surface impurity layer of opposite type to the substrate, and conductivity is decreased by application of a field that depletes carriers from this surface layer. The 'metal' in the name MOSFET is now often a misnomer because the previously metal gate material is now often a layer of poly-silicon (polycrystalline silicon). Aluminum had been the gate material until the mid-1970s, when poly-silicon became dominant, due to its capability to form self-aligned gates. Metallic gates are regaining popularity, since it is difficult to increase the speed of operation of transistors without metal gates.

An insulated-gate field-effect transistor or IGFET is a related term almost synonymous with MOSFET. The term may be more inclusive, since many "MOSFETs" use a gate that is not metal, and a gate insulator that is not oxide. Another synonym is MISFET for metalinsulatorsemiconductor FET. The basic principle of the field-effect transistor was first patented by Julius Edgar Lilienfeld in 1925.

3.2 MOSFET operation:

Fig. 3.5 Metaloxidesemiconductor structure on p-type silicon A traditional metaloxidesemiconductor (MOS) structure is obtained by growing a layer of silicon (SiO2) on top of a silicon substrate and depositing a layer of metal or polycrystalline (the latter is commonly used). As the silicon dioxide is a dielectric material, its structure is equivalent to a planar capacitor, with one of the electrodes replaced by a semiconductor. When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a p-type semiconductor (with bulk), a positive voltage, the density of acceptors, p the density of holes; p = NA in neutral from gate to body (see figure). Creates a depletion layer by

forcing the positively charged holes away from the gate-insulator or semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions. If is high enough, a high concentration of negative charge carriers forms in

an inversion layer located in a thin layer next to the interface between the semiconductor and the insulator. Unlike the MOSFET, where the inversion layer electrons are supplied rapidly from the source/drain electrodes, in the MOS capacitor they are produced much more slowly by thermal generation through carrier generation and recombination centers in the depletion region. Conventionally, the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage. This structure with p-type body is the basis of the n-type MOSFET, which requires the addition of an n-type source and drain regions.

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3.3 MOSFET structure and channel formation:

Fig.3.6.showing MOSFET channel formation Channel formation in n-MOS MOSFET: Top panels: An applied gate voltage bends bands, depleting holes from surface (left). The charge inducing the bending is balanced by a layer of negative acceptor-ion charge (right). Bottom panel: A larger applied voltage further depletes holes but conduction band lowers enough in energy to populate a conducting channel. A metaloxidesemiconductor field-effect transistor (MOSFET) is based on the modulation of charge concentration by a MOS capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer which in the case of a MOSFET is an oxide, such as silicon dioxide. If dielectrics other than an oxide such as silicon dioxide (often referred to as oxide) are employed the device may be referred to as a metalinsulatorsemiconductor FET (MISFET). Compared to the MOS capacitor, the MOSFET includes two additional terminals (source and drain), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they must both be of the same type, and of opposite type to the body region. The source and drain are highly doped as signified by a '+' sign after the type of doping.

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If the MOSFET is an n-channel or n-MOS FET, then the source and drain are 'n+' regions and the body is a 'p' region. If the MOSFET is a p-channel or p-MOS FET, then the source and drain are 'p+' regions and the body is an n region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel. The occupancy of the energy bands in a semiconductor is set by the position of the Fermi level relative to the semiconductor energy-band edges. As described above, and shown in the figure, with sufficient gate voltage, the valence band edge is driven far from the Fermi level, and holes from the body are driven away from the gate. At larger gate bias still, near the semiconductor surface the conduction band edge is brought close to the Fermi level, populating the surface with electrons in an inversion layer or n-channel at the interface between the p region and the oxide. This conducting channel extends between the source and the drain, and current is conducted through it when a voltage is applied between source and drain. Increasing the voltage on the gate leads to a higher electron density in the inversion layer and therefore increases the current flow between the source and drain. For gate voltages below the threshold value, the channel is lightly populated, and only a very small sub-threshold leakage current can flow between the source and the drain. When a negative gate-source voltage (positive source-gate) is applied, it creates a pchannel at the surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and voltages. When a voltage less negative than the threshold value (a negative voltage for p-channel) is applied between gate and source, the channel disappears and only a very small sub-threshold current can flow between the source and the drain. The device may comprise Silicon On Insulator (SOI) device in which a buried oxide (BOX) is formed below a thin semiconductor layer. If the channel region between the gate dielectric and a BOX region is very thin, the very thin channel region is referred to as an ultrathin channel (UTC) region with the source and drain regions formed on either side thereof in and/or above the thin semiconductor layer. Alternatively, the device may

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comprise a semiconductor on insulator (SEMOI) device in which semiconductors other than silicon are employed. Many alternative semiconductor materials may be employed. When the source and drain regions are formed above the channel in whole or in part, they are referred to as raised source/drain (RSD) regions. 3.4 Modes of operation:

Fig.3.7. showing modes of operation of MOSFET

Example application of an N-Channel MOSFET: When the switch is pushed the LED lights up Ohmic contact to body to ensure no body bias; top left: sub-threshold, top

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right: Ohmic mode, bottom left: Active mode at onset of pinch-off, bottom right: Active mode well into pinch-off channel length modulation evident. The operation of a MOSFET can be separated into three different modes, depending on the voltages at the terminals. In the following discussion, a simplified algebraic model is used that is accurate only for old technology. Modern MOSFET characteristics require computer models that have rather more complex behavior. For an enhancement-mode, n-channel MOSFET, the three operational modes are: Cutoff, sub-threshold, or weak-inversion mode When VGS < Vth: Where gate-to-source is bias and is the threshold voltage of the device.

According to the basic threshold model, the transistor is turned off, and there is no conduction between drain and source. A more accurate model considers the effect of thermal energy on the Boltzmann distribution of electron energies which allow some of the more energetic electrons at the source to enter the channel and flow to the drain. This results in a sub-threshold current that is an exponential function of gatesource voltage. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch, there is a weak-inversion current, sometimes called subthreshold leakage. In weak inversion the current varies exponentially with as given approximately by:

Where

= current at

, the thermal voltage

and the

slope factor n is given by , With = capacitance of the depletion layer and = capacitance

of the oxide layer. In a long-channel device, there is no drain voltage dependence of the current once , but as channel length is reduced drain-induced barrier

lowering introduces drain voltage dependence that depends in a complex way upon the

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device geometry (for example, the channel doping, the junction doping and so on). Frequently, threshold voltage Vth for this mode is defined as the gate voltage at which a selected value of current ID0 occurs, for example, ID0 = 1 A, which may not be the same Vth-value used in the equations for the following modes. Some micro power analog circuits are designed to take advantage of sub-threshold conduction. By working in the weakinversion region, the MOSFETs in these circuits deliver the highest possible transconductance-to-current ratio, namely: , almost that of a bipolar transistor The subthreshold IV curve depends exponentially upon threshold voltage, introducing a strong dependence on any manufacturing variation that affects threshold voltage; for example: variations in oxide thickness, junction depth, or body doping that change the degree of drain-induced barrier lowering. The resulting sensitivity to fabrication variations complicates optimization for leakage and performance. The transistor is turned on, and a channel has been created which allows current to flow between the drain and the source. The MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. The current from drain to source is modeled as:

Where the gate length and

is the charge-carrier effective mobility,

is the gate width,

is

is the gate oxide capacitance per unit area. The transition from the

exponential sub-threshold region to the triode region is not as sharp as the equations suggest.

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Saturation or active mode: When VGS > Vth and VDS > ( VGS Vth ) The switch is turned on, and a channel has been created, which allows current to flow between the drain and source. Since the drain voltage is higher than the gate voltage, the electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. The onset of this region is also known as pinch-off to indicate the lack of channel region near the drain. The drain current is now weakly dependent upon drain voltage and controlled primarily by the gatesource voltage, and modeled approximately as:

The additional factor involving , the channel-length modulation parameter, models current dependence on drain voltage due to the early effect, or channel length modulation. According to this equation, a key design parameter, the MOSFET transconductance is: Where the combination Vov = VGS Vth is called the overdrive voltage and where VDSsat = VGS Vth accounts for a small discontinuity in parameter is the MOSFET output resistance rout given by: which would otherwise

appear at the transition between the triode and saturation regions. Another key design

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rout is the inverse of gDS

where

. ID is the expression in

saturation region. If is taken as zero, an infinite output resistance of the device results that leads to unrealistic circuit predictions, particularly in analog circuits. As the channel length becomes very short, these equations become quite inaccurate. New physical effects arise. For example, carrier transport in the active mode may become limited by velocity saturation. When velocity saturation dominates, the saturation drain current is more nearly linear than quadratic in VGS. At even shorter lengths, carriers transport with near zero scattering, known as quasi-ballistic transport. In addition, the output current is affected by drain-induced barrier lowering of the threshold voltage.

3.5 Other MOSFET types: 3.5.1 Dual-gate MOSFET: The dual-gate MOSFET has a tetrode configuration, where both gates control the current in the device. It is commonly used for small-signal devices in radio frequency applications where biasing the drain-side gate at constant potential reduces the gain loss caused by Miller effect, replacing two separate transistors in cascade configuration. Other common uses in RF circuits include gain control and mixing (frequency conversion).

Fig. 3.8 showing dual gate MOSFET

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The FinFET, see figure to right, is a double-gate silicon-on-insulator device, one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering. The "fin" refers to the narrow channel between source and drain. A thin insulating oxide layer on either side of the fin separates it from the gate. SOI FinFETs with a thick oxide on top of the fin are called double-gate and those with a thin oxide on top as well as on the sides are called triple-gate FinFETs.

Depletion-mode MOSFETs:

Fig. 3.9 showing depletion mode MOSFETs

There are depletion-mode MOSFET devices, which are less commonly used than the standard enhancement-mode devices already described. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to source. To control the channel, a negative voltage is applied to the gate (for an n-channel device),

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depleting the channel, which reduces the current flow through the device. In essence, the depletion-mode device is equivalent to a normally closed (on) switch, while the enhancement-mode device is equivalent to a normally open (off) switch. Due to their low noise figure in the RF region, and better gain, these devices are often preferred to bipolar in RF front-ends such as in TV sets. Depletion-mode MOSFET families include BF 960 by Siemens and BF 980 by Philips (dated 1980s), whose derivatives are still used in AGC and RF mixer front-ends.

NMOS logic:

Fig.3.10 showing NMOS logic MOSFET N-channel MOSFETs are smaller than p-channel MOSFETs and producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler. These were the driving principles in the design of NMOS logic which uses n-channel MOSFETs exclusively. However, unlike CMOS logic, NMOS logic consumes power even when no switching is taking place. With advances in technology, CMOS logic displaced NMOS logic in the mid-1980s to become the preferred process for digital chips.

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Power MOSFET:

Fig.3.11 showing Cross section of a Power MOSFET, with square cells.

A typical transistor is constituted of several thousand cells. Power have a different structure than the one presented above. As with most power devices, the structure is vertical and not planar. Using a vertical structure, it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the N-epitaxial layer (see cross section), while the current rating is a function of the channel width (the wider the channel, the higher the current). In a planar structure, the current and breakdown voltage ratings are both a function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the "silicon estate". With the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness (actually the N-epitaxial layer thickness) is proportional to the breakdown voltage. Power MOSFETs with lateral structure are mainly used in high-end audio amplifiers and high-power PA systems. Their advantage is a better behavior in the saturated region (corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Vertical MOSFETs are designed for switching applications

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DMOS:

Fig, 3.12 D MOS DMOS stands for double-diffused metaloxidesemiconductor. Most power MOSFETs are made using this technology. RHBD MOSFETs: Semiconductor sub-micro meter and Nano-meter electronic circuits are the primary concern for operating within the normal tolerance in harsh radiation environments like outer space. One of the design approaches for making a radiation-hardened-by-design (RHBD) device is Enclosed-Layout-Transistor (ELT). Normally, the gate of the MOSFET surrounds the drain, which is placed in the center of the ELT. The source of the MOSFET surrounds the gate. Another RHBD MOSFET is called H-Gate. Both of these transistors have very low leakage current with respect to radiation. However, they are large in size and take more space on silicon than a standard MOSFET. Newer technologies are emerging for smaller devices for cost saving, low power and increased operating speed. The standard MOSFET is also becoming extremely sensitive to radiation for the newer technologies. A lot more research works should be completed before space electronics can safely use RHBD MOSFET circuits of nanotechnology.

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When radiation strikes near the silicon oxide region (STI) of the MOSFET, the channel inversion occurs at the corners of the standard MOSFET due to accumulation of radiation induced trapped charges. If the charges are large enough, the accumulated charges affect STI surface edges along the channel near the channel interface (gate) of the standard MOSFET. Thus the device channel inversion occurs along the channel edges and the device creates off-state leakage path, causing device to turn on. So the reliability of circuits degrades severely. The ELT offers many advantages. These advantages include improvement of reliability by reducing unwanted surface inversion at the gate edges that occurs in the standard MOSFET. Since the gate edges are enclosed in ELT, there is no gate oxide edge (STI at gate interface), and thus the transistor off-state leakage is reduced very much. Low-power microelectronic circuits including computers, communication devices and monitoring systems in space shuttle and satellites are very different than what we use on earth. They are radiation (high-speed atomic particles like proton and neutron, solar flare magnetic energy dissipation in earth's space, energetic cosmic rays like X-ray, gamma ray etc.) tolerant circuits. These special electronics are designed by applying very different techniques using RHBD MOSFETs to ensure the safe space journey and also space-walk of astronauts.

4 Peripheral Interface Controllers (MICRO CONTROLLER) (PIC): PIC is a family of modified Harvard architecture microcontrollers made by Microchip Technology, derived from the PIC1650 originally developed by General Instrument's Microelectronics Division. The name PIC initially referred to "Peripheral Interface Controller" .PICs are popular with both industrial developers and hobbyists alike due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, and serial programming (and reprogramming with flash memory) capability.

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Fig.4.1 showing PIC microcontroller

4.1 Core architecture: The PIC architecture is characterized by its multiple attributes: Separate code and data spaces (Harvard architecture) for devices other than PIC32, which has Von Neumann architecture. A small number of fixed length instructions Most instructions are single cycle execution (2 clock cycles, or 4 clock cycles in 8bit models), with one delay cycle on branches and skips One accumulator (W0), the use of which (as source operand) is implied (i.e. is not encoded in the op-code) All RAM locations function as registers as both source and/or destination of math and other functions. A hardware stack for storing return addresses A fairly small amount of addressable data space (typically 256 bytes), extended through banking Data space mapped CPU, port, and peripheral registers The program counter is also mapped into the data space and writable (this is used to implement indirect jumps).

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There is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers.

4.2 Data space (RAM): PICs have a set of registers that function as general purpose RAM. Special purpose control registers for on-chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC devices have some banking mechanism to extend addressing to additional memory. Later series of devices feature move instructions which can cover the whole addressable space, independent of the selected bank. In earlier devices, any register move had to be achieved via the accumulator.

To implement indirect addressing, a "file select register" (FSR) and "indirect register" (INDF) are used. A register number is written to the FSR, after which reads from or writes to INDF will actually be to or from the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer (SP).External data memory is not directly addressable except in some high pin count PIC18 devices.

4.3 Code space: The code space is generally implemented as ROM, EPROM or flash ROM. In general, external code memory is not directly addressable due to the lack of an external memory interface. The exceptions are PIC17 and select high pin count PIC18 devices.

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4.4 Word size: All PICs handle (and address) data in 8-bit chunks. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline (PIC12) and mid-range (PIC16) families have program memory addressable in the same word size as the instruction width, i.e. 12 or 14 bits respectively. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differ from the instruction width of 16 bits. In order to be clear, the program memory capacity is usually stated in number of (single word) instructions, rather than in bytes.

4.5 Stacks: PICs have a hardware call stack, which is used to save return addresses. The hardware stack is not software accessible on earlier devices, but this changed with the 18 series devices. Hardware support for a general purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture friendlier to high level language compilers.

4.6 Instruction set: A PIC's instructions vary from about 35 instructions for the low-end PICs to over 80 instructions for the high-end PICs. The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a register, as well as for conditional execution, and program branching. Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W (the accumulator), writing the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the "high end" cores.

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PIC cores have skip instructions which are used for conditional execution and branching. The skip instructions are 'skip if bit set' and 'skip if bit not set'. Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip (with the opposite condition) followed by an unconditional branch. Skips are also of utility for conditional execution of any immediate single following instruction.

The 18 series implemented shadow registers which save several important registers during an interrupt, providing hardware support for automatically saving processor state when servicing interrupts.

In general, PIC instructions fall into 5 classes: Operation on working register (WREG) with 8-bit immediate ("literal") operand. E.g. movlw (move literal to WREG), andlw (AND literal with WREG). One instruction peculiar to the PIC is retlw, load immediate into WREG and return, which is used with computed branches to produce lookup tables. Operation with WREG and indexed register. The result can be written to either the Working register (e.g. addwf reg, w). Or the selected register (e.g. addwf reg, w). Bit operations. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible. Control transfers. Other than the skip instructions previously mentioned, there are only two: goto and call. A few miscellaneous zero-operand instructions, such as return from subroutine, and sleep to enter low-power mode.

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4.7 Performance: The architectural decisions are directed at the maximization of speed-to-cost ratio. The PIC architecture was among the first scalar CPU designs,[citation needed] and is still among the simplest and cheapest. The Harvard architecturein which instructions and data come from separate sourcessimplify timing and microcircuit design greatly, and this benefits clock speed, price, and power consumption. The PIC instruction set is suited to implementation of fast lookup tables in the program space. Such lookups take one instruction and two instruction cycles. Many functions can be modeled in this way. Optimization is facilitated by the relatively large program space of the PIC (e.g. 4096 14-bit words on the 16F690) and by the design of the instruction set, which allows for embedded constants. For example, a branch instruction's target may be indexed by W, and execute a "RETLW" which does as it is named - return with literal in W. Interrupt latency is constant at three instruction cycles. External interrupts have to be synchronized with the four clock instruction cycle; otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized. The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. An example of this is a video sync pulse generator. This is no longer true in the newest PIC models, because they have a synchronous interrupt latency of three or four cycles. 4.8 Advantages: The PIC architectures have these advantages: Small instruction set to learn RISC architecture Built in oscillator with selectable speeds Easy entry level, in circuit programming plus in circuit debugging PIC Kit units available for less than $50 Inexpensive microcontrollers Wide range of interfaces including IC, SPI, USB, USART, A/D, programmable comparators, PWM, LIN, CAN, PSP, and Ethernet

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4.9 Limitations: The PIC architectures have these limitations: One accumulator Register-bank switching is required to access the entire RAM of many devices Operations and registers are not orthogonal; some instructions can address RAM and/or immediate constants, while others can only use the accumulator

The following stack limitations have been addressed in the PIC18 series, but still apply to earlier cores: The hardware call stack is not addressable, so preemptive task switching cannot be implemented Software-implemented stacks are not efficient, so it is difficult to generate reentrant code and support local variables

With paged program memory, there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups). For example, on PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2048 instruction words. For computed GOTOs, where you add to PCL, the page size is 256 instruction words. In both cases, the upper address bits are provided by the PCLATH register. This register must be changed every time control transfers between pages. PCLATH must also be preserved by any interrupt handler. 4.10 Compiler development: While several commercial compilers are available, in 2008, Microchip released their own C compilers, C18 and C30, for the line of 18F 24F and 30/33F processors. The easy to learn RISC instruction set of the PIC assembly language code can make the overall flow difficult to comprehend. Judicious use of simple macros can increase the readability of PIC assembly language. For example, the original Parallax PIC assembler ("SPASM") has macros which hide W and make the PIC look like a two-address machine. It has macro instructions like "mov b, a" (move the data from address a to address b) and "add b,
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a" (add data from address a to data in address b). It also hides the skip instructions by providing three operand branch macro instructions such as "cjne a, b, dest" (compare a with b and jump to dest if they are not equal). 4.11 Family core architectural differences: PIC microchips have Harvard architecture, and instruction words are unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations. Later revisions added op-code bits, allowing additional address bits. 4.12 Baseline core devices (12 bit): These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages. Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. Pointers are implemented using a register pair: after writing an address to the FSR (file select register), the INDF (indirect f) register becomes an alias for the addressed register. If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 1631; registers 015 are global and not affected by the bank select bits. Because of the very limited register space (5 bits), 4 rarely-read registers were not assigned addresses, but written by special instructions (OPTION and TRIS).The ROM address space is 512 words (12 bits each), which may be extended to 2048 words by banking. CALL and GOTO instructions specify the low 9 bits of the new code location; additional high-order bits are taken from the status register. Note that a CALL instruction only includes 8 bits of address, and may only specify addresses in the first half of each 512-word page. Lookup tables are implemented using a computed GOTO (assignment to PCL register) into a table of RETLW instructions.

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The instruction set is as follows. Register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (07) are selected by "b". The "d" bit Selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic.

5 BRIDGE RECTIFIERS:

Fig.5.1 three bridge rectifiers. The size is generally related to the current handling capability.

A diode bridge is an arrangement of four (or more) diodes in a bridge circuit configuration that provides the same polarity of output for either polarity of input. When used in its most common application, for conversion of an alternating current (AC) input into direct current a (DC) output, it is known as a bridge rectifier. A bridge rectifier provides full-wave rectification from a two-wire AC input, resulting in lower cost and weight as compared to a rectifier with a 3-wire input from a transformer with a centertapped secondary winding.

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6 DRIVER CIRCUIT:

Fig. 6.1showing driver circuit for triggering the MOSFETs In electronics, a driver is an electrical circuit or other electronic component used to control another circuit or other component, such as a high-power transistor. They are usually used to regulate current flowing through a circuit or are used to control the other factors such as other components, some devices in the circuit. The term is often used, for example, for a specialized integrated circuit that controls high-power switches in switchedmode power converters. An amplifier can also be considered a driver for loudspeakers, or a constant voltage circuit that keeps an attached component operating within a broad range of input voltages. Typically the driver stage(s) of a circuit requires different characteristics to other circuit stages. For example in a transistor power amplifier, typically the driver circuit requires current gain, often the ability to discharge the following transistor bases rapidly, and low output impedance to avoid or minimize distortion. 7 FILTERS: Electronic filters are electronic circuits which perform signal processing functions, specifically to remove unwanted frequency components from the signal, to enhance wanted ones, or both. Electronic filters can be:

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passive or active analog or digital High-pass, low-pass, band pass, band-reject (band reject; notch), or all-pass. discrete-time (sampled) or continuous-time linear or non-linear infinite impulse response (IIR type) or finite impulse response (FIR type)

Fig. 7.1 showing various types of filters in various sizes

8 TRANSFORMERS:

Fig.8.1 showing transformer

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A transformer is a device that transfers electrical energy from one circuit to another through inductively coupled conductorsthe transformer's coils. A varying current in the first or primary winding creates a varying magnetic flux in the transformer's core and thus a varying magnetic field through the secondary winding. This varying magnetic field induces a varying electromotive force (EMF), or "voltage", in the secondary winding. This effect is called inductive coupling. If a load is connected to the secondary, current will flow in the secondary winding, and electrical energy will be transferred from the primary circuit through the transformer to the load. In an ideal transformer, the induced voltage in the secondary winding (Vs) is in proportion to the primary voltage (Vp) and is given by the ratio of the number of turns in the secondary (Ns) to the number of turns in the primary (Np) as follows:

In this kit we are using the step down transformers one of which is 230v/50v and another is 50v/7v

9 THREE PHASE A.C. MOTOR:

Fig.9.1 three phase a.c. motor

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An induction or asynchronous motor is a type of AC motor where power is supplied to the rotor by means of electromagnetic induction, rather than a commutator or slip rings as in other types of motor. These motors are widely used in industrial drives, particularly polyphase induction motors, because they are rugged and have no brushes. Single-phase versions are used in small appliances. Their speed is determined by the frequency of the supply current, so they are most widely used in constant-speed applications, although variable speed versions, using variable frequency drives are becoming more common. The most common type is the squirrel cage motor, and this term is sometimes used for induction motors generally. 9.1 Squirrel cage rotor:

Fig.9.2 showing squirrel cage rotor The idea of a rotating magnetic field was developed by Franois Arago in 1824, and first implemented by Walter Baily. Based on this, practical induction motors were independently invented by Nikola Tesla in 1883 and Galileo Ferraris in

1885. According to his 1915 autobiography, Tesla conceived the rotating magnetic field in 1882 and used it to invent the first induction motor in 1883; Ferraris developed the idea in 1885. In 1888, Ferraris published his research to the Royal Academy of Sciences in Turin, where he detailed the foundations of motor operation; Tesla, in the same year, was granted U.S. Patent 381,968 for his motor. The induction motor with a cage was invented by Mikhail Dolivo-Dobrovolsky a year later.

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9.2 Operation:

Fig.9.3 a 3-phase power supply provides a rotating magnetic field in an induction motor.

In both induction and synchronous motors, the stator is powered with alternating current (polyphase current in large machines) and designed to create a rotating magnetic field which rotates in time with the AC oscillations. In a synchronous motor, the rotor turns at the same rate as the stator field. By contrast, in an induction motor the rotor rotates at a slower speed than the stator field. Therefore the magnetic field through the rotor is changing (rotating). The rotor has windings in the form of closed loops of wire. The rotating magnetic flux induces currents in the windings of the rotor as in a transformer. These currents in turn create magnetic fields in the rotor, that interact with (push against) the stator field. Due to Lenz's law, the direction of the magnetic field created will be such as to oppose the change in current through the windings. The cause of induced current in the rotor is the rotating stator magnetic field, so to oppose this rotor will start to rotate in the direction of the rotating stator magnetic field to make the relative speed between rotor and rotating stator magnetic field zero. For these currents to be induced, the speed of the physical rotor must be lower than that of the stator's rotating magnetic field ( ), or the magnetic field would not be moving

relative to the rotor conductors and no currents would be induced. As the speed of the rotor drops below synchronous speed, the rotation rate of the magnetic field in the rotor

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increases, inducing more current in the windings and creating more torque. The ratio between the rotation rate of the magnetic field as seen by the rotor (slip speed) and the rotation rate of the stator's rotating field is called "slip". Under load, the speed drops and the slip increases enough to create sufficient torque to turn the load. For this reason, induction motors are sometimes referred to as asynchronous motors. An induction motor can be used as induction, or it can be unrolled to form the linear induction motor which can directly generate linear motion. Synchronous speed: The synchronous speed of an AC motor is the rotation rate of the rotating magnetic field created by the stator. It is always an integer fraction of the supply frequency. The synchronous speed ns in revolutions per minute (RPM) is given by:

Where f is the frequency of the AC supply current in Hz and p is the number of magnetic pole pairs per phase. When using total number of poles, use 120 as constant instead of 60. For example, a small 3-phase motor typically has six magnetic poles organized as three opposing pairs 120 apart, each powered by one phase of the supply current. So there is one pair of poles per phase, which means p = 1, and for a line frequency of 50 Hz the synchronous speed is 3000 RPM.

Slip:

Fig.9.4Typical torque curve as a function of slip (slip is represented by g here, equivalent to in the formula at left).
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Slip s is the rotation rate of the magnetic field, relative to the rotor, divided by the absolute rotation rate of the stator magnetic field

Where

is the rotor rotation speed in rpm? It is zero at synchronous speed and

1 (100%) when the rotor is stationary. The slip determines the motor's torque. Since the short-circuited rotor windings have small resistance, a small slip induces a large current in the rotor and produces large torque. At full rated load, typical values of slip are 4-6% for small motors and 1.5-2% for large motors, so induction motors have good speed regulation and are considered constant-speed motors. Torque curve:

The torque exerted by the motor as a function of slip is given by a torque curve. Over a motor's normal load range, the torque line is close to a straight line, so the torque is proportional to slip. As the load increases above the rated load, increases in slip provide less additional torque, so the torque line begins to curve over. Finally at a slip of around 20% of the motor reaches its maximum torque, called the "breakdown torque". If the load torque reaches this value, the motor will stall. At values of slip above this, the torque decreases. In 3-phase motors the torque drops but still remains high at a slip of 100% (stationary rotor), so these motors are self-starting. The starting torque of an induction motor is less than other types of motor, but still around 300% of rated torque. In 2-pole single-phase motors, the torque goes to zero at 100% slip (zero speed), so these require alterations to the stator such as shaded polesto provide starting torque.

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Speed control:

Fig.9.5showing speed characteristics with respect to slip Typical torque curves for different line frequencies. By varying the line frequency with an inverter, induction motors can be kept on the stable part of the torque curve above the peak over a wide range of rotation speeds. However, the inverters can be expensive, and fixed line frequencies and other start up schemes are often employed instead. The theoretical unloaded speed (with slip approaching zero) of the induction motor is controlled by the number of pole pairs and the frequency of the supply voltage. When driven from a fixed line frequency, loading the motor reduces the rotation speed. When used in this way, induction motors are usually run so that in operation the shaft rotation speed is kept above the peak torque point; then the motor will tend to run at reasonably constant speed. Below this point, the speed tends to be unstable and the motor may stall or run at reduced shaft speed, depending on the nature of the mechanical load. Before the development of semiconductor power electronics, it was difficult to vary the frequency, and induction motors were mainly used in fixed speed applications. However, many older DC motors have now been replaced with induction motors and accompanying inverters in industrial applications.

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Starting:

Fig.9.6showing types of torques for different motors Torque curves for 4 types of asynchronous induction motors:

A)Single-phasemotor B)Poly-phasesquirrel-cagemotor C)Polyphasesquirrelcagedeepbarmotor D) Polyphase double squirrel cage motor A single phase induction motor is not self-starting; thus, it is necessary to provide a starting circuit and associated start windings to give the initial rotation in a single phase induction motor. The normal running windings within such a motor can cause the rotor to turn in either direction, so the starting circuit determines the operating direction. A polyphase induction motor is self-starting and produces torque even at standstill. The four methods of starting an induction motor are direct on-line, reactor, autotransformer and star-delta. Unlike a wound-rotor motor, the rotor circuit is inaccessible and it is not feasible to introduce extra resistance for starting or speed control. For small single-phase shaded-pole motor of a few watts, starting is done by a shaded pole, with a turn of copper wire around part of the pole. The current induced in this turn lags behind the supply current, creating a delayed magnetic field around the shaded part of the pole face. This imparts sufficient rotational character to start the motor. These motors are typically used in applications such as desk fans and record players, as the starting torque is very low and low efficiency is not objectionable.

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Larger single phase motors have a second stator winding fed with out-of-phase current; such currents may be created by feeding the winding through a capacitor or having it have different values of inductance and resistance from the main winding. In some designs, the second winding is disconnected once the motor is up to speed, usually either by a centrifugal switch acting on weights on the motor shaft or a thermistor which heats up and increases its resistance, reducing the current through the second winding to an insignificant level. Other designs keep the second winding on when running, improving torque. Polyphase motors have rotor bars shaped to give different speed/torque characteristics. The current distribution within the rotor bars varies depending on the frequency of the inducted current. At standstill, the rotor current is the same frequency as the stator current, and tends to travel at the outermost parts of the squirrel-cage rotor bars. As the rotor accelerates, the slip frequency declines, and current tends to travel deeper within the squirrel cage bars. Polyphase motors can generate torque from standstill, so no extra mechanism is required to initiate rotation. The different bar shapes can give usefully different speed/torque characteristics as well as some control over the inrush current at startup. In a wound rotor motor, slip rings are provided and external resistance can be inserted in the rotor circuit, allowing the speed/torque characteristic to be changed for purposes of acceleration control and speed control.

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10 TRACTION:

Fig. showing traction used in electric train ..a physical process in which a tangential force is transmitted across an interface between two bodies through dry friction or an intervening fluid film resulting in motion, stoppage or the transmission of power. The traction produced by a vehicle if expressed as a force is synonymous with tractive effort, or tractive force, and closely related to the term drawbar pull. Coefficient of traction The coefficient of traction is defined as the usable force for traction divided by the weight on the running gear (wheels, tracks etc.) i.e.: Usable Traction = coefficient of Traction x Weight As the coefficient of traction refers to two surfaces which are not slipping relative to one another it is the same as Coefficient of static friction, also known as limiting friction.

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10.1 Factors affecting tractive coefficient:

Fig. traction used in elevators Traction between two surfaces depends on several factors including: Material composition of each surface. Macroscopic and microscopic shape (texture; macro texture and micro texture) Normal force pressing contact surfaces together. Contaminants at the material boundary including lubricants and adhesives. Relative motion of tractive surfaces - e.g. a wheel on gritted ice when in motion may displace the grit and melt the ice - causing loss of traction. Current traction control systems do not work on untreated ice.

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