Full Paper

Int. J. on Recent Trends in Engineering and Technology, Vol. 7, No. 2, July 2012
2012 ACEEE
DOI: 01.IJRTET.7.2.548
Reconfigurabe Current Mode Programmable
Multifunctional Filter
Ahmed M. Nahhas
Department of Electrical Engineering,
Faculty of Engineering and Islamic Architecture,
Umm Al Qura University, Makkah, Saudi Arabia
Email: amnahhas@uqu.edu.sa
AbstractA reconf igurable current mode second-order
programmable multifunctional functional filter is realized
using digitally controlled low voltage CMOS current
conveyors. The programmable multifunctional functional
filter provides low pass, non-inverting band pass and high
pass responses. The realized current mode programmable
filter can provide independent digital control to its pole-
0
and pole-Q through n-bit control words with high resolution
capability, as well as reconf igurability. The realized
multifunctional functional filter is suitable as programmable
filter module for current mode field programmable analog
array. The programmable multifunctional functional filter is
designed and verified using PSPICE and the results thus
obtained justify the theory.
Index TermsCurrent conveyors, current mode amplifiers,
filters
I. INTRODUCTION
Recently, the introduction of digital control to the current
conveyor (CCII) has boosted its functional capability and
versatility in addition to its higher signal bandwidth, greater
linearity and large signal bandwidth. This digital control has
eased the on chip control of continuous time systems with
high resolution capability and reconfigurability [1-9].
This paper basically deals with the realization of current
mode second-order programmable multifunctional functional
filter using digitally controlled low voltage CMOS CCII [1],
[4-9]. The realized programmable multifunctional functional
filter (PMFF) provides digitally programmable filter parameters
through n-bit control words. The PMFF can be used as a
programmable module of a field programmable analog array
(FPAA) [10], [11]. To verify the theory, the realized PMFF is
designed and verified using PSPICE and the results thus
obtained justify the theory.
II. THE CMOS DPCCII
The digitally programmable CCII (DPCCII) symbol is
shown in Fig. 1(a) and its CMOS implementation with 4-bit
control word is shown in Fig. 1(b) [4-7]. The current
summing network (CSN) is included at port-X. The transfer
matrix can be expressed as
(
(
(

(
(
(

=
(
(
(

Z
X
Y
m
Z
X
Y
V
I
V
N I
V
I
0 0
0 0
0 0 0

(1)
Thus the port voltages and currents for DPCCII can be
expressed as

X
m
Z
Y X
Y
I N I
V V
I

=
=
=
,
, 0
(2)
In equation (2) is the voltage transfer gain from terminal-Y
to terminal-X and is the current transfer gain from X to Z.
Both the voltage gain () and the current gain () are ideally
unity. N is an n-bit digital control word, the plus sign(+) is for
I
Z+
and minus sign(-) is for I
Z-
-. The power integer m = 1 for
current summing network (CSN) at port-Z and m = -1 for cur-
rent summing network (CSN) at port-X of the DPCCII [1], [4-
8]. The additional number of Z+ or Z- outputs may be added
as per requirement just by connecting in parallel a set of
PMOS and NMOS for each output as shown in Fig. 1(b).
Figure 1(a). Symbol for 4-bit DPCCII
88
Full Paper
2012 ACEEE
DOI: 01.IJRTET.7.2.
Int. J. on Recent Trends in Engineering and Technology, Vol. 7, No. 2, July 2012
548
Figure 1(b). The CMOS implementation of a 4-bit DPCCII with CSN at port X
III. THE PMFF CIRCUIT
The current mode PMFF circuit using low voltage
digitally controlled CMOS DPCCII with m=1, is shown in
Fig. 2. The circuit uses three DPCCII, each one with two
outputs along with grounded R and C elements.
Figure 2. The PMFF circuit
The routine analysis yields its current transfers functions
respectively for low pass filter (LPF), band pass filter (BPF)
and high pass filter (HPF) as follows.

2 1 3 2
2
1 1
2
2 1 3 2
2
1
C C R R
N
C R
s s
C C R R
N
I
I
IN
LP
+ +
=
3(a)
2 1 3 2
2
1 1
2
1 2
1
C C R R
N
C R
s s
C R
N
s
I
I
IN
BP
+ +
=
3(b)
2 1 3 2
2
1 1
2
2
1
C C R R
N
C R
s s
s
I
I
IN
HP
+ +
=
3(c)
By just directly adding I
HP
and I
LP
the Band Reject (BR) output
(I
BR
) response can easily be obtained and the resulting transfer
function can be expressed as follows.

2 1 3 2
2
1 1
2
2 1 3 2
2
2
1
C C R R
N
C R
s s
C C R R
N
s
I
I
IN
BR
+ +
+
=
3(d)
From equation (3) the filter parameters can be expressed as
follows.
The pole frequency

3 2 2 1
0
R R C C
N
=
4(a)
The pole-Q

3 2 2
1
1
R R C
C
N R Q =
4(b)
If resistance R
1
is replaced by an equivalent digitally
programmable resistor (DPR) as shown in Fig. 3, [5],
with the relationship given in equation (5) and with R =R
2
=R
3
, and C
1
= C
2
= C, the pole-
0
and pole-Q

0
1
N
R
R =
(5)
from equation (4) reduces to

RC
N
=
0

0
N
N
Q =
(6)
89
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Int. J. on Recent Trends in Engineering and Technology, Vol. 7, No. 2, July 2012
2012 ACEEE
DOI: 01.IJRTET.7.2.548
Figure 3. The digitally programmable resistor (DPR) using CMOS
DPCCII with m=1
The filter gains are H
LP
= H
HP
= 1, and the H
BP
= Q 6(b)
From equation (6) it is evident that the pole frequency
0
is
directly proportional to digital control word N. The pole-Q
can be independently controlled through the digital control
word N
0
. The minimum N
0
= 1, and thus maximum Q = N.
However, by selecting the DPCCII with m = -1, for the DPR of
Figure 3, with R
1
= RN
0
, results the pole-Q as
Q = NN
0
(7)
Thus from equation (7), it is obvious that the pole-Q can be
independently and directly controlled through the digital
control word N
0
. Now with N
0
= 1 the minimum Q = N. The
maximum Q = NN
0
and the choice is suited for designing
high-Q filter.
Taking the non-idealities of CCIIs into account as given
in equation (2), for the PMFF of Figure 2, with identical
and for all the CCIIs, the ideal relationship of pole-
0
, filter
gains and pole-Q given in equation(6) and (7) respectively,
yields the non-ideal pole-
0
, filter gains and pole-Q as follows.


RC
N
=
0

0
N
N
Q =
(8)
The filter gains are
H
LP
= H
HP
= 1, and the H
BP
= Q

0
NN Q = (9)
It is evident from equation (8) and (9) that the non-idealities
slightly affect the pole-
0
and pole-Q.
IV. DESIGN AND VERIFICATION
The realized digitally controlled current mode PMFF of
Figure 2 was designed and verified by performing PSPICE
simulation with supply voltage 0.75V using CMOS TSMC
0.25m technology parameters. The aspect ratios used are
given in the Table 1. The PMFF was verified using the DPCCII
with the CSN at port-Z (i.e. m=1).
TABLE I. THE ASPECT RATIOS OF THE MOSFETS OF THE DPCCII
The PMFF was initially designed for a pole frequency of f
0
=46.8kHz and pole-Q = 1 with N =N
0
= 1, R = 13.6k and C =
0.25nF. Then the pole frequency was controlled through digital
control word N. The observed frequency responses of the
filter for different control words are given in Figure 4 which
show the close conformity with the design.
Figure 4(a). Frequency response of LP, HP and BP second
order current mode filter at control word N = 2
CONCLUSION
The current mode programmable second-order multifunc-
tional filter is realized using digitally controlled low voltage
CMOS current conveyors. The programmable multifunctional
filter provides low pass, high pass, band pass and band re-
ject responses. The realized current mode multifunctional fil-
ter parameters are digitally programmable through n-bit con-
trol words with high resolution capability and
reconfigurability. The programmable multifunctional filter is
suitable as a programmable filter module for the current mode
field programmable analog array. The realized programmable
multifunctional filter was designed with minimal passive com-
ponents spread and verified using PSPICE. All the results
thus obtained justify the theory.
90
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2012 ACEEE
DOI: 01.IJRTET.7.2.
Int. J. on Recent Trends in Engineering and Technology, Vol. 7, No. 2, July 2012
548
Figure 4(b). Frequency response of LP second order current mode
filter at different control word N
Figure 4(c). Frequency response of HP second order current mode
filter at different control word N
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Figure 4(d). Frequency response of the BP second order current
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Figure 4(e). Frequency response of BR second order current mode
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