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Array Multiplier
a a a a a a
b b b b b b p1p1p1p1p1p1 p2p2p2p2p2p2 longest delay

pnpnpnpnpnpn

delay ~ # digits in word + # partial products # partial products can be reduced by using radix > 2 multiplier

0 1 0 0 0 0 0 0 1 1

0 0 1 0 0

1 0 0 1 0 1

1 0 1 0 0 0 1 0 1

0 1 0 1 0 0 0

1 0 1 1 0 0

1 0 1 1 0

1 0 1 1 1 0 0

multiplicand multiplier 1 0 10 1 0 0 11 0 0 0 1 1

1 0 1 0 0 0 0 1 0 1 0

1 1 1 0 0 3 1 0 1 0 0 0 1 0 1 0

0 1 0 1 0 1 0 1 1 1 0 3 1 0 1 1 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0

## must pre-calculate 3 x multiplicand

Could take 3 bits at time (radix 8), but need 3x, 5x, 6x, 7x multiplicand.
Array Multiplier October 20, 2000 page 1 of 10

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Trick: recode multiplier changing all 3s to 4 - 1. This can be done with a shifter and 2s complement hardware and does not need an extra adder. Example 101110 (+1)(+1)(-1) 1 1 1 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 0 1 0

## sign extension of negative partial product

103

1 1 -1

Booth algorithm replaces any string of 1s (including 3s) with single digits isolated by strings of 0s. 01111110 10000000 10000010 00000010 Booth recoding (original) b i b i 1 b i (recoded) 0 0 1 1 Example assume zero multiplier recoded multiplier 010011 110101 (+1) (+1) (-1) Now that 3s are gone, combine each pair bits into single recorded digit to reduce number of partial products.
Array Multiplier October 20, 2000 page 2 of 10

0 1 0 1

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## Modified Booth Recoding

bi+1 0 0 0 0 1 1 1 1

bi 0 0 1 1 0 0 1 1

bi-1 0 1 0 1 0 1 0 1

## Modified Booth Recoding 0 +1 +1 +2 -2 -1 -1 0

implemented by shift, comp, zero The modified Booth recoded multiplier digits are -2, -1, 0, 1, 2 (never 3). When the multiplicand is multiplied by one of these digits to get the partial product, the partial product is generated by a combination of shifting, complementing or zero-ing without any extra adders. Suppose we try to use an even higher number base to further reduce the number of partial products. Consider base 8 which combines three binary bits into one digit which produces only 1/3 of the original partial products. However, we must find ways to recode the base 8 digits so that there are no non-powers of 2. 0 is OK 1 is OK 2 is OK 3=? 4 is OK 5=? 6 = 8 - 2 is OK 7 = 8 - 1 is OK Since there is no way to recode the 3 and 5 digits, extra adders must be provided to precompute multplying by these digits. This negates most of the advantage of going to the higher number base. Most multiplier designs use modified Booth recoding and multiply by two bits at a time which is what we will assume from now on.
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Implementation

Multiplicand (A)

## Adder Multiplier Encoder Partial Product Gen Carry

multiplier (B)

Multiplier Encoder

Carry

Product

Array Multiplier

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FA

FA

FA

CSA

FA

FA

FA

CSA

## No carry delay! (within a CSA stage) CSA array

CS

CS

CS

CS

Partial Product Generator recoded digit 0 +1 +2 -1 -2 operation 0 => partial product multiplicand => partial product shifted multiplicand => partial product complemented multiplicand => partial product shifted & complemented multiplicand => partial product

Array Multiplier

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Ai

Ai-1

ZERO

COMP

SHIFT

MUX P.P.i

MUX P.P.i-1

Carry Generation

## ZERO COMP SHIFT

.
Cin two ways to get a zero p.p. p.p. bits Cin 000 0 0 111 1 1

Array Multiplier

## October 20, 2000

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Multiplier Encoder

bi+1 0 0 0 0 1 1 1 1

bi 0 0 1 1 0 0 1 1

bi-1 0 1 0 1 0 1 0 1

Recoded Digit 0 +1 +1 +2 -2 -1 -1 0

COMP x 0 0 0 1 1 1 x

SHIFT x 0 0 1 1 0 0 x

ZERO 1 0 0 0 0 0 0 1

## COMP = b i + 1 SHIFT = b i b i 1 + b i b i 1 ZERO = b i + 1 b i b i 1 + b i + 1 b i b i 1 Sign Extension Problem original example

sign extension

1 1 0 0 1 0 1

1 1 0 0 1 0 1

1 1 0 0 1 0 1

1 1 0 0 0 0 0

1 1 0 0 1 0 1

1 1 0 0 1 0 0

1 0 1 0 0 0 1 0 1

0 1 0 1 0 0 0

1 0 1 1 0 0

1 0 1 1 0 0

1 1 1 0 0 0

0 1 0 0 0

0 1 0 1 0

Array Multiplier

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## recoded example 10 11 10 (+1)(+1)(-1) 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 0 1 0

can rewrite the first non-zero sign extension as 1111 10001 The sign extension part of the partial products for a Booth encoded multiplier can be written as S0 S0 S0 S0 S0 S1 S1 S1 Sn-1Sn-1 Sn SSSS S 00 trick 1-S=S 0(-S) S 1-S 0 1 1 0 S 1 0
Array Multiplier

SS

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## +1 111 0 0 111 1 0 0(-S0) 0(-S1)

0(-Sn-1) +1 0 0 0 1 S0 0 1 S1 1 Sn-1 Partial Product Generation for Sign Extension An-1 ZERO COMP 1 SHIFT Si MUX Sign bit of multiplicand PPn+1 PPn PPn-1 Note: the remaining bits are always zero even when P.P. < 0. No adder inputs are needed for these zeroes.
Array Multiplier October 20, 2000 page 9 of 10

## 6 X 6 Booth Multiplier Example

A5 3 B.E. 1
PPG

A4
PPG

A3
PPG

A2
PPG

A1
PPG

A0
PPG

B0 B1

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B.E.

3
PPG PPG PPG PPG PPG PPG

1
HA

1
FA HA HA HA HA

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B.E.

3
PPG PPG PPG PPG PPG PPG

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HA 0

FA

FA

FA

FA

FA 0

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