designfeature By Raminderpal Singh, IBM

GUIDELINES CAN HELP BLOCK AUTHORS AND CHIP INTEGRATORS LOWER SIGNAL-INTEGRITYRELATED RISKS DURING INTEGRATION.

Avoid signal-integrity blowouts in SOC-design IP-block integration

M
any small and large design teams use Alliance) signal-integrity-specifications-developthird-party IP (intellectual property) to ac- ment work addresses these problems (Reference 1). celerate SOC (system-on-chip) design by importing functional blocks, such as data converters, SIGNAL-INTEGRITY PROBLEMS PLLs, Ethernet PHY layers, DSPs, and processors. Signal-integrity concerns are among the top obImporting IP today is consistently expensive for stacles to successfully designing an SOC. Handling many reasons, but poor information transferals be- these concerns can require a great deal of time and tween IP authors and IP integrators is the most fre- money, worrying many design managers and chip quent culprit. architects. EDA-tool vendors are investing heavily in IP authors often provide incomplete or ambigu- trying to provide useful design options. ous documentation about the IP, incorrect or inThe capacitive coupling between the victim net consistent design views, incomplete design data, or and one or more aggressor nets is mainly responsiincorrect IP verification. Even if an author provides ble for interconnect crosstalk, although inductive complete and correct information, the IP integra- coupling is also beginning to cause problems in leadtor still may have difficulty taping out a functional ing-edge custom designs (Reference 2). Interconnect chip after following the IP providers guidelines. In crosstalk is worsening with each process generation addition to these issues, the integrator must also deal because of nonideal scaling of wires. As wires grow with signal integrity, such as parasitic noise in the narrower and taller with each generation to keep redesign, which requires a sophisticated understand- sistance manageable, the ratio of the coupling caing of the issues and communication with the IP author. SYSTEM ON CHIP The inability to observe signalADAPTIVE integrity problems early in the CONTROL-PLANE PROCESSING EQUALIZER design process compounds the SOC-design problem. Engineers frequently fail to detect the probFIFO lem until after the creation of the SAR GDSII data. And, at worst, they PHY NETWORK MEDIASERDES PROCESSOR ACCESSfail to find the problem until after CONTROL the chips are in production. These FRAMER issues will likely worsen as devices become smaller; thus, signal integrity is now one of the most CLOCK MANAGEMENT CLOCK fundamental challenges to RECOVERY achieving a successful complex A network-IC block diagram demonstrates signal-integrity issues in SOC design. The VSIA Figure 1 modern SOC design (courtesy Xilinx). (Virtual Socket Interface

SWITCHPHY SERDES

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pacitance of a wire to its total capacitance also increases. Although moving from aluminum to copper can halt this deterioration for a generation, successive generations will have to tackle the same issue. Therefore, it is becoming increasingly important for designers to account for coupling during timing analysis. Increasing design size, increasing power consumption, and decreasing supply voltage and, thus, increasing current are resulting in an increase in the amount of power-grid IR drop and ground bounce on chips. This trend is critical, because the IR-drop and ground-bounce noise margins are decreasing along with the supply voltage. Designers are already discovering chip failures due to power-grid issues, involving both IR drop and electromigration. Because these issues relate to the number of components on a chip and the way you assemble them and are primarily a global phenomenon, powergrid analysis is becoming a necessary addition to many design flows. Substrate coupling occurs in many types of circuitsfrom small RF designs, to large embedded memories. A key aspect of this problem is the flow of ac currents in the substrate. Fast-switching digital devices are typically the source of these currents. Problems most often occur in embedded data converters or memories in large ASIC or ASSP (application-specific standard-product) ICs. Interconnect-inductance modeling is an important analysis tool for critical high-speed nets in both analog- and digital-IP designs, as well as for chip-level interconnects. Enhancements to the RLC interconnect-extraction engines or transmission-line models allow designers to model interconnect inductance. Extraction techniques provide higher capacity but do not supply the high accuracy that transmission-line modeling offers. The VSIA handles signal-integrity problems by offering detailed checklists and guidelines for IP authors and integrators written by a range of industry experts (Reference 1). An international team of EDA, design, CAD, research, and foundry engineers has worked for more than a year to put together an infrastructure of the issues you face when integrating complex analog and digital IP, formalizing and presenting these issues in a practical manner that creates a smooth IP-integration process. The docblock designers. Designing the block involves an advanced understanding of the parasitic noise issues associated with the interconnect, devices, and substrate. The problem gains complexity, however, when an IP designer has to ensure that the block functions within specifications once you integrate it into the SOC. Often, the IP author must guarantee its functioning with little knowledge of the SOCtypically, when he or she is selling the IP to thirdparty integrators. In these cases, the VSIA signal-integrity specifications can be of critical value to the IP designer. Consider, for example, the issue of substrate couplinga difficult problem for designers. A section of the VSIA document provides detailed information for IP designers, so that the designer can provide the SOC integrator with accurate constraints and guidelines using industry-standard formats and supported documentation (Reference 1). Network-SOC integrators face a multitude of signal-integrity issues, one of which is ground bounce due to the large supply and ground network that the design needs. The ground bounce that the network processor generates can affect the performance of the SERDES blocks unless you perform careful integration. The VSIA signal-integrity document also contains guidelines that can help you handle this task. Signal integrity is a serious issue facing both IP designers and SOC integrators, and the VSIAs international and crossfunctional team of IC designers, researchers, CAD engineers, and process engineers has taken a practical approach to resolving it. More development is under way and will offer even more useful specifications for new chip-level interconnects. References 1.Signal Integrity Specifications Document Version 1.0,Virtual Socket Interface Alliance, www.vsi.org. 2. Singh, Raminderpal, Signal Integrity Effects in Custom IC and ASIC Designs, IEEE Press and Wiley & Sons, November 2001. 3. www.xilinx.com/products/virtex2 pro/systemdiagrams.htm#. Acknowled gment Thanks to Prashant Saxena of Intel Corp, Franois Clement of Simplex Solutions,
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SIGNAL INTEGRITY IS A SERIOUS ISSUE FACING BOTH IP DESIGNERS AND SOC INTEGRATORS, AND THE VSIAs TEAM HAS TAKEN A PRACTICAL APPROACH TO RESOLVING IT.
ument structure allows readers to focus on each issue that the previous section discusses without reading the entire document. This structure is useful when, for example, an RF designer is focusing on substrate-coupling issues but may be unconcerned about (or may not understand) interconnect-crosstalk issues. As an example, consider the generic signal-integrity problems that occur when you build large Ethernet-processing ICs by integrating a digital-standardcell and Ethernet-custom-digital cores. (The emerging Ethernet Gigabit, XAUI, and SONET standards are making this type of IC common today.) Figure 1 depicts a typical SOC structure for networking. The SOC comprises numerous aspects, ranging from a high-speed (10Gbyte/sec) SERDES (serializer/deserializer) to lower frequency (more than 1GHz) network processors, with even lower frequencies in the surrounding control blocks. The SOC integrator must carefully integrate the SERDES and processor cores so that signal-integrity issues do not cause failed tape-outs. This integration is especially important in the networking market, in which time to market is critical. A bad spin in the foundry can lengthen the production schedule by three months and be disastrous to the product-line success. And, because signal integrity is a key reason for failure, network-SOC designers need to place strong emphasis on avoiding the signal-integrity problems that occur during integration. CHALLENGES Figure 1 shows many types of IP in a network SOC. Its architecture is typical of communications-system designs and raises many challenges for RF-IP designersin this case, especially for SERDES-

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Steffen Rochel of Simplex Solutions, Larry Cooke of VSIA, and Carl Dickey of IBM. Authors bio graphy Raminderpal Singh, PhD, is a senior engineer in the IBM Communications Research and Development Center (Essex Junction, VT). He is the team leader for physical verification and signal integrity for design-kit development (specifically leading the transmission-line- and substrate-coupling-modeling efforts). He also leads the IBM strategy for development of CAD for mixed-signal SOC designs for the RF-CMOS and SiGe foundry business. He is co-chairman of the AMS working group in the VSIA SOC standards body, chairman of the VSIA signal-integrity development team, and a senior member of IEEE.

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