Cairo University Faculty of Engineering Computer Engineering Department

CMP 444

Copmuter Interfacing

Spring 2004

Reduced Instruction Set Computer (RISC)

Presented to:
Dr. Ahmed Darwish

Prepared by:
Amr M. Medhat Mostafa Fathy Sameh M. Serag For Contact: SpeechLab@YahooGroups.com

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TABLE OF CONTENTS
1. INTRODUCTION....................................................................................................3 1.1. Brief history of the CPU ...................................................................................3 1.2. CISC ...................................................................................................................3 1.3. RISC ...................................................................................................................3 2. RISC FEATURES....................................................................................................4 2.1. Small Instruction Set ........................................................................................4 2.2. Register-to-Register Operations (Load/Store Architecture) ........................4 2.3 Single Instruction per Cycle..............................................................................4 2.4. Large Number of Registers:.............................................................................4 2.5. Hardwired Design (No Microcode) .................................................................4 2.6. Fixed instruction format (size).........................................................................4 2.7. Harvard Architecture (Code and Data Buses)...............................................4 3. OVERLAPPED REGISTER WINDOWS.............................................................5 4. RISC AND THE MARKET....................................................................................6 5. RISC VS. CISC AND THE FUTURE....................................................................7 5.1. Post-RISC Architecture....................................................................................8 5.2. EPIC ...................................................................................................................8 6. REVIEW QUESTIONS...........................................................................................9 7. REFERENCES.......................................................................................................10

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1. INTRODUCTION 1.1. Brief history of the CPU

In the 40s, CPUs were designed using vacuum tubes that consumed a lot of electricity. In the early 50s, Vacuum tubes were replaced by the transistors. After the evolving of the integrated circuits, the year 1971 witnessed the emerging of the first working CPU on a single chip that was called microprocessor [1]. This processor was the 4004 by Intel.

1.2. CISC
Before the emergence of the first microprocessor till the early 80s, the design of all the CPUs was following one Philosophy. This philosophy was to put as many instructions as possible to the instruction set of the microprocessors to cover every possible situation in which a programmer might need some instruction. This was specifically since the IBM 360 system, created in 1964, which was probably the first modern processor system that initiated the idea of computer architecture in computer science and adopted micro-coded control. Micro-coded control facilitated the use of complex instruction sets and provided flexibility, thus appeared so-called Complex Instruction Set Computer (CISC) [2]. The idea behind this philosophy is to minimize the number of instructions needed to perform a given task, thus, reduce the "semantic gap" between the machine language of the processor and the high-level languages in which people were programming. Having a single instruction that could describe quite a complex sequence of operations was reasonable for some reasons [2]: the compiler technology at that time was in its infancy, same as advanced programming language, people always used assembly language at that time at that era, hardware was extremely expensive, thus fewer memory occupy was strongly preferred

However, with more and more complex instructions sets, decoding and execution of such instructions were complicated and time-consuming; also, the expensive overhead brought by them slowed down the execution of those more frequently used simple instructions [2].

1.3. RISC
The question that rose up and was the scope of studies of many researches was "Do we need such a huge instruction set?" The answer is that most of these instructions were neither used by the assembly programmers or by high-level language compilers [1]. Studies showed that only 20% of a computer's instructions do 80% of the work [2]. This answer led to another philosophy of designing CPUs; this philosophy tends to reduce the number of instructions of the machine's instruction set to only the basic

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common used instructions. Thus these CPUs were called RISC (reduced instruction set computer) [1]. By the time, the declining cost of memory devices and improved compiler technology, were the most important factors that have transformed RISC into a success in the marketplace in addition to its design simplicity of course [2]. So what are the gains? RISC achieved a lot of gains as reducing the instruction set didn't only simplify the design and reduce the cost but also made more transistors available to enhance the power of the CPU. It also made hardwired control possible instead of micro-coded control used in CISC. Let us discuss all of these and more other RISC features in some detail.

2. RISC FEATURES 2.1. Small Instruction Set

RISC processors have only the basic instructions such as: ADD, SUB, MUL, DIV, LOAD, STORE, AND, OR, EXOR, SHR, SHL, CALL and JMP. For example, there are no such instructions as INC, DEC, NOT, NEG and so on [3].

2.2. Register-to-Register Operations (Load/Store Architecture)

Instructions can only load from memory into registers or store registers into memory locations. There is no direct way of doing arithmetic and logic operations between registers and contents of memory locations. All these instructions must be performed by first bringing both operands into the registers inside the CPU, performing the operation then returning the result back to the memory limiting addressing modes [3].

2.3 Single Instruction per Cycle

An important feature of RISC is that its instructions are executed with only one clock. This was the result of limiting the addressing modes and it made pipelining feasible [3].

2.4. Large Number of Registers:

There are 32 32-bits integer registers and 32 64-bits floating-point registers in most RISC processors no need for stack [3]. Only a few are assigned to dedicated function e.g.: r0 is automatically assigned the value zero.

2.5. Hardwired Design (No Microcode)

Due to the small number of instructions, they are all implemented hardwired and take no more than 10% of the transistors ( In CISC processors, the implementation of microinstructions inside the CPU take more than 60%of the transistors).

2.6. Fixed instruction format (size)

In CISC, instructions can be 1, 2 or even 6 bytes. In RISC, all instructions are 4 bytes [3]. Difficult instruction decoding.

2.7. Harvard Architecture (Code and Data Buses)

RISC processors have separate buses for code and data. There are four sets of Reduced Instruction Set Computer 4

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buses:1- a set of data buses for carrying data(operands) in and out of the CPU, 2- a set of address buses for accessing data operands, 3- a set of buses to carry the opcodes, and 4- a set of address buses to access the opcodes [3].

3. OVERLAPPED REGISTER WINDOWS

Procedure call and return occurs quite often in high-level programming languages. When translated into machine language, a procedure call produces a sequence of instructions that save register values, pass parameters needed for the procedure, and then calls a subroutine to execute the body of the procedure. After a procedure return, the program restores the old register values, passes results to the calling program, and returns from the subroutine. Saving and restoring registers and passing of parameters and results involve time-consuming operations. Some computers use the memory stack to store the parameters that are needed by the procedure, but this requires a memory access every time the stack is accessed. An alternative is to provide multipleregister banks inside the processor, and each procedure is allocated its own bank of registers. This eliminates the need for saving and restoring register values. A characteristic of some RISC processors is their use of overlapped register windows to provide the passing of parameters and avoid the need for saving and restoring register values. Each procedure call results in the allocation of a new window consisting of a set of registers from the register file (register file means all registers in the processor) for use by the new procedure. Each procedure call activates a new register window by incrementing a pointer, while the return statement decrements the pointer and causes the activation of the previous window. Windows for adjacent procedures have overlapping registers that are shared to provide the passing of parameters and results. An example of a system using overlapped register windows is shown in Figure [1] below. The system has a total of 74 registers. Registers R0 through R9 are global registers that hold parameters shared by all procedures. The other 64 registers are divided into four windows to accommodate procedures A,B,C, and D. Each register window consists of 10 local registers and two sets of six registers common to adjacent windows. Local registers are used for local variables. Common registers are used for exchange of parameters and results between adjacent procedures. The common overlapped registers permit parameters to be passed without the actual movement of data. Only one register window is activated at any given time with a pointer indicating the active window. Each procedure call activates a new register window by incrementing the pointer. The high registers of the calling procedure overlap the low registers of the called procedure, and therefore the parameters automatically transfer from calling to called procedure [1]. A R10 R27 B R26 R43 C R42 R59 D
Used for passing parameters bet. A and B R58 R73

Figure [1]

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4. RISC AND THE MARKET

The birth The first system that would today be known as RISC was the CDC 6600 supercomputer, designed in 1964 by Seymour Cray.It had a load/store architecture with only two addressing modes and it used pipelined functional units [4]. But the earliest attempt to make a chip-based RISC CPU was a project at IBM research center started in 1975. It was the IBM 801 minicomputer which was used as a fast controller in a very large telephone switching system. The growth Two projects which started some years later brought RISC concepts finally into the mainstream of computer architecture. The first one was the RISC project started in 1980 at the University of Berkeley. The project delivered the RISC-I processor in 1982. Consisting of only 44,420 transistors (compared with averages of about 100,000 in newer CISC designs of the era). RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design. They followed this up with the 40,760 transistor, 39 instruction RISC-II in 1983 [4]. The second project was MIPS at Stanford University in 1981. MIPS focussed almost entirely on the pipeline, making sure it could be run as "full" as possible. The Stanford research group had a strong background in compilers, which led them to develop a processor whose architecture would represent the lowering of the compiler to the hardware level, as opposed to the raising of hardware to the software level, which had been a long running design philosophy in the hardware industry [5]. In these early years, the RISC efforts were well known, but largely confined to the university labs that had created them. The spreading But starting in 1986, all of the RISC research projects started delivering products. In fact, almost all modern RISC processors are direct copies of the RISC-II design that was used at first by Sun to develop SPARC. SPARC designers decided in favor of aggressive use of register windows for performance. The basic design included 128 32-bit registers, which can be accessed in "windows" of 8[4, 5]. After that RISC has come to completely dominate the market for low-power "embedded" CPUs and microcontrollers as its design offers low power consumption and some designs also were modified to be memory-efficient. But this didn't prevent from taking a place in the market of PCs and large workstations too. [4] RISC designs have led to a number of successful platforms and architectures, some of the larger ones being: MIPS's MIPS line, found in most SGI computers and the Nintendo 64 IBM's POWER series, used in all of their minis and mainframes Motorola and IBM's PowerPC used in all Apple Macintosh computers Sun's SPARC and UltraSPARC, found in all of their later machines ARM -- Palm originally used the (CISC) Motorola 680x0 processors in their early PDAs, but now uses (RISC) ARM processors in their latest PDAs

But although a significant number of microprocessors are based on RISC technology today, RISC never achieved the market penetration that its early proponents hoped for. In part, this limited acceptance was because the performance improvement offered by RISC was offsetted by a very large installed base of x86-compatible CISC

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computers. With large investments in software for CISC computers, corporation decision-makers could not justify switching to RISC in many cases. Nevertheless, RISC takes lead in academic community, research funding and publications.

5. RISC VS. CISC AND THE FUTURE

We end up our discussion of RISC with a comparison summarizes the major differences between RISC and CISC [8]: POINT OF COMPARISON Number of instructions Complexity of instructions (how many clock cycles are needed?) Instruction length Instruction cycle CISC Large Simple instructions (require only one clock cycle) as well as complex ones (require more than one clock cycle) Variable Conventional Width: narrow Register file: few registers Stack pointer: available RISC Small Only simple instructions Fixed Pipelined Width: wide Register file: many registers) Stack pointer: not available Few (Simple) Only LOAD and STORE instructions can access memory (all instructions are register-toregister)

Registers

Addressing modes

Many No. of addressing modes (Complex) Memory-tomemory access (most of the instructions can operate directly on operands from memory)

Control Unit

Microprogrammed (uses control store for storing microinstructions)

Hardwired

Price Popularity

Move complexity from software to hardware More popular

Move complexity from hardware to software Less popular

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Now, the usual question to be introduced is which one is better?? Well, the usual answer is none of them. There is no absolute better or absolute worse, as there are lots of benchmarks for performance evaluation and comparison. We only present here a simple performance equation for the execution time of a program depending on the processor executing it [6]: time/program = [ (instructions/program) x (steps/instruction) x (time/step) ] A program on a RISC processor will have much more instructions than a program doing the same task on a CISC processor. But a RISC instruction takes much less time in execution than a CISC instruction. So there is a tradeoff.

5.1. Post-RISC Architecture

We presented the usual answer to the question of which is better, but if we come to the unusual answer, we will say no one of them is better too, as actually the question itself has lost its meaning. Really with the fleeting of time, the battle over RISC and CISC became blur, and now RISC and CISC architectures are becoming more and more alike. In fact, the two architectures almost seem to have adopted the strategies of the other. This has led some to argue that we are now in the "post-RISC" era [2]. An example is Intel microprocessors, though they use a CISC instruction set and are considered CISC chips, the internal architecture has gradually migrated to RISC. Beginning with the Pentium Pro, Intel used a RISC core, converting CISC instructions to RISC-like instructions. On the other hand, some RISC machines added more instructions to their architectures for new data types [2]. So, nowadays, the difference between RISC and CISC is no longer one of instruction sets, but of the whole chip architecture and system. The designations RISC and CISC are no longer meaningful in the original sense. What counts in a real world is always how fast a chip can execute the instructions it is given and how well it runs existing software. It seems that this is the end of the story, but actually it isn't as EPIC appeared on the horizon.

5.2. EPIC
The biggest threat for CISC and RISC might not be each other, but a new technology called EPIC. EPIC stands for Explicitly Parallel Instruction Computing. Like the word parallel already says EPIC can do many instruction executions in parallel to one another. EPIC is a created by Intel and is in a way a combination of both CISC and RISC. This will in theory allow the processing of Windows-based as well as UNIX-based applications by the same CPU [2, 7]. So, will the future be for EPIC? Really it's a hard question to answer as RISC didn't meet the expectations and it couldn't kick CISC out of the market. We only say God knows best! Let the days tell us the answer. Now, we cannot say that's all, but we must end our discussion as we cannot keep pace with the evolving technologies we hear and talk about, we can just say that in technology world no one holds the crown forever. Reduced Instruction Set Computer 8

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6. REVIEW QUESTIONS True or False:

1. RISC processors are based on the philosophy of minimizing the number of instructions needed to perform a given task. 2. CPU design history was affected by the compilers technology. 3. Reducing the semantic gap between the machine language and high level languages was one of the motivations towards RISC 4. RISC used the same bus for code and data. 5. RISC instructions were decoded into smaller number of microinstructions than CISC because the instruction set was smaller. 6. Not all instructions can access the memory in RISC. 7. Processors used currently in Apple machines are pure RISC processors. 8. RISC processors are used in PDAs and microcontrollers while CISC processors are used in minis and supercomputers.

Complete:
1. RISC processors used Harvard Architecture; this means that there are separate buses for ______ and ______. 2. There were four busses in RISC, two busses carried the _____ of the operands and the opcode, and the other two carried the ____ of the operands and the opcode. 3. The instruction decoding process was easier in RISC because all instructions ______. 4. Due to the small number of instructions in RISC, they are all implemented _____, unlike CISC which used ______. 5. The large number of registers in RISC eliminated the need for _____. 6. RISC instructions are all simple instructions execute in _____ which makes pipelining feasible. 7. All instructions in RISC were executed in one clock cycle, this made _____ feasible. 8. RISC dominated the market of ____ and ____ as its design offers low power consumption. 9. The new architecture that resulted in after migrating RISC and CISC architectures is called ____ 10. The gains achieved after reducing the instruction set are ____, ____ and ____ 11. According to the performance equation given by: time/program = [(instructions/program) x (steps/instruction) x (time/step)] RISC tries to improve its performance by decreasing ____ and____ but the cost is ____, while CISC tries to improve the performance by decreasing ____ but the cost is ____ and ____

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Multiple Choice Questions:

1. The price of RISC is: a) Moving complexity from hardware to software b) Moving complexity from software to hardware c) RISC is too complex in software and hard ware d) RISC is too simple in hardware and software 2. The following are the factors that led to the success of RISC except: a) its design simplicity b) the declining cost of memory c) the emergence of microprogrammed control (T) d) the improved compiler technology 3. EPIC stands for: a) a) Extended Programmable Integrated Circuits b) b) Explicitly Parallel Integrated Circuits c) a) Extended Programmable Instruction Computer d) b) Explicitly Parallel Instruction Computer

Essay Questions:
1. Explain the Load/Store Architecture. 2. Explain by an example how the Overlapped Register Windows characteristic enabled parameter passing between procedures in RISC. 3. No one can tell which is better CISC or RISC, give a simple performance equation for the execution time of a program depending on the processor executing it. Show how CISC and RISC improve their performance according to this equation. 4. "RISC is just a philosophy not a standard", discuss. 5. Compare between CISC and RISC with respect to: number of instructions, control unit, registers, and addressing modes. 6. Knowing CISC is more popular than RISC; can we say that CISC is better than RISC? If yes, give more evidences, if no, why?

7. REFERENCES
[1] Ahmed Hamdy, Ashraf Abdel Raouf and Yousif Kamal "RISC", A CMP302 lecture handout, spring 2002 [2] Gao Y., Tang S., Ding Z. "Comparison between CISC and RISC" http://userpages.umbc.edu/~zding1/cmsc611/report.doc [3] Mazidi M. and J., " The 80X86 IBM PC and Compatible Computers" Volume II, Second Edition, Prentice Hall. [4] Wikipedia, The free Encyclopedia http://en.wikipedia.org/wiki/Reduced_Instruction_Set_Computer

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[5] Chen C., Novick G. and Shimano K. "RISC Architecture" http://cse.stanford.edu/class/sophomore-college/projects- 0/risc/about/index.html [6] Hannibal, " RISC vs. CISC: the Post-RISC Era, a historical approach to the debate" http://www.arstechnica.com/cpu/4q99/risc-cisc/rvc-1.html [7] Gerritsen, A., "CISC vs. RISC" http://www.tomax7.com/aplus/cisc_vs_risc.htm [8] Mano M. and Kime C., "Logic And Computer Design Fundamentals"

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