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ECE 526

Current Catalog Course Description

ECE 526: Verilog HDL for Digital Integrated Circuit Design Prerequisite: ECE 320/L. Corequisite: ECE 526L. This course covers use of Verilog Hardware Description Language for the design and development of digital integrated circuits, including mask-programmed ASICs and FPGAs. Hierarchical top down vs. bottom up design, synthesizable vs. nonsynthesizable code, verification, hardware modeling, simulation system tasks, compiler directives and subroutines are all covered and illustrated with design examples. Lab exercises emphasize use of professional compilation and simulation tools for debugging and verification.
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Verilog and SystemVerilog for Digital Integrated Circuit Design

Slides Dr. Nagi El Naga and Dr. Ronald W. Mehler

ECE526 Digital Integrated Circuit Design with Verilog and SystemVerilog Alternative titles: Digital Design with Verilog and SystemVerilog Advanced Digital Design with Verilog and SystemVerilog IC Design with Verilog and SystemVerilog Verilog and SystemVerilog for Digital Integrated Circuit Design Prerequisite: ECE 320/L. Corequisite: ECE 526L. This course covers the use of Verilog and SystemVerilog Languages (IEEE Std. 1800) for the design and development of digital integrated circuits, including maskprogrammed integrated circuits (ASICs) and field programmable devices (FPGAs). Hierarchical top down vs. bottom up design, synthesizable vs. non-synthesizable code, design scalability and reuse, verification, hardware modeling, simulation system tasks, compiler directives and subroutines are all covered and illustrated with design examples. 3

Instructor
Dr. Ronald W. Mehler Jacaranda 3303 (818) 677 2495 Office Hours: T,R 2:00 3:00

Course Web Page

Prerequisite
ECE 320: Theory of Digital Systems Boolean algebra, combinational and sequential circuits, number systems, etc. Advised: At least two 400-level computer engineering courses such as 420, 422 and 425. Neither ECE526 nor any other 500-level course is a beginners course.
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http://www.csun.edu/~rmehler/mehler_files/526f12.html

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Books
Textbook: Samir Palnitkar, "Verilog HDL, A guide to digital design and Synthesis," Second Edition. SunSoft Press, Sun Microsystems, Inc., Mountain View, California, 2003. Warning: text covers only Verilog. We will be mixing in SystemVerilog too. Interesting Reading: Thomas L. Friedman The World Is Flat: A Brief History of the Twenty-first Century, Farrar, Straus and Giroux, 2005. Andy Kessler Running Money, Collins, 2004. Michael Lewis The New New Thing: A Silicon Valley Story, 1999

Lab Manual
ECE 526 Verilog HDL Laboratory Purchase photocopy at CSUN Bookstore Fall 2011 revision
May be modified on the fly during the semester.

Lab Access
To use the lab, you will need a user ID and password. If you are registered, you should have one of each. If you dont know what yours are, see the web site
http://www.csun.edu/it/helpdesk/outages/accou nts.html
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Login Problems
Would recommend that all students be asked to reset their password at the beginning of the semester so that their account info are current and updated. Also, please note that if the student does not know their password, we (Information Systems) will not be able to reset it. They would have to go over to the Campus Helpdesk WalkIn Center - located in Oviatt Library, room 32 (Garden Level). The Center is open from Mon-Thu 8 a.m. to 7 p.m., and on Fri. 8 a.m. to 5 p.m. Picture ID is required for password resets. Please note that if the student has never been able to login successfully to a Windows machine in the CECS labs that most likely he/she has never reset their CSUN password. The password can be reset through the Campus Portal, under the Technology Tab. 10

Linux Computer Access

Computers in this room are the only ones on campus that run the required software. This room is only open during lab hours. You can access these machines remotely from the common lab. You can also use your own computers to remotely log in from anywhere.
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Common Lab (JD 1622C) Hours

Mon: Tue: Wed: Thu: Fri: Sat: Sun: 8 a.m. 11 p.m. 8 a.m. 11 p.m. 8 a.m. 11 p.m. 8 a.m. 11 p.m. 8 a.m. 6 p.m. 8 a.m. 6 p.m. 8 a.m. 6 p.m.

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COURSE POLICY
1. Homework and laboratory exercises will be assigned. They will be collected on due dates. Keep a copy of all solutions because homework solutions might not be returned. No late homework will be accepted. Three exams will be given (two midterm exams and one final exam). Tentative dates of the midterm exams are Thursday, October 11 and Thursday, November 15. Exam solution should be in Blue Books. (These can be bought at the bookstore.) Absolutely no other solution papers will be accepted. The Blue Books will be collected at the beginning of the semester and returned back on the exam day. Exams are cumulative; study everything for every exam. Absolutely no make-ups on exams. For emergency, you will be allowed to miss only one midterm exam with no penalty. The final exam must be taken to pass the course.

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The weights of the exams and exercises will be as follows:

Exam #1 Exam #2 Final Exam Total 30% 30% 35% 95%

COURSE POLICY

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The remaining 5% will be given on homework as well as the general impression given by each student. Talking to neighbors or coming late to the class disturbs the class and give a bad impression. Please avoid doing that and participate in classroom discussions to guarantee a big portion of the 5%. Your final grade will directly reflect the total number of points you will get. The following are the percentages for each grade:
Grade A Grade AGrade B+ Grade B Grade BGrade C+ 90-100% 85-90% 82-85% 78-82% 75-78% 72-75% Grade C Grade CGrade D+ Grade D Grade DGrade F 68-75% 65-68% 60-65% 55-60% 50-55% Below 50%
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4. 5.

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Course Policy
ECE 526 and ECE 526L are separate courses. Courses are co-requisites. It is required to take both concurrently. ECE 526L grade will be solely the average of all lab reports. Lab reports will have no bearing on ECE 526 grade.
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Academic Dishonesty
Claiming credit for someone elses work is the ultimate sin in academia. Your instructor is as hard core as they come on this. Not only will cheating result in an F in the course, it may result in expulsion from the university. International students found guilty of academic dishonesty may be deported.
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Its NOT a Victimless Crime

Giving diplomas to engineers who dont know engineering quickly damages the reputation of the university. A cheater prevents those who come after from even getting interviews.

Swine Flu

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Class presentation materials will be made available on the course 18 web site. If you are sick, stay home and dont infect anyone else.

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The only stupid question is one you dont ask.

Homework
Review ECE 320 material, prepare for assessment test Read Palnitkar through Chapter 2 Read Lab Manual through Experiment 1 Make sure you have access to your UNIX account No deliverables this week
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Better to keep your mouth shut and be thought a fool than to open it and remove all doubt. -- Mark Twain 19

Whats an ASIC, Anyhow?

Application Specific Integrated Circuit
Processors are generally NOT considered ASIC though design methodology is essentially identical. Processors (including DSPs) are multi-purpose devices.

ASIC Classes
Custom Mask FPGA

Pretty much all digital integrated circuits are developed using ASIC methodology. Many times more ASICs are designed every year than GP Processors or other catalog parts. 21

Full Custom

Standard Cell

Gate Array

Structured

Unstructured
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Its a Hot Field

Brief | Detailed | View jobs on map Results 1-25 of 350 Next ASIC ENGINEER POSITION-OPPORTUNITY OF A LIFETIME!! The Select Group Raleigh, NC 27607 Aug 20 ASIC ENGINEERS - Multiple Positions! Our client, new to the Raleigh market and growing rapidly, has won numerous awards and is ready to make their mark here in the Triangle!!! They are working with gr ... More Senior ASIC Design Verification Engineer Cisco Systems San Jose, CA 95134 Aug 20 We are seeking a Senior ASIC Design Engineer with specialized knowledge in digital ASIC design and networking technologies to join in the design of the Next Generation ASICs for our Catalyst 4K produc ... More ASIC Design Engineer CyberCoders Los Angeles 90001 Aug 20 Location Los Angeles, CA; Long Beach, CA Salary $90,000 - $110,000 Education Bachelor of Science Category Engineering Experience Required At least 2 Years Short Description ASIC Engineer - VHDL or Ver ... More SR SoC/ASIC Designer SemiconductorTalent.com Portland, OR 97201

Job Posting (Aug. 19)

TECHNICAL SKILLS: Use software development tools for microcontrollers. Must have experience with verification test languages such as Vera, Specman, and their extensions. Must know VHDL or Verilog language and using synthesis tools. Must know how to do Clevel and ASM level programming/debug. Must have basic understanding of electrical interfacing of microcontroller into system level environment.
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More every day: Monster search done Aug. 20.

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Digital Design
Virtually all digital design is now done in ASICs. Virtually all ASICs are designed using an HDL and logic synthesis. Verilog is the HDL of choice among most engineers and companies, particularly in California. A few use VHDL.
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Karnaugh Map
0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1
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Minimize Functions Manually Translate to Gates

0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1
Best design may be smallest, fastest, lowest power, quickest to market. Any one design will not be best in all categories.

Sometimes it takes a few tries to find the best implementation. 27

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Redundancy For Reliability

A

Four-bit Counter

SEL

OUT

The smallest design might not be the most desirable.

29 30 Image Texas Instruments

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Encode States (half table shown)

A 0 0 0 0 0 0 0 0 B 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 Current State 0 1 0 1 0 1 0 1 Next State 1 1 1 0 1 0 1 0

Manual Minimization Limits

Anyone can make a K-map for 4 inputs. 5 inputs is a bit tedious, but still manageable. Beyond 6? Useful devices tend to have a lot of states and inputs. Sum of products may not be the best implementation. Consider something so basic as a stoplight controllerpretty simple compared to a Pentium-class processor.

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Stoplight Controller
States: Red, Yellow, Green for each direction. Left-turn arrows: maybe 4, maybe 8 Right-turn arrows: maybe 4 Pedestrian lights: several possible states Sensors: push buttons and magnetic detectors Emergency Services override Fail-safe mode Once a single controller is perfect, synchronize it with the rest of the city. 33
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Moores Law
2005: Cell processor has 234 million transistors 2006: Intel produces 153 megabit SRAM with > 1 billion transistors 2007: Peryn dual-core has 410 million, quad-core will have 820

Engineering Density in the USA

Who is going to design all those gates?

35 Image Intel, Inc

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EDA : Electronic Design Automation

The process of using computer-based software systems to design very large-scale integrated (VLSI) circuits. All modern integrated circuits are designed with EDA tools. This course uses Verilog HDL for hardware description and the NC Verilog simulator from Cadence for simulation.
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Course Outline
1. Introduction to EDA (Electronic Design Automation). 2. Introduction to Hardware Modeling 3. Verilog primitive operators and structural modeling 4. Design verification: folded into other topics 5. Synchronization and synchronous design 6. Top down and bottom up methodology 7. Library modeling 38