--------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 15:07:27 10/05/2012 -- Design Name: -- Module Name: D:/xilinx prog/RAM_6116/RAM6116_TB.

vhd -- Project Name: RAM_6116 -- Target Device: -- Tool versions: -- Description: --- VHDL Test Bench Created by ISE for module: ram6116 --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: --- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementatio n -- simulation model. -------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; ENTITY RAM6116_TB IS END RAM6116_TB; ARCHITECTURE behavior OF RAM6116_TB IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ram6116 PORT( address : IN std_logic_vector(7 downto 0); data : INOUT std_logic_vector(7 downto 0); WE : IN std_logic; CS : IN std_logic; OE : IN std_logic ); END COMPONENT; --Inputs signal address : std_logic_vector(7 downto 0) := (others => '0'); signal WE : std_logic := '0'; signal CS : std_logic := '0'; signal OE : std_logic := '0';

--BiDirs signal data : std_logic_vector(7 downto 0); -- No clocks detected in port list. Replace <clock> below with -- appropriate port name -BEGIN -- Instantiate the Unit Under Test (UUT) uut: ram6116 PORT MAP ( address => address, data => data, WE => WE, CS => CS, OE => OE ); --------- Clock process definitions <clock>_process :process begin <clock> <= '0'; wait for <clock>_period/2; <clock> <= '1'; wait for <clock>_period/2; end process; -- Stimulus process stim_proc: process begin CS<='0'; OE<='1'; WE<='1'; address<="00000001"; data<="00000010"; wait for 10 ns; address<="00000010"; data<="00000100"; wait for 10 ns; address<="00000100"; data<="00001000"; wait for 10 ns; address<="00001000"; data<="00010000"; wait for 10 ns; OE<='0'; WE<='0'; CS<='0'; address<="00000001"; wait for 10 ns; address<="00000010"; wait for 10 ns; address<="00000100"; wait for 10 ns; address<="00001000"; -- insert stimulus here constant <clock>_period : time := 10 ns;

wait; end process; END;