Circuit diagram for verification of Kirchoffs Current Law:

Tabulation (KCL):

RPS Voltage, I1 = I2 I1 I2 I3 S.No. V + I3 (mA) (mA) (mA) (volts) (mA)

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Expt. No: . . . . . . . .

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Verification of Kirchoffs Current Law and Kirchoffs Voltage Law

Aim:

To verify Kirchoffs current law and Kirchoffs voltage law experimentally and compare the results with the theoretical value.

Equipment Required:

S.No. 1.

Name of the component Resistor

Type Rating Quantity 1k, Each 1 3.3k, 5.6k. (02 30)mA (01 50)mA (02 30)V (02 30)V 1

2. 3. 4. 5. 6.

Ammeter Ammeter Regulated Power Supply Voltmeter Breadboard

DC DC DC DC -

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Kirchoffs Current Law: Statement: Kirchoffs Current Law states that the algebraic sum of all the current meeting at a junction point is equal to zero.

Procedure: Connect the circuit as shown in figure. Switch ON the regulated power supply and set the voltage to a particular value say 5V. Record the reading of the three ammeters namely I1, I2 and I3 with proper sign by taking current entering the node as negative in observation table. Add I1 and I3 and verify whether the added value is equal to I1.

 Increase the RPS voltage insteps of 5V up to a maximum of 25V. Repeat the steps 3 to 5 by incrementing the RPS voltage in terms of 5V. Circuit Diagram for verification of Kirchoffs Voltage Law:

Tabulation (KVL):

S.No. RPS Voltage,

V1

V2

V = V1 +

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V (volts)

(volts) (volts)

V2 (volts)

.0 Kirchoffs Voltage Law: Statement:

Kirchoffs Voltage Law states that in any network the algebraic sum of voltage across the circuit element of any closed path is equal to the algebraic sum of emfs in the circuit.

Procedure: Connect the circuit as shown in figure. Switch ON the regulated power supply and set the RPS to a particular value of voltage say 5V. Record the reading of two voltmeters namely V1 and V2 in the observation table. Add V1 and V2 and verify whether the added value is equal to V. Increase the RPS settings in steps of 5V up to a maximum of 25V. Repeat the steps 3 to 5 for each value of RPS voltage in terms of 5V.

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Result: Thus the Kirchoffs Current Law and Kirchoffs Voltage Law are verified experimentally and theoretically.

Circuit Diagram for Superposition theorem:

Observation Table 1: Source 1 Source 2 I1 I2 I3 S.No. voltage (V) voltage (V) (mA) (mA) (mA)

Verification of Superposition Theorem

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Aim: To verify the superposition theorem and do determine the current in branch of multi source circuit (3.3K).

Equipment Required:

S.No. 1.

Name of the component Resistor

Type Rating Quantity 1k, Each 1 3.3k, 5.6k. (02 30)mA (01 50)mA (01 100) mA (02

2. 3. 4.

Ammeter Ammeter Ammeter

DC DC DC

5.

Regulated Power

DC

6. 7.

Supply Voltmeter Breadboard

DC -

30)V (030)V -

2 1

Superposition theorem: Statement: Superposition theorem states that the response at any point in a linear circuit having more than one independent source can be obtained as the sum of the response caused by the separate independent source acting alone.

Procedure: Connect the circuit as shown in circuit diagram. Set the source RPS and source 2 RPS to particular values of 5V and 9V respectively.

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Record the three ammeters reading namely I1, I2 and I3 in the observation table. Set the source RPS to a particular value of 5V and replace source 2 by its internal resistance as shown in circuit diagram. Record the three ammeter readings namely I1a, I2a and I3a in the observation table. Circuit Diagram with source 2 replaced by its internal resistance:

Observation Table 2: Source 2 is replaced by its internal resistance:

S. No.

Source 1 voltage (volts)

I1a (mA)

I2a (mA)

I3a (mA)

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Set the source 2 RPS to a particular value say 9V and replace source 1 by its internal resistance. Record the three ammeter readings namely I1b, I2b and I3b in the observation table. By principle of Superposition theorem, I1 = I1a + I1b --- 1 I2 = I2a + I2b --- 2 I3 = I3a + I3b --- 3 Verify the observation table whether the equation 1, 2 and 3 are satisfied. If they are satisfied the principle of superposition theorem is satisfied. Reset the value of source 1 and source 2 to new values and repeat steps 3 to 9.

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Circuit Diagram with source 1 replaced by its internal resistance:

Observation Table 3: Source 1 is replaced by its internal resistance:

S. No.

Source 2 voltage (volts)

I1a (mA)

I2a (mA)

I3a (mA)

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Result: Thus the superposition theorem was verified experimentally and theoretically. Circuit for verification of Thevenins theorem:

Circuit for verification of Thevenins voltage:

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Verification of Thevenins theorem and Nortons theorem

Aim: To draw a circuit and find the current through the load resistance of the given circuit by using both Thevenins and Nortons theorem

experimentally and compare the results with the theoretical values.

Components Required:

S.No. 1. 2. 3. 4. 5.

Name of the component Resistor Ammeter Regulated Power Supply Voltmeter Breadboard

Type Rating Quantity 1k (050)mA DC (030)V DC (050)V DC 3 1 2 1 1

Thevenins theorem: Statement:

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Thevenins theorem states that in a linear bilateral network, the current between any two terminals A and B can be determined by replacing the given network consisting of a voltage source Vth and a series resistance by Req connected across the same two terminals A and B, where, Vth: Thevenins open circuit voltage measured across the terminals A and B. Req: Thevenins equivalent resistance viewed between the terminals A and B.

Procedure: Connect the circuit as given in the circuit diagram. Set the regulated power supply to a particular value of voltage say 5V, note the

ammeter reading, i.e. the load current I1 is measured. Remove the load resistor and maintain the circuit. Circuit to obtain Thevenins resistance:

Verification of Thevenins Theorem:

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Again set the RPS voltage to 5V and note the voltmeter reading across the two terminals A and B as in observation table which is the thevenin voltage (Vth). Remove the voltmeter and maintain the circuit. Measure the resistance across the terminals A and B which is the thevenins

resistance Req and note the value in the observation table. Calculate the load current I2 by using the formula, Vth
eq L

Verify whether the measured value of load current (IL) is equal to the calculated value of load current. If both are equal to the thevenin theorem. Repeat the steps 3 to 8 by incrementing the RPS setting in terms of 5V.

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Short circuit current:

Nortons equivalent circuit:

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Nortons theorem: Statement: It states that in any bilateral linear network, current through two terminals A and B can be determined by replacing the given network by any equivalent network consisting of current with a resistance connected in parallel in it, across the two terminals, A and B.
N( N) L N L

Where, IL = IN = RN = source. RL = Load current between A and B. Nortons equivalent current source. Nortons equivalent resistance Load resistance between A and B.

Procedure: Connect the circuit as shown in the diagram. Set the regulated power supply voltage to a particular value and voltage say 5V. Record the current flowing through the load resistance in the observation table. Remove the load resistance across the terminals A and B with a multimeter. Short circuit the terminals A and B with ammeter and maintain the circuit as shown. Record the short circuit current (Ith) in the observation table. Calculate the current in load resistance using the formula, N( N)
L

Verify that IL1 and IL2, i.e. IL1 = IL2 of both are equal, then the Nortons theorem is verified.

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Repeat the steps 3 to 8 by changing the values of the given RPS.

Circuit diagram to find Nortons equivalent resistance:

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Table 1 (Thevenins): RPS S. Measure Vth Req Calculate Voltag No d IL (volts (ohms d IL e . (mA) ) ) (mA) (volts)

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Table

(Nortons):

RPS Load Load S. Nortons Short Voltag Curren Current No Resistanc Circui e t , . e t (volts) (mA) IL

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Result: Thus the Thevenins theorem and Nortons theorem are verified experimentally and theoretically.

Circuit Diagram (Maximum power transfer theorem):

Circuit diagram for verification of Maximum power transfer theorem:

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Verification of Maximum Power Transfer theorem

Aim: To calculate the maximum power transfer in a given DC network and verify the maximum power transfer theorem.

Components Required:

S.No. 1. 2. 3. 4. 5.

Name of the component Resistor Ammeter Regulated Power Supply Voltmeter Breadboard

Type Rating Quantity 1k (010)mA DC (030)V DC (010)V DC 4 1 1 1 1

Maximum Power Transfer theorem: Statement: Consider a resistance load, connected to a DC network. It receives maximum power when the load resistance is equal to the internal resistance of the source network as seen from the load terminals. The internal resistance is the thevenins equivalent resistance.

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Procedure: Connect the circuit as shown in the figure. Set the source decade resistance to a required value. Set the load decade resistance to some initial value. Switch ON the power supply and note down the current and RL value and enter it in the observation table. Set the load decade resistance RL < RS for two readings and note down the current and enter it in observation table. Set the load decade resistance RL = RS and note down the current and enter it in observation table. Tabulation:

Load Load S. Resistance, RL Current, IL No. (ohms) (mA)

Calculated Power (W)

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Set the load decade resistance RL > RS for two readings and note down the current and enter it in observation table.

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Result: Thus the Maximum Power transfer theorem was verified and the maximum power for the given circuit is . . . . . . . . . . . W.

Circuit diagram with source at one side:

Circuit diagram with source at another side:

Verification of Reciprocity theorem

Aim: To verify the reciprocity theorem in a DC network.

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Components Required:

S.No. 1.

Name of the component Resistor

Type Rating Quantity 1k, Each 1 3.3k, 5.6k DC (01 10)mA DC (01 30)V 1 1

2. 3. 4. 5.

Ammeter Regulated Power Supply Decade Resistance Box Breadboard

Reciprocity theorem: Statement: In any branch of a network, the current due to a source of voltage elsewhere in the network

is equal to the current through the branch in which the source was originally obtained.

Procedure: Connect the circuit as per the circuit diagram Set the regulated power supply (RPS) to 5V and measure the corresponding value of current (I1). Now connect the circuit as per the circuit diagram (2). Again set the RPS voltage to 5V and measure the corresponding value to current I2. Repeat the steps 1 to 4 by incrementing for new values of the RPS. If I1 = I2, then the reciprocity theorem is verified.

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Table 1:

S. No.

RPS Voltage (volts)

I1 (mA)

Table 2:

S. No.

RPS Voltage (volts)

I2 (mA)

I1 = I2 (mA)

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Result: Thus the reciprocity theorem was verified experimentally.

Circuit Diagram: Diode in Forward Bias:

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Diode in Reverse Bias:

Characteristics of PN junction diode

Aim: To plot the VI characteristics of a PN junction diode under forward and reverse bias.

Apparatus Required:

S. No. 1. 2. 3.

4. 5.

Equipment Range Resistor 1 k Voltmeter (0 -100) V Ammeter (0 100) mA, (0 100) A PN junction IN4007 diode Regulated (0 30) V

Quantity 1 1 Each 1

1 1

Date: . . . . . . . .

Expt. No: . . . . . . . .

Page No: . . . . . . . .

6. 7.

Power Supply Breadboard Connecting Wires

1 As required.

Theory: A PN junction diode is a semiconductor device constructed with the following two semiconductor materials i. P Type semiconductor material. ii. N Type semiconductor material. The p type material is formed by doping a trivalent impurity to the pure semiconductor such as silicon or germanium. It forms holes as majority carriers and electrons as minority carriers. The n type material is formed by doping a pentavalent impurity into pure semiconductor

and it forms electrons as majority carriers and holes as minority carriers. The current flow in PN junction is due to both majority and minority carriers.

Table 1: PN in Forward Bias: S. No. Voltage across the diode, Vf, (volts) Anode Current, I f, (mA)

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Table 2: PN in Reverse Bias: S. No. Voltage across the diode, Vr, (volts) Anode Current, Ir, (A)

Principle of operation: There are two types of operation of a PN junction diode, i. Forward bias. ii. Reverse bias.

Forward Bias: The diode is said to be forward biased when the anode is connected to the positive terminal of the DC source, the holes in the P region of the diode are repelled by the positive current.

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Hence these holes have sufficient energy to cross the potential barrier at the PN junction. Similarly as the anode is connected to the negative terminal of the DC source, so the electrons in the N region are repelled by the applied voltage. Hence they too get the sufficient energy to cross the junction. So the potential barrier at the junction becomes zero. So the diode acts as a ordinary resistor with a small resistance because of internal voltage drop in it.

Reverse Bias: Similarly when the anode is connected to the negative terminal of the DC source, the diode is said to be reverse biased. In this case the current from the source is in such a way that, it attracts the holes towards the negative terminal and electrons towards the positive terminal

connected to the cathode of the diode. So this causes the potential barrier at the junction to increase a lot. During reverse bias the diode almost acts as an open circuit. During reverse bias small current flows through the diode. This current is called as reverse saturation current (Io). When voltage is increased, the electric field in the junction increases. This increases the reverse saturation current. At particular voltage, even for a small increase in voltage there is a large rate of increase in current. This is called as Avalanche Breakdown. Cut In Voltage: Even though voltage is applied to the diode during forward bias, initially there is no current flowing through the diode till a particular forward voltage is applied. The forward voltage at which the diode current starts to increase is

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called as cut in voltage. The cut in voltage for silicon is 0.7V and 0.3V for germanium.

Model Graph: VI characteristics of a PN junction diode:

Procedure: Forward Characteristics:

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The connections are given as per the circuit diagram. The input voltage is varied in steps by varying the RPS from minimum value. The corresponding voltage across the diode and the anode current values are noted and tabulated in table 1. The VI characteristics of PN junction diode is plotted for the value in table 1.

Reverse Characteristics: The connections are given as per the circuit diagram. The input voltage is varied in steps by varying the RPS from minimum value. The corresponding voltage across the diode and the anode current values are noted and tabulated in table 2.

 The VI characteristics of PN junction diode is plotted for the value in table 2. The characteristics of the PN junction diode are drawn between voltage and current with forward characteristics in the first quadrant and the reverse characteristics in the second quadrant.

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Result: Thus the VI characteristics of a PN junction diode were obtained and the graph was plotted.

Circuit Diagram 1: Zener in Forward Bias:

Circuit Diagram 2:

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Zener in Reverse Bias:

Characteristics of Zener diode

Aim: To plot the VI characteristics of a zener diode under forward and reverse bias.

Apparatus Required:

S. No. 1. 2. 3.

Equipment Resistor Voltmeter Ammeter

4. 5.

6. 7.

Range 1 k (0 -10) V (0 100) mA, (0 100) A Zener diode IZ5.6V Regulated (0 30) V Power Supply Breadboard Connecting Wires

Quantity 1 1 Each 1

1 1

1 As required.

Theory:

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Zener diode is a heavily doped PN junction diode which is operated in the breakdown region. Forward Bias: The p type semiconductor is connected to the positive terminal of DC power supply and n type semiconductor is connected to the negative terminal of the supply under forward bias condition. The zener diode acts as an ordinary PN junction diode. This will cause maximum current to flow in the diode. Reverse Bias: The n type semiconductor is connected to positive terminal of DC power supply and p type semiconductor is connected to the negative terminal of the power supply. The zener diode is connected in reverse bias and hence the current flow in the diode is very small when the reverse

bias voltage across a zener diode can be used as a voltage regulator. Table 1: Zener in Forward Bias: S. No. Voltage across Zener diode, Vf, (volts) Zener Current, I f, (mA)

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Table 1: Zener in Reverse Bias: S. No. Voltage across Zener diode, Vr, (volts) Zener Current, Ir, (A)

Procedure: Forward Bias: The connections are given as per the circuit diagram 1. The input voltage is applied across the zener diode using RPS and the zener current values are noted and tabulated. The VI characteristics of zener diode under forward bias condition are drawn using the values in the table 1. Reverse Bias: The connections are given as per the circuit diagram 2.

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The input voltage is applied across the zener diode using RPS and the zener current values are noted and tabulated. The VI characteristics for the zener diode under reverse bias condition are drawn using the values in the table 2.

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Result: Thus the VI characteristics of zener diode were obtained and the graph was plotted.

Circuit Diagram for Common Base Configuration:

Model Graph for CB configuration: Input Characteristics:

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Characteristics of Common Base configuration

Aim: To determine the characteristics of BJT under Common Base configuration.

Apparatus Required:

S. No.

Apparatus Required

Range

Quantity

1. 2. 3. 4. 5. 6. 7.

(0 30) V (0 1) V, (0 30) V Ammeter (0 -100) mA Resistor 1 k Transistor BC107 Breadboard Connecting wires RPS Voltmeter

2 Each 1 2 2 1 1 As Required

Theory: A Bipolar Junction Transistor (BJT) is a three terminal device in which the operation depends on the interaction of both majority and minority carriers. The three terminals are Base, Emitter and Collector. The arrow on the emitter specifies the direction of the conventional current flow when the EB junction is forward

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biased. Emitter is heavily doped and it can eject large number of charge carriers into the base. Base is lightly doped and very thin. It passes most of the injected charge carriers from the emitter into the collector. The collector is moderately doped.

Principle of Operation:

This is also called a grounded base configuration. Emitter is the input terminal, Collector is the output terminal and Base is the common terminal. Output Characteristics:

Tabulation for CB characteristics: Input Characteristics:

VCB = V VBE IE (V) (mA)

VCB = V VBE IE (V) (mA)

VCB = V VBE IE (V) (mA)

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Input Characteristics: (IE vs. VBE, keeping VCB constant) The collector base voltage VCB is kept constant at zero voltage and the emitter current is increased from in suitable steps by increasing VBE. This is repeated for higher fixed values of VCB. When VCB is equal to zero then the emitter base junction is forward biased and the

junction behaves as a forward biased diode, so that the emitter current IE increases rapidly with small increase in the base emitter voltage VBE. When VCB is increased keeping VBE constant, the width of the base region will decrease.

Output Characteristics: (IC VS VCB, keeping IE constant) The emitter current IE is kept constant at a suitable value by adjusting the emitter base voltage VEB. Then VCB is increased in equal steps and collector current IC is noted for each value of IE. This is repeated for different fixed values of IE.

Procedure: Input Characteristics:

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Keeping the voltage across the collector to emitter (VCE) as constant, tabulate the values of base current for various values of base emitter voltage (VBE). Repeat the same procedure for various constant values of VCE.

Output Characteristics: Keeping the base current as constant, tabulate the values of collector current (IC) for various values of collector emitter voltage (VCE). Repeat the same procedure for various constant values of base current (IB).

Output Characteristics:

IE = (mA) VBC IC (V) (mA)

IE = (mA) VBC IC (V) (mA)

IE = (mA) VBC IC (V) (mA)

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Result: Thus the characteristics of BJT under Common Base configuration were determined and plotted.

Circuit Diagram for Common Emitter configuration:

Model Graph for CE configuration: Input Characteristics:

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Characteristics of Common Emitter configuration

Aim: To determine the characteristics of BJT under Common Emitter configuration.

Apparatus Required:

S. No.

Apparatus Required

Range

Quantity

1. 2. 3. 4. 5. 6. 7.

(0 30) V (0 1) V (0 500) A Resistor 1 k Transistor BC107 Breadboard Connecting wires RPS Voltmeter Ammeter

2 2 2 2 1 1 As Required

Theory: This is also called as grounded emitter configuration. Here base is the input terminal, collector is the output terminal and emitter is the common terminal.

Operation: Input Characteristics:

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The collector to emitter voltage is kept constant at zero voltage and base current increased from zero in equal steps by increasing VBE. This procedure is repeated for higher values of VCE and curves of IB Vs VBE are drawn. When VCE = 0, the emitter base junction is forward biased and the junction behaves as a forward biased diode. When VCE is increased, the width of the depletion region at the reverse biased collector base junction will increase. Hence the effective width of the base will decrease.

Output Characteristics:

Tabulation for CE characteristics: Input Characteristics:

VCE = V VBE IB (V) (mA)

VCE = V VBE IB (V) (mA)

VCE = V VBE IB (V) (mA)

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Output Characteristics: The base current IB is kept constant at a suitable value by adjusting base emitter voltage VBE. The magnitude of the collector emitter voltage VCE is increased in suitable equal steps from zero and the collector current IC is noted for each setting of VCE. Now the curves of IC

versus VCE are plotted for different constant values of IB.

Saturation Region: Both junctions are forward biased and an increase in the base current does not cause a corresponding large change in IC. The ratio of VCE (sat) to IC in this region is called as saturation region.

Cut off region: Both junctions are reverse biased. When the operating point for the transistor enters the cut off region, the transistor is OFF. The transistor is virtually an open circuit between collector and emitter.

Active region:

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Emitter base junction is forward biased and the collector base junction is reverse biased, the transistor acts as a linear amplifier and it is said to be in active region.

Procedure: Input Characteristics: Keeping the voltage across the collector to emitter (VCE) as constant, tabulate the values of base current for various values of base emitter voltage (VBE). Repeat the same procedure for various values of VCE.

Output Characteristics: Keeping the base current as constant, tabulate the values of collector current (IC)

for various values of collector emitter voltage (VCE). Repeat the same procedure for various values of base current IB. Output Characteristics:

IB = (A) VCE IC (V) (mA)

IB = (A) VCE IC (V) (mA)

IB = (A) VCE IC (V) (mA)

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Result: Thus the characteristics of BJT under Common Emitter configuration were determined and plotted.

Circuit Diagram for UJT:

Model Graph: Characteristics of UJT:

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Characteristics of UJT

Aim: To determine the static characteristics of UJT.

Apparatus Required:

S. No. 1. 2.

Apparatus Required RPS Voltmeter

Range (0 30) V (0 10) V

Quantity 2 2

3. 4. 5. 6. 7.

(0 100) mA Resistor 1 k, . k UJT 2N2646 Breadboard Connecting wires Ammeter

1 Each 1 1 1 As Required

Theory: The Uni Junction Transistor is a three terminal device. It has three terminals, emitter, base 1 and base 2. It consists of N type semiconductor bar into which p type semiconductor material is diffused. Contacts are then made into the device.

Operation:

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From the characteristics of UJT up to the peak point, the diode is reverse biased, and hence to the left of the peak point is known as cut off voltage. The voltage corresponding to this point is the peak voltage. In the cut off region PN junction is reverse biased. The device does not conduct, only a small amount of current flows through the device. Once the peak point is reached the device starts conducting. UJT has negative resistance characteristics. The device conducts up to one point which is called valley point. After the valley point the device passes to a saturation region. In this region the device voltage and current reach standard values.

Tabulation for UJT: VB1B2 = (volts) VB1B2 = (volts)

VBE (V)

IE (A)

VBE (V)

IE (A)

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Procedure: The connections are given as per the circuit diagram. The voltage VB1B2 is kept as constant. Varying the RPS voltage, the voltmeter readings of VEB1 and ammeter IE readings are noted down.

 The above process is repeated for various values of VB1B2. At one point the needle deflects back and the current starts increasing. The current must not be increased beyond 25 mA. The graph is plotted between VEB1 and I E.

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Result: Thus the characteristics of UJT were determined and plotted.

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Circuit Diagram for SCR:

Characteristics of SCR

Aim: To obtain the forward and reverse characteristics of SCR and measure the holding and latching current.

Apparatus Required:

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S. No. 1. 2. 3.

4. 5. 6. 7.

Apparatus Range Required RPS (0 30) V Voltmeter (0 30) V Ammeter (0 500) mA, (0 50) mA Resistor SCR Breadboard Connecting wires

Quantity 2 1 Each 1

Each 1 1 1 As Required

Theory: An SCR is a three terminal device. The three terminals are anode, cathode and gate. When the anode is more positive with respect to the cathode, the junctions j1 and j3 are forward biased and the junction j2 is reverse biased.

Only a small leakage current flows through the device. The device is said to be in the forward blocking state or off state. When the anode to cathode voltage is increased to break over value, the junction j2 breaks down and the device starts conducting (ON state). The anode current must be more than the value known as latching current in order to maintain the device in the ON state. Once the SCR starts conducting, it behaves like a conducting diode and gate has no control over the device. The device can be turned off only by bringing the device in below a value known as holding current. The forward voltage drop across the device in the ON state is around one volt. When the cathode voltage is made positive with respect to the anode voltage, the junction j2 is forward biased and the junction j1 and j3 are reverse biased. The device will be in the reverse blocking state and only small leakage current

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flows through the device. The device can be turned ON at forward voltage by applying suitable gate current. Tabulation for SCR:

IG = VAK (V)

mA IG = IA VAK (mA) (V)

mA IG = IA VAK (mA) (V)

mA IA (mA)

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Procedure: The connections are made as per the circuit diagram. RPS is adjusted to the required gate current flows through the device. The VAK is increased in steps by varying the RPS and each step, the corresponding anode current noted down. Reading corresponding to the break over point, latching current, holding current and also noted down. To determine latching current: The forward voltage is increased to break over value, gradually. The device gets turn ON. At this condition, the gate current is removed. If the anode current is less than the latching current, the SCR will go into OFF state immediately. The circuit resistance is repeated until the device remains in ON state even after removing the

gate current. This current is called latching current. To determine holding current: The gate current is removed from bringing the device into ON state. The circuit resistance is increased in steps. The minimum value of anode current at which the SCR remains in the ON state is the holding current.

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Result: Thus the forward and reverse characteristics of SCR are plotted and the holding and latching current were determined.

Circuit Diagram for DIAC:

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Characteristics of DIAC:

Characteristics of DIAC

Aim: To obtain the forward and reverse characteristics of DIAC.

Apparatus Required:

S. No.

Apparatus Required

Range

Quantity

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Page No: . . . . . . . .

1. 2. 3.

4. 5. 6. 7.

(0 30) V (0 30) V (0 100) mA, (0 50) mA Resistor 1 k DIAC Breadboard Connecting wires RPS Voltmeter Ammeter

2 1 Each 1

1 1 1 As Required

Theory: DIAC circuits use the fact that a DIAC conducts current only after certain breakdown voltage has been exceeded. The actual breakdown voltage will depend upon the specification for the particular component type. When the DIAC breakdown voltage occurs, the resistance of the component decreases

abruptly and this leads to a sharp decrease in the voltage drop across the DIAC, and a corresponding increase in the current. The DIAC will remain in its conducting state until the current flow through it drops below a particular value known as the holding current. When the current falls below the holding current, the DIAC switches back to its high resistance, or non conducting state. DIACs are widely used in AC applications and it is found that the device is reset to its non conducting state, each time the voltage on the cycle falls so that the current falls below the holding current.

Tabulation for DIAC: Voltage (VA), V Current (IA), mA

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Procedure: Connections are made as per the circuit diagram. Keep in position minimum so IS and VA across MT1 and MT2 are zero. Switch ON the supply.

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Allow low voltage between MT1 and MT2. Increase VA so IA increases. Repeat it till the device turn ON. Slowly increase gate to MT1 voltage, set particular IG = 7 mA. Keep IG constant and increase VA in step by step when VA increases. IA increases slightly when break over is reached current increases sharply.

Result: Thus the forward and reverse characteristics of DIAC were obtained.

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Characteristics of TRIAC

Aim: To obtain the forward and reverse characteristics of TRIAC.

Apparatus Required:

S. No. 1. 2.

Apparatus Range Required RPS (0 30) V Voltmeter (0 30) V

Quantity 2 1

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3.

4. 5. 6. 7.

(0 100) mA, (0 50) mA Resistor 1 k TRIAC Breadboard Connecting wires Ammeter

Each 1

2 1 1 As Required

Theory: A TRIAC is a bidirectional thyristor (it can conduct in both directions) with three terminals. It is used extensively for control of power in AC circuit. When in operation, a TRIAC is equivalent to two SCRs connected in antiparallel. Its three terminals are usually designated as MT1, MT2 and gate. The V-I characteristics of a TRIAC is based on the terminal MT1 as the reference point. The first

quadrant is the region wherein MT2 is positive with respect to MT1 and vice-versa for the third quadrant. The peak voltage applied across the device in either direction must be less the break over voltage in order to retain control by the gate. A gate current of specified amplitude of either polarity will trigger the TRIAC into conduction in either quadrant, assuming that the device is in a blocking condition initially before the gate signal is applied. The characteristics of a TRIAC are similar to those of an SCR, both in blocking and conducting states, except for the fact that SCR conducts only in the forward direction, whereas the TRIAC conducts in both the directions.

Tabulation for SCR:

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IG = VT (V)

mA IG = IA VT (V) (mA)

mA IG = IA VT (V) (mA)

mA IA (mA)

Procedure: Connections are made as per the circuit diagram.

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Keep in position minimum so Is and VA across MT1 and MT2 are zero. Switch on the supply. Allow low voltage between MT1 and MT2 increase VA so IA increases. Repeat it till the device turn ON. Slowly increases gate to MT1 voltage set particular Ig = 7 mA Keep Ig constant and increases VA in step by step when VA increases. IA increases slightly when break over is reached current increases sharply.

Result: Thus the forward and reverse characteristics of TRIAC were obtained.

Circuit Diagram for JFET:

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MODEL GRAPH FOR JFET: DRAIN CHARACTERISTICS:

Characteristics of JFET

Aim: To draw the drain and transfer characteristics and determine the transconductance, drain resistance and amplification factor of the given JFET.

Apparatus Required:

S. No.

Apparatus

Range

Quantity

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Page No: . . . . . . . .

1. 2. 3. 4. 5. 6. 7.

Required RPS Voltmeter

(0 30) V 2 (0 30) V, Each 1 (0 10) V Ammeter (0 10) 1 mA Resistor 1 k, 1.5 Each 1 k JFET BFW10 1 Breadboard 1 Connecting As wires Required

THEORY: FET is a three terminal device which current is controlled an electrified. The operation of FET depends only on the majority carriers. OPERATION: When VGG applied VDD = 0

The P-type gate and N-type channel constitute PN junction is always reverse biased in JFET operation. The reverse bias is applied by a battery voltage, VGG connected between the gate and the source terminal. When PN junction is reverse biased, the electrons and holes diffuse across the junction and leave behind the positive ions on N side and negative ions on P side. The region containing immobile ions is known as Depletion region. Both regions are heavily doped, then the depletion region symmetrically on both sides. When no VDD is applied the depletion region is a symmetrical and the conductivitys zero, since there are no mobile carriers in the junction. As the reverse bias voltage across the junction is increased, thickness of the depletion region also increases.

Transfer Characteristics:

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Tabulation for JFET: Drain Characteristics: VGS = V VDS ID (V) (mA) VGS = V VDS ID (V) (mA) VGS = V VDS ID (V) (mA)

When VDD applied VGG =0 When no voltage is applied to gate i.e. VGG=0 and VDD is applied between source

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and drain. The electron will flow from source to drain through the channel.

When VDD applied VGG is applied When voltage is applied between the drain and source with a battery VDD, the electrons flows from source to drain through the narrow channel existing between the depletion regions. Transfer Characteristics: The curves shows the relationship between drain current (ID) and gate to source voltage (VGS) for different values of drain source (VDS) voltage. First adjust the drain to source voltage to some suitable value. Then increase the gate to source voltage in small suitable value at each step and record the corresponding values of drain current at each step. If VGS continuously

increasing, the channel width reduced when VGS =VP, the pinch off occurs thus ID =0. Drain Characteristics: It shows the relation between the drain to source voltage (VDS) and drain current (ID). Active Region: In this region for a small increase in drain to source voltage the drain current increases largely. Hence this is called active region. Cut off region: In this region the current never increases even if voltage increases. Hence it is called cutoff region. Saturation region: In this region after increasing from active region, the drain current remains constant over a range of drain to source voltage. After that current pinches off or shoots to a very high

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value. The drain to source voltage at which it occurs is called as pinch off Voltage.

Transfer Characteristics: VDS = V VGS ID (V) (mA) VDS = V VGS ID (V) (mA) VDS = V VGS ID (V) (mA)

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Procedure: The connections are given as shown in circuit diagram. By varying RPS1, VGS is kept constant. Now VDS is varied and corresponding variation in drain current ID is tabulated. This process is repeated for another value of VGS(VGS is set at -1 V and -2Volts) Plot these values on graph with VGS on x axis and ID on Y axis. This gives the drain characteristics. By varying RPS2, it is kept at constant value. Say VDS = 2V.

 Now for various values of VGS, drain current is taken(ID).This is repeated for another value of VDS. Plot these values on graph sheet with VGS on X axis and ID on Y axis. This gives us Transfer characteristics. The various parameters are found as given in formula used.

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Result: Thus the drain and transfer characteristics were determined and the transconductance, drain resistance and amplification factor of the given JFET were found.