DESIGN FEATURE Probing Diodes

Probe On-Wafer novel approach uses horizontal This Diodes coplanar-waveguide probes to
minimize parasitics and maintain accurate RF measurements.
Scott Wartenberg and Chris Mohr
Agilent Technologies, 39201 Cherry St., Newark, CA 94560; (510) 505-5585, (510) 505-5476, FAX: (510) 505-5560, e-mail: scott_wartenberg@ agilent.com, chris_mohr@agilent.com

C processing of nonplanar discrete diodes, such as Schottky and PIN diodes, places the cathode on the top and the anode on the bottom of the wafer (Fig. 1). But in traditional on-wafer RF probing, the probes contact either the top or the bottom surfacenot both. This poses a physical problem for performing RF measurements on these devices. A common solution to this problem is mounting a single die to a connectorized test fixture. But test fixtures are more susceptible to parasitics than on-wafer test methods, and these parasitics can cloud the test results.
ground isolation, calibration, and deembedding.

This article describes a technique for measuring the RF characteristics of nonplanar diodes using horizontal coplanar-waveguide (CPW) RF probes. This method retains all of the advantages of conventional RF onwafer characterization while providing faster design-turnaround time and better model accuracy than the test-fixture approach. The success of the method described here depends on three important techniques:

SYSTEM DESCRIPTION
The new test system centers on an Electroglas probe station, shown in Fig. 2. Figure 3 shows the CPW probe making contact with two diode dice. These diodes are side by side on the wafer surface, aligning with the probe pitch. The ground probe contacts one diode and the signal probe

Die Wafer (Top view)

Cathode (Side view) Anode

1. This figure shows a typical diode wafer and the vertical nature of the die.
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contacts the diode under test. The signal and ground probes are DC-isolated from lab ground. The RF path contains two connectorized DCblocking capacitors. One blocks DC from the vector-network-analyzer (VNA) signal path and the other blocks DC from the VNA ground path. This arrangement permits independent biasing of the signal and ground probes. The voltage on the signal probe is designated as Vs, and the voltage on the ground probe is designated Vg (Fig. 3). Both power supplies connect to a bias tee mounted inline between the blocking capacitors and the diode under test. A third bias, Vch, is supplied to the chuck. Applying a chuck potential keeps leakage current from flowing to the wafers backside. The chuck itself is DC- and AC-isolated from the lab ground. Force and sense lines run to opposite sides of the chuck. HP 4142B programmable power supplies provide the three biases. Plugging equipment into isolation transformers rather than the wall outlet further isolates them from all grounds. The general-purpose interface bus (GPIB) connects to each instrument through opto-isolators. (Without the opto-isolators, ground sneaks in through the GPIB.) The net result of these connections is full DC ground isolation to the diode under test. The AC ground arrives to the diode under test through a single path: the RF cable shield. Calibration deembeds the blocking capacitors, the bias tee, and other system effects. An alumina substrate contains precision impedance standards for on-wafer calibration. Schottky diodes require low-capacitance testing, but parasitic capacitance that is associated with the gold (Au) contact pads can swamp the diodes junction capacitance. To quantify the parasitic capacitance, one can fabricate a dummy wafer with the same pitch and pads as the diodeunder-test wafer. This dummy wafer contains contact pads and no active devices underneath. Measuring it reveals the pad capacitance and any residual chuck capacitance. Isolating ground from the system lowers the parasitic capacitance of the system. De-embedding the ground diode from the measurement should yield the diode under test. One can assume that adjacent diodes are similar. Biasing them identically should yield two diodes with nearly the same characteristics. Another way to deembed the ground diode is to fully forward-bias it. This creates a small resistance from the ground probe to the backside of the wafer. De-embedding the S-parameters shifts the reference plane from the ground probe to the back of the wafer. Since the two diodes are biased independently, locating a problem with either diode becomes simpler. A virtual ground to the wafer backside, along with ground isolation, enables RF probing of nonplanar devices.

A TECHNIQUE FOR MEASURING THE RF CHARACTERISTICS OF NONPLANAR DIODES USING HORIZONTAL COPLANAR-WAVEGUIDE (CPW) RF PROBES IS DESCRIBED. THE SUCCESS OF THE METHOD DEPENDS ON GROUND ISOLATION, CALIBRATION, AND DE-EMBEDDING.

MEASURED RESULTS
Two diode figures of merit are carrier lifetime and series resistance Rs. High-volume production requires these characteristics to be automatically tested on each wafer. Assembling an RF on-wafer test system to the specifications mentioned met this need. Use Caverlys method1.2 to calculate and Rs with S-parameters. A software routine written in IC-CAP, Agilents device-characterization program, enables quick calculation of and Rs. Calibrating the DC path is

(Top view)

RF connector Vs (Side view) Vg

Vch

2. This photograph shows the RF probe system used to test PIN and Schottky diodes on-wafer.

3. The voltage assignments for biasing through the coplanar probes are shown above.
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ues fell to within 15 percent straightforward. Measurof those measured using ing a precision resistor with conventional time-domain the CPW probes detertechniques.3 mines the cable voltage drop. Precision resistors The next phase in the and other standards are development of this system found on Cascade Microwill involve the measuretechs impedance-standard ment of Schottky diodes, substrate (ISS). It can also which have small junction be used to calibrate the RF capacitances. To accurately path. This sets the referand repeatably measure ence plane at the coplanar them, one must de-embed probes. The next step is to the system capacitance move the ground-reference down to the fempto-Farad plane to the back of the level. Acknowledgements wafer. Fully biasing both The authors thank Domingo Figueredo, Steve Randle, Alan Rixon, and Ray Waugh diodes results in a small of Agilent Technologies Wireless Semiconductor Division, Newark, CA for their unwaresistance and reactance vering support. between the signal and References 1. Robert Caverly, RF Technique for ground probes. Model the Determining Ambipolar Carrier Lifetime in PIN RF Switching Diodes, Electronics Letdiode under test as two ters, Vol. 34, No. 23, 12th November 1998, pp. 2277-2278. identical diodes connected 4. This is a map of the wafer containing the PIN diodes. 2. Robert H. Caverly and Gerald Miller, anode to anode. Half the The Small Signal A.C. Impedance of Gallium Arsenide and Silicon P-I-N Diodes, Solid-State Electronics, Vol. 33, No. behavior approximately equals one diode at a fixed bias point, the diode 10, October 1990, pp. 1255-1263. 3. Mohamed Derdouri, Philippe Leturcq, and diode. De-embedding half from the under test can be characterized at Munoz-Yague, A Comparative Study of MethodsAntonio of Measuring Carrier Lifetime in P-I-N Devices, IEEE Transactotal measurement provides the any bias. Figure 4 shows high-fre- tions on Electron Devices, Vol. 27, No. 11, November 1980, diode under test. With the ground quency wafer maps of Rs. These val- pp. 2097-2101.

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