Second International Conference on Emerging Trends in Engineering and Technology, ICETET-09

Computer Aided Design Automation of Low Power, Low Voltage Four Quadrant Transconductance Multiplier
Dr. B. K. Mishra and Mrs. Sandhya Save, Mumbai

AbstractAnalog

and mixed signal (AMS) design are important part of system on chip design (SoC) ,application specific design (ASIC) in short embedded system design which links digital designs to analog world. The IC technologies are scaled to finer feature sizes and circuit applications move to higher frequency bands, analog/RF circuit design faces several new challenges. It is found that AMS design consumes considerable portion of the total chip design cycle time. In contrast to digital systems, the design and verification of analog and mixed signal systems is a challenging task due to the fact there are many CAD tool are available for digital system design where as when it comes to AMS design it is still a fancy. The CMOS multipliers implementation is still a challenging subject especially for low voltage and low power circuit design which is requirement of embedded system. This paper describes automation of the simple four quadrant CMOS multiplier operated in saturation region using a practical methodology for synthesis of analog circuits It involves embedding knowledge into pure simulation based methodology without any intervention from expert designers. In order to evaluate the fitness of the circuit specifications in any iteration of SA, NGSPICE simulation is used. The simulation results confirm the efficiency of presented methodology in determining the device sizes in analog circuits.

produced is up to 50% of chip due to error in the AMS portion of design [1]. Therefore, the demand for a robust AMS validation and verification systems are becoming increasingly important. The cornerstone in ASIC systems are analog and mixed signal (AMS) SoC designs which are required to be interface with real world environment for real world applications[2] . The important functionalities of AMS designs are the processing of analog signal on front and back ends of the system, analog to digital conversion, frequency synthesis, amplification and generating timing references. In addition to this analog circuits are used for biasing which are necessary for stable operation of the system. Many computer aided design (CAD) tools for AMS design have been proposed [4-7] and developed to overcome challenges in the design process of such circuits. For instance, the need to design and improve the quality of more complex integrated systems with the tight constraints of increasing shorter time to market and productivity increase. Such CAD tools and concepts are needed to provide unique insights of into the behaviors and characteristics of integrated circuits to help the designers select the best design strategies. Finally, the need of market is the CAD tools should tackle the crucial activity too correctly and efficiently model as well as simulate performance behaviour of AMS designs. The formal verification of AMS design is relatively young research field and still under developed [4]. Real time analog multiplication of two signals is a very important operation in analog signal processing. The multipliers are not only used as a programming element in systems such as filters, neural networks and as mixers and modulators in communication systems. Although high performance bipolar junction transistor multipliers have been available for some time , the CMOS multipliers implementation is still a challenging subject especially for low voltage and low power circuit design which is requirement of todays embedded system world . Recent years reveled the considerable interest in development of analog multipliers [9-14].

Index Terms Analog chip design, ASIC, CAD, EDA tools, Transconductance multipliers, SoC, in deterministic algorithms.

I. INTRODUCTION he latest technology advancement the transistor sizes shrinks down to deep submicrometer and advanced semiconductor manufacturing are prepared for SOC applications. About 75% of all chips produced today include analog/ mixed systems (AMS) circuits [1].While these chips only make up about 2% of the devices and 20% area. They are taking about 40% of the design efforts whereas the yield

Dr .B. K. Mishra, Principal, Thakur college of Engg. Mumbai-India. (E-mail : drbk.mishra@thakureducation.org) Sandhya S. Save, Ph. D. student, S. N. D. T. University, Mumbai-India. (E-mail: save_sandhya@rediffmail.com)

978-0-7695-3884-6/09 $26.00 2009 IEEE

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VDD K1 VX + VX / 2 Id1 M1 M2 Id2 M3 K2 Vp1 K4 K2 M11 M13 K4 M14 K4 M12 K4 Vp2 Vq2 Vq1 I1 I2 M5 M6 K2 M4 K2 VY -- VY / 2 K1 VX -- VX / 2

VY + VY / 2

R M7 K3 K3 M9

R M10 K3 M8 K3

Fig. 1. Circuit diagram of four quadrant CMOS- Multiplier operated in the saturation region

The classification and adequate survey of analog multipliers based on different transconductance element is listed [8]. The proposed topology is selected for synthesis due to its advantage over above listed multipliers [3]. The circuit analysis of the transconductance multipliers is a tedious job, due complexity of design the automation of analog multipliers were not attempted before. Considering this facts, this paper describes automation of a CMOS four quadrant analog multiplier operated in saturation region. The simulation results show a better combination of linearity, bandwidth, THD than previous MOS multipliers [3, 9-14]. The methodology used is flat circuit synthesis technique, which uses a knowledge based and simulation based optimization method. This technique leads to global optimal synthesis solution. Simulated Annealing (SA)[17]is the in deterministic Algorithm implementation is used as a global optimum search engine. II. CIRCUIT DISCRIPTION CMOS MULTIPLIER The circuit diagram of the selected CMOS multiplier for synthesis is shown in figure 1. Applying standard square-law model for MOS devices M1 and M2 we can write the following equations.

and TN denotes the threshold voltage of NMOS device. Subtracting (1)-(2)

I d 1 I d 2 = 2 K1 (VVDD Vx VTP )vx (3)

Respective formulae for transistors M3-M6 can be written, which will give

I d 1 I d 2 = k2 [(2Vy + v y Vp1 Vq1 2VTN )(Vq1 V p1 ) + (2Vy v y Vp 2 Vq 2 2VTN )(V p 2 Vq 2 )]

(4) Using (2), (4) we get

Vq1 V p1 + V p 2 Vq 2 = vx 2k1 / k2 (5)

By maintaining drain currents of drain current of M3, M6, M7, and M10same (M4, M5, M8, M9) respectively, using equality we get, V p1 Vq 2 = Vq1 V p 2 = v y (6) The differential output current can be written as I d = I1 I 2 (7)

I d 1 = K1 (VVDD Vx vx / 2 VTP )2 (1) I d 2 = K1 (VVDD Vx + vx / 2 VTP )2 (2)

Where

I d = KVxVy = k4 2k1 k2 vx v y (8)

VTP denotes the threshold voltage of PMOS device

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III. SYNTHESIS OF CMOS MULTIPIER The circuit ( Fig 1.) can be divided into following sub groups, differential pair working into saturation region, active loads and level shifters and lastly class AB amplifier with resistive load and (M13, M14). Transistors M1 and M2 act as a differential pair with the applied input stage working in saturation Transistors (M3, M7), (M5, M9), (M4, M8) and (M6, M10) are active loads of the differential input stage and they also realize lever shifters for transistor pairs(M11, M12) and (M13, M14). These cross-coupled devices form a classical AB-class amplifier with resistive load R. Depending on the DC offset in the respective input of this amplifier, we can obtain different values of the linear range conversion of voltage into current. The whole circuit enables us to carry out four-quadrant multiplication of two input signals. Since the equation (8) is obtained by [3] assuming perfect square-law MOS modeling, we can expect some nonlinear distortion of the output signal due to the second order effects. These effects are mobility reduction, channel-length modulation and the body effect. The first two of them are process dependent. That means as the process changes the equation required to be derived again for validity of equation (8). Note that the body effect is greatly reduced in the circuit in Fig.1 since almost all transistors (except M3-M6) have their bulks connected to the sources. But, can not be neglected completely. Note that the biasing voltages relate to the operating point of the circuit. To find the global solution using above design to achieve better specs and reduce area all the time, all the design constraints has to be careful considered, which will be always associated with complex algebraic equation solving . Now consider these facts if width and length of either of the Mosfet is changed that will hamper the performance of above circuit drastically since the value of the output current depends upon the transconducane of the Mosfet. To make the design more robust, and simplify design constraints i.e. to maintain symmetry we keep W (width of the Mosfet) and L s (length of the Mosfet) of mosfets pairs (M1 M2), (M3, M4), (M5, M6), (M7, M8), (M9, M10) (M11, M12) and (M13, M14) equal respectively. The unknown parameters are W and L of all MOS transistors. L min <= L i <= L max W min <= W j <= W max Where value of i , j varies as per sub circuit design . The suggested methodology for synthesis of the four quadrant multiplier is embedded knowledge based Design methodology is modification of pure simulation based approach. Here, some basic knowledge about the circuit, as a set of analog design

rules, is incorporated into the search mechanism. This guides the search engine towards solution in much faster times. It is also process independent and designer doesnt need to have expert knowledge about the in- depth working circuit. This technique leads to global optimal synthesis solution for fixed topology. Simulated Annealing (SA) Algorithm is used as a global optimum search engine. IV. COST FUNCTION Simulated annealing is optimization method applicable for searching for global minimum of cost function. It is objective of the algorithm to maximize the fitness of specifications subject to hard constraints that exits within the system. The cost mapping function evaluates the relative fitness of particular solution specification. The cost mapping function takes the many different objectives into account. The fitness value of specifications is a subject measure of device performance. In this work, the cost function defined as weighted sum performance parameters of the circuit. For synthesis of the four quadrant multiplier cost function is weighted sum of the Bandwidth, linearity, area, THD, power, etc and can be represented as

cos t = k wi * f i
i =1

Where k = constant 0<

-3

k <1
i

wi =assigned weight coefficient of performance parameter

8 6 4 2 0 -2 -4 -6 -8 x 10

-0.25 -0.2 -0.15 -0.1 -0.05

0.05

0.1

0.15

0.2

0.25

Fig. 2. Simulated transfer characteristics of four quadrant CMOS multiplier with Vx as a parameter

V. SYNTHESIS RESULTS We synthesized the four quadrant analog multiplier using the suggested methodology. The implementation of methodology is done using standard Perl. The source code consists of about 900 lines. The code was complied on a PC with Intel Pentium processor at 2.6 GHz, (256MB RAM). The Values of W s and L s for different MOS transistors are changed randomly during synthesis process.

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8 6 4 2 0 -2 -4 -6

x 10

-3

Area in m2,

is not one). The area calculation varies as per layout rule. The circuit performance characteristics are shown in Fig. 2, 3, 4. The Fig 2and 3 shows the transfer characteristics curve of the circuit as Vx and Vy parameters, respectively. The Fig. 4 shows the ac frequency response of the amplifier. Most of the parameters have been found in reported results are better than desired values in [3, 15, and 16] except -3db frequency when compared with the results of [3]. Table1. shows the comparative results of different multipliers.
x 10
-4

0 gives fixed area,

1(if it

-8

-0.25 -0.2 -0.15 -0.1 -0.05

0.05

0.1

0.15

0.2

0.25

Fig3. Simulated transfer characteristics of four quadrant CMOS multiplier with Vy as a paprameter

The four quadrant transconductance specifications to be satisfied are

multipliers
Output

Bandwidth >= 260MHz THD < 0.035%@ 0.3V(p-p) at 1MHz Area < 100m2 Power =minimum

The first parameter can be directly measured by AC analysis in ngSpice. The total harmonic distortion (THD) is calculated using Fourier analysis. The linearity is calculated using DC analysis in ngSpice. All this parameters are generated using appropriate test bench analysis (Fig.4.) which is incorporated in flat net list as per analysis type. The generated flat net list is run in spice batch mode to compare the results with given constraints list. The spice net list is simulated using BSIM3V3, Level49 model. The biasing voltages Vx and Vy has been are set to0.3V and 0.9V respectively. The power consumption is about 0.052mW.The achieved transistor sizes are (W/L) M1-M6 =2/1, (W/L) M7-M14 =7/1.
Test Bench

4 5 6 Frequency in Logscale

Fig. 4. The obtained frequency response of four quadrant CMOS multiplier Circuit This work [3] [15] [16] Supply Voltage 1.2V 1.2V 3V 1.5V THD 0.025%@ 0.3V(pp) 0.03%@ 0.3 V(pp) <1%@ 1.4V(pp) 0.026%@ 0.6V(pp) Bandwidth 550Mhz 620Mhz 140Mhz 620Mhz Area 68m2 -

DC Transfer Char

DC Analysis

Bandwidth AC Analysis

THD
Fourier analysis

Table 1.Comaprision between obtained results by suggested methodology and recently reported multipliers

Fig4. The test bench condition incorporated in spice netlist

VI.

CONCLUSION AND FUTURE SCOPE

For area calculation analytic equation are incorporated in the program. The analytical equations are shown below.

Area = 0 + 2 Wi * Li
i =1

where n = Number of Mosfet

A practical methodology for synthesis of analog four quadrant transconductance multiplier circuit is presented in this paper. This multiplier is characterized by very low power consumption, works with one supply voltage and required less area. Using this methodology, the in depth circuit analysis of large circuit can avoided. This can save significant design time and efforts at the same when model parameters are

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varying drastically as per technology changes. Experimental results show that the analog design rules in the used methodology, guide the search engine in producing constraint satisfying solution, in very short times. VII. REFERENCE
[1] A. Shah, Technology migration of a high performance cmos amplifier using an automated front-to-back analog design flow, in Proc. Design, Automation Test Europe, Paris, France, march 2002. [2] K. Kundert, L. H. Chang, D. Jefferies, G. Lamant, E. Malavasi, F. Sandig Design of mixed signal system on chip , IEEE trans. CAD, vol.19, pp.15611571, 2000. [3] Szczepanski and S.Koziel, , 1.2 V low power four quadrant CMOS transconductance multiplier operating in saturation region,pp.10161019,ISCAS-2004. [4] M. Zaki,S. Tahar,G. BoisW. Nye, D. Riley, A. Sangiovanni-Vicentelli, and Atits, Forrmal verification of analog and mixed signal design : A surveys,Microelectronics journal(39), pp.501-519,2008.

[17]Alex Cave, Saeid Nahavandi, Abbas Kouszani, Simulation optimization for process scheduling though simulated annealing, in Proceedings of the 2002 Winter Simulation Conf.

VIII. BIOGRAPHIES

[5] R. Harjani, R. Rutenbar, and L. Carley, OASYS: a framework for analog circuit synthesis, IEEE Trans CAD, vol. 8, pp. 1247-1266, December 1989. [6] M.G.R. Degrauwe, , Idac: An interactive design tool for analog cmos circuits,in IEEE Journal of Solid-State Circuits, pp. sc-22(6):1116, Dec 1987. [7] Sherif Hammouda, Mohamed Dessouky, Mohamed Tawfik and Wael Badawy, , A Fully Automated Approach for Analog Circuit Reuse,Proc. of the 4th IEEE Int. Workshop on System-on-Chip for Real-Time Applications (IWSOC04). [8] G. Han, E. Sanchez-Sinencio, CMOS Transconductance Multipliers: A Tutorial, IEEE Trans. Circuits Systems II, CAS-45, (12), pp. 1550-1562, 1998 [9] N. Saxena, J.J. Clark, A Four-Quadrant CMOS Analog Multiplier for Analog Neural Networks, IEEE J. Solid-State Circuits SC-29, (6), pp. 746749, 1994 [10] P.R. Kinget, M.S.J. Steyaert, A 1-GHz CMOS Up-Conversion Mixer, IEEE J. Solid-State Circuits SC-32, (3), pp. 370-376, 1997 [11] S.-I. Liu, ,Low voltage CMOS Four-Quadrant Multiplier, Electron. Lett., Vol.30, No.25, pp. 2125-2126, 1994 [12] C.J. Debono, F. Maloberti, J. Micallef, On the Design of Lo w-Voltage, Low-Power CMOS Analog Multipliers for RF Applications IEEE Trans. VLSI Systems, Vol.10, No.2, pp.168-174, 2002. [13] B. Pankiewicz, S. Szczepanski, Y. Sun, CMOS Level-Shifter Buffer and Four-Quadrant Analog Multiplier .Proc Int. Conference Mixed Design Integrated Circuits and Systems (MIXDES) Poland, pp. 251-254, 2002 [14] C.A. De La Cruz-Blas, A.J. Lopez-Martin A. Carlosena, 1.5V FourQuadrant CMOS Current Multiplier/Divider, Electron. Lett. , Vol. 39, No. 5, pp. 434-436, 2003 [15]A. Hyogo, Y. Fukutomi, K. Sekine, Low voltage four-quadrant analog multiplier using square-root circuit based on CMOS pair, in Proc. IEEE Symp Circuits Syst, ISCAS, Vol.2, pp.274-277, 1999. [16]A.H. Ismail, A.M. Soliman, A novel CMOS four q uadrant multiplier based on linearization of the long tail differential pair, in Proc. IEEE Symp. Circuit s Syst. ISCAS, Vol.5, pp.485 -488, 2000.

Sandhya Save was born in Mumbai on May 23, 1978. She has completed her Bachelor of Engineering in Electronics from Mumbai University and completed M. Tech in Electronics from VJTI College of Engg., Mumbai University. Currently she is pursing PhD from SNDT university. She is working as an Asst. Professor in Electronics Dept of Thakur College of Engineering & Technology. Her special fields of interest included analog devices and VLSI.

Dr. B. K. Mishra was born in the year 1966. He has completed his Bachelor of Engineering in Electronics from Amravati University in the year 1988, M.E. in Electronics and Communication Engineering in 1998 from Birla Institute of Technology, Ranchi. He has teaching and administrative experience of more than 18 years with research experience of 4 years. He has published more than 30 technical papers in National and International Journals including the proceedings of National and International conferences. He has also published six text books in the area of Electronics Devices and Circuits and Communication. His area of interest includes Electronics Devices and circuits. At present he is guiding 6 Ph. D. scholars. Currently he is working as a Principal of Thakur College of Engineering & Technology since June 2006.

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