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Design Techniques for NBTI-Tolerant Power-Gating Architectures

Andrea Calimera, Member, IEEE, Enrico Macii, Fellow, IEEE, and Massimo Poncino, Member, IEEE
AbstractWhile negative bias temperature instability (NBTI) effects on logic gates are of major concern for the reliability of digital circuits, they become even more critical when considering the components for which even minimal parametric variations impact the lifetime of the overall circuit. pMOS header transistors used in power-gated architectures are one relevant example of such components. For these types of devices, an NBTI-induced current capability degradation translates into a larger IR-drop effect on the virtual-Vdd rail, which unconditionally affects the performance and, thus, the reliability of all power-gated cells. In this brief, we address the problem of designing NBTI-tolerant power-gating architectures. We propose a set of efcient NBTI-aware circuit design solutions, including both static and dynamic strategies, that aim at improving the lifetime stability of power-gated circuits by means of oversizing, body biasing, and stress-probability reduction while minimizing the design overheads. Experimental results prove the effectiveness of such techniques when applied to a suite of benchmarks mapped onto a 45-nm industrial CMOS technology library. In particular, we prove that it is possible to achieve more than ten times of lifetime extension with respect to a traditional power-gating approach. Index TermsNegative bias temperature instability (NBTI), power gating, reliability, sleep transistor.

I. I NTRODUCTION CALING OF MOS device geometries poses hard limitations on the development of new generations of integrated circuits. In particular, reliability has been indicated as one of the most serious concerns [1], [2]. Adverse on-chip operating conditions, characterized by extremely high substrate temperature, accelerate the degradation of the electromechanical properties of both active (i.e., transistors) and passive (i.e., interconnects) devices. Electromigration, hot-carrier injection, and time-dependent dielectric breakdown have been indicated as the main responsible of reliability decrease [3]. If we restrict our attention to the aging sources, negative bias temperature instability (NBTI) has emerged as the dominant factor in determining the lifetime of digital devices [4]. In CMOS circuits, NBTI effects occur in p-type transistors when a logic 0 is applied to the gate terminal (gate-to-source voltage Vgs = Vdd , i.e., negative bias). Under this condition, called the stress state, the magnitude of the threshold voltage (Vth ) increases over time, resulting in a degradation of the drive

Manuscript received July 17, 2010; revised October 10, 2010; accepted January 29, 2012. Date of publication March 8, 2012; date of current version April 11, 2012. This paper was recommended by Associate Editor C.-C. Wang. The authors are with the Dipartimento di Automatica e Informatica, Politecnico di Torino, 10129, Torino, Italy. Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TCSII.2012.2188457

current. In contrast, when a logic 1 is applied to the gate terminal (Vgs = 0), NBTI stress is actually removed. The latter condition, called the recovery state, induces a progressive yet partial recovery of the Vth . The impact of NBTI in random logic manifests itself as an increase of the propagation delay. Increased Vth reduces in fact the drive current of individual gates, which thus require more time to propagate the input signals, and might then no longer meet the timing constraints [5]. To overcome this issue, a number of recent works proposed various design techniques to compensate and/or tolerate such NBTI-induced effects [6][8]. The basic idea behind these approaches is to identify the gates which are responsible for the overall performance degradation (i.e., critical cells) and selectively apply gate/transistor resizing [6] to guarantee larger design margin and/or circuit transformation [7] (like NBTI-aware synthesis and technology mapping) to maximize the use of the standard cells that show smaller NBTI sensitivity. Different from these static design-time solutions, the authors of [8] propose the use of adaptive techniques to dynamically compensate for NBTI effects during the lifetime of the circuit. Such solutions are effective because the total delay degradation of a circuit is usually signicantly smaller than that of individual devices, on the order of a few percent per year of operation [6]. This is mainly due to the fact that the propagation delay of a circuit consists of the sum of rising and falling transitions, and NBTI only affects rising transitions. Moreover, the stress time of some cell may be extremely low due to the logical structure of the circuit, thus masking the aging effect of 0 values. Nevertheless, there exist special devices for which the stress time is dominant, which thus represent a concentrated source of timing failure [9]. For these components, even a minimal variation on the electrical parameters drastically impacts the performance of the overall circuit. The sleep transistors used in power-gated architectures are a signicant example of such devices: Due to accumulated active periods (i.e., when the circuit is not idle), NBTI effects induce a progressive increase of the channel resistance of the sleep transistors, which, in turn, causes a larger IR drop between the real Vdd and the virtual Vdd (at which the gated cells are connected). As a nal result, the propagation delay of all the gated cells suffers from a sensible increase, no matter if it is a rising or a falling transition, independently of the stress time of the local input signals. While standard power-gating ows [11][19] ignore the deleterious effects of NBTI on sleep transistors, in this brief, we present several design techniques for an effective implementation of NBTI-tolerant power-gating architectures. The proposed solutions, which exploit static and dynamic strategies, aim at compensating the aging effects on the sleep transistors,

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thus guaranteeing maximum lifetime stability of the powergated circuits. We describe seven design solutions representing different combinations of three main mechanisms used to compensate Vth increase: 1) sleep-transistor oversizing (OS), 2) body biasing (BB), and 3) equivalent stress-time reduction of the sleep-transistor driving signal. Each technique, characterized by its own aging-versus-leakage tradeoff, is applied to several benchmarks, which have been synthesized onto a 45-nm industrial CMOS technology using a power-driven design ow. Experimental results dene the basic guidelines to be used for the design of sleep transistors that are NBTI tolerant and emphasize the effectiveness of the proposed design methodologies in terms of lifetime extension (more than ten times in the best case) and leakage overhead. II. BACKGROUND A. BTI Effects on PMOS Transistor BTI has emerged as the most insidious source of permanent time-dependent variation of transistor characteristics. The mostly affected parameter is the threshold voltage Vth , whose absolute value increases over time, thus causing the shift of other electrical parameters, such as the drive current Ids and the transconductance Gm . Even if both n- and p-type MOS transistors suffer from BTI-induced degradation, at typical operating elds of SiO2 , BTI is relevant only for pMOS transistors under negative gate bias NBTI (i.e., Vgs < 0). We summarize here the basic factors that impact NBTI effects using, as reference, the reactivationdiffusion model [10]. A simplied version of such a model is described in the following equations: Stress : Vgs = Vdd Vth ks e Recovery : Vgs = 0 Vth kr
Ea kT

modeled as a periodic one with the same amount of stress time, thus allowing the use signal probabilities for the evaluation of the effective aging. In other words, NBTI can be modeled as a function of the gate signal stress probability Vth = K t 4
1

(3)

where K is a parameter which lumps all the technological constants and considers the operating conditions of the device. B. Power-Gating Basics Power gating is one of the most effective leakage reduction techniques for deep-submicrometer technologies. It is based on the principle of adding switches (i.e., sleep transistors) in series with the pull-up and/or pull-down network of logic blocks, thus creating an intermediate virtual rail (i.e., virtual Vdd ) or virtual ground (i.e., virtual GND). In the idle mode, the sleep transistor is off, and the pull-up/pull-down path is cut. In this condition, the logic gates are ideally isolated from power supply/ground rail and sensibly reduce their subthreshold leakage current. Conversely, in the active mode, the sleep transistor is on; the normal circuit functionality is guaranteed, but due to the onresistance of the sleep transistor, the logic gates connected to it are slowed down. Therefore, proper sizing of the sleep transistor, and thus its on-resistance, is of primary importance when designing power-gated architectures. Although the power-gating version using a footer has been historically very popular in the literature [11], [12], the use of header pMOS switches has also become widespread [13], [14]. The two choices represent different tradeoffs between sleep-transistor area and leakage. On one hand, nMOS sleep transistors are more conductive than pMOS ones; thus, from the area point of view, the use of nMOS sleep transistors is preferable. On the other hand, pMOS transistors have a better leakage characteristic than nMOS. Another important issue in the choice of pMOS or nMOS sleep transistors is technology [15]. Usage of nMOS sleep transistors requires triple-well CMOS process; conversely, in the case of a pMOS sleep transistor, the p-substrate easily separates its n-well from other n-wells of pMOS transistors used in normal cells. For this reason, pMOS header transistors are usually preferred by semiconductor vendors. III. C HARACTERIZATION OF NBTI E FFECTS ON P OWER -G ATED C IRCUITS This section describes the customized SPICE-based framework that we have implemented for the assessment of NBTIinduced effects on power-gated circuits. Fig. 1 shows the ow of the proposed two-phase methodology. In the rst phase, the aging of the sleep transistor is evaluated in terms of current capability degradation. The latter is then used in the second phase to estimate the delay degradation of the power-gated logic circuit. Sleep-Transistor Current Capability Degradation: This analysis consists of a two-step simulation: the prestress simulation phase, in which we estimate the aging effects on the pMOS sleep transistor, and the poststress simulation phase, in which the stress information is integrated into the pMOS device parameters.

(t tstr ) 4

(1) (2)

t trcv t

where kv and kr are two parameters whose magnitude depends on a few technological parameters (like channel strain and nitrogen concentration), k is the Boltzmann constant, T is the local operating temperature of the device, Ea is a technologyindependent parameter that guarantees the convergence of the model, and tstr and trcv correspond to the times at which the stress and the recovery phases begin, respectively. The above equations highlight the relevant features of NBTI. 1) During stress phases (t > tstr ), the shift in Vth increases with time as a power law exponent of one-fourth, while it shows an exponential relationship with temperature. 2) As soon as the stress is removed (t > trcv ), a signicant fraction of broken SiH bonds are annealed, thus inducing a partial Vth recovery. 3) The Vth recovery is independent of temperature and transistor BB. 4) The nal Vth is frequency independent; in other terms, it is the total stress time that matters. From the aforementioned observations, it is possible to derive an additional property; since aging is independent of the frequency of the waveform applied to the gate terminal and it is the total stress time that matters, a generic waveform can be

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IV. NBTI-AWARE S LEEP -T RANSISTOR D ESIGN Since NBTI effects on sleep transistors induce performance slowdown throughout the lifetime of the circuit, it is important to identify a set of effective low-cost NBTI-tolerant implementations of power gating. In the sequel, we present some possible solutions, in which aging is controlled by means of three basic strategies, i.e., transistor OS, BB, and control of equivalent stress probability. Each technique results into some area and leakage overheads; thus, it is possible to combine them into hybrid solutions, which can achieve better tradeoffs between leakage and aging. We will rst outline the basic features of the three strategies and eventually describe their possible variants. Sleep-Transistor OS: The pMOS sleep transistor can be up sized in order to compensate for NBTI-induced current capability degradation over time. The size of the transistor does not have a direct impact on the amount of Vth shift, i.e., it is not an explicit parameter in the equation describing the drift in threshold voltage. Rather, using a larger sleep transistor implies larger currents, thus compensating the current degradation induced by NBTI. In other words, up sizing provides a larger guard band and, thus, more functionality margin. Conceptually, if the size of the sleep transistor that guarantees the functionality of the circuit at time zero is Wsleep and the drain current degradation after the required lifetime is , then the resulting oversized sleep-transistor width is simply given by Wsleep = Wsleep (1 + ). Needless to say, increasing the size of the sleep transistor results in larger area, larger dynamic power, and increased leakage current. All the three overheads increase linearly with . BB: In a standard CMOS conguration, the bulk terminal of each pMOS transistor is connected to the power supply (i.e., Vb = Vdd ). However, by varying the bulk voltage Vb , it is possible to control the body effect and thus modulate the threshold voltage Vth and the current drive of the transistors: Vth decreases for Vb < Vdd [forward body bias (FBB)] and increases for Vb > Vdd [reverse body bias (RBB)]. The two methods have been widely used for controlling process variability (specically, FBB, to speed up devices showing degraded performance after fabrication), and for low-power design (RBB, to reduce the subthreshold leakage by selectively raising Vth ). BB represents an attractive solution for NBTI-aware design. At rst glance, one may imagine that FBB can be used, alone, to completely recover any degradation in the sleep transistor Vth and bring the drain current to exactly meet the target specication. The amount of FBB, however, is severely constrained by several issues. First, Vb must be larger enough to guarantee the correct functionality of the transistor, namely, source-to-bulk voltage larger than the built-in potential of the p-n junctions. Second, but not for importance, the reduction in Vth caused by FBB translates into an exponential increase of subthreshold leakage (in fact, Isub eVth /kb T ). Therefore, in order to alleviate such leakage overhead, it is preferable to apply FBB in conjunction with RBB, following an adaptive BB (ABB) style: During the active mode, when the sleep transistor is turned on (i.e., under NBTI stress), applying FBB guarantees more current margin, extending the lifetime of the entire circuit; during idle periods, using RBB reduces the static power consumption.

Fig. 1.

NBTI-characterization ow for pMOS sleep transistor.

According to the properties of the sleep signal (dened by its zero static probability and voltage level), and the user-dened environmental setup (Vdd voltage, virtual-Vdd voltage, temperature, BB Vbs , and temperature), the prestress simulation computes the aging of the pMOS sleep transistor after a userdened usage time. The amount of aging, calculated on the base of the builtin aging models integrated into Synopsys HSPICE and the technology parameters provided by the silicon vendor, is then translated and annotated into device parameter degradation, i.e., threshold voltage degradation (i.e., Vth ). As shown in Fig. 1, during poststress simulation, the NBTI-induced Vth degradation is modeled using a voltage source on the gate terminal of the sleep transistor. At the end of the pre- and poststress simulations, we have a complete characterization of the current drive prole before and after NBTI stress. In other words, we are able to estimate the degradation over time of the maximum current drained by the pMOS sleep transistor (Ids = Ids Ids ), for a given value of usage time and for any operating condition. Circuit Delay Degradation: The knowledge of the degraded value of the maximum drain current Ids allows estimating the actual delay degradation of the power-gated logic block, as follows. Since the sleep transistor operates in the triode region, it behaves as a resistor. The value of such a resistance after aging is given by Rsleep = (Vdd VVdd )/Ids . (4)

Given the active current Ion drained by the power-gated circuit from the virtual rail,1 we can now estimate the new voltage drop across the sleep transistor as VVdd = Rsleep Ion . (5)

The IR-drop voltage between the real Vdd and the virtual Vdd is nally used to estimate the actual delay degradation of the gated logic block.2
1 We consider as I on the worst case active current drained by the circuit at time zero. 2 Technology-dependent derating factors are used to estimate the delay variation due to VVdd variation.

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It is important to notice that, although NBTI recovery is not directly affected by bulk polarization, the substrate under RBB is subject to substrate hot-carrier injection [2]. Under this condition, the carriers in the substrate, which are driven by the substrate eld toward the SiSiO2 interface, may gain enough kinetic energy to overcome the surface energy barrier and get injected into the gate oxide, where some of them are trapped, inducing Vth instability. Stress-Probability Control (p0): As described in Section II, NBTI aging effects occur only during stress; therefore, the larger the zero probability of the sleep signal, the larger the aging of the sleep-transistor characteristics. However, the static zero probability of the sleep signal is not a free design variable by itself; it depends on the actual workload and the resulting idle periods of the circuit. Nevertheless, it is possible to distribute the NBTI-induced stress over multiple sleep transistors. This idea of multiple parallel sleep transistors has been also used to dynamically compensate for performance variations of different nature (temperature, variability, and NBTI aging) [17], [18]. For example, suppose that we duplicate the sleep transistor (i.e., two sleep transistors ST1 and ST2 ), so that the stress period Tstress (i.e., the time in which the sleep signal is at zero) can be time multiplexed over the two transistors. This implies that, for the rst half period of duration Tstress /2, ST 1 is on and ST 2 is off while, for the other half period, ST 1 is off and ST 2 is on. Then, both ST1 and ST2 are stressed for half time. This scheme can be generalized by assuming that the original sleep transistor consists of n equally sized parallel subsleep transistors (as it is usually done) and adding m redundant subsleep transistors. Since, at each period, only n over n + m transistors must be activated, in order to guarantee the proper current capability, the new zero probability P(Vg =0) becomes P(Vg =0) = P(Vg =0) [1 m/(n + m)] . (6)

Fig. 2.

Normalized lifetime of the ISCAS85 benchmarks.

From an overhead viewpoint, this approach is equivalent to oversizing the sleep transistor by a factor = 1 + m/n. Furthermore, we should consider the area and power overheads required to implement the selection of m signals out of n + m ones (e.g., a shift register of n + m bits plus the proper wiring). Hybrid Approaches: The OS and p0 strategies can extend the lifetime of the power-gated circuit at the cost of both increased area and leakage. Integrating such techniques with RBB might offer a solution to achieve the best tradeoff between reliability and power efciency. While, in the standard approaches, the bulk voltage Vb of a pMOS is set, statically, to its nominal value Vdd , here, we consider a dynamic approach in which, for both OS and p0, the sleep transistor can be reverse biased. V. E XPERIMENTAL R ESULTS For the validation of the proposed power-gating strategies, we used as benchmarks the circuits in the ISCAS85 suite [20]. Each circuit is assumed to be fully power gated (i.e., all cells are connected to the same virtual-Vdd rail) and was mapped onto a 45-nm CMOS library by STMicroelectronics using Synopsys Design Compiler for synthesis and Synopsys ICCompiler for the placement of the cells. The methodology presented in [16] was adopted to determine the maximum active current Ion of

each benchmark. The resulting current values were then used as upper bounds to the sizing of the sleep transistors. The nominal width of the sleep transistor Wsleep is chosen so that the maximum virtual-Vdd voltage drop across it equals 10% of Vdd (110 mV) when Ion is owing. Although this voltage drop may appear as a relatively large value, it corresponds to a minimum leakage choice, which is the main target of our optimization ow. The sleep transistor is customly designed as a standard cell that can be seamlessly used by the synthesis engine [19]; as such, since the height of a standard cell is constrained, the desired width is obtained by putting multiple transistors in parallel. The analysis framework described in Section III has been implemented using HSPICE built-in reliability analysis model as a basis. This allowed us to explore NBTI-aware design techniques in a practical fully automated analysis environment. Ad hoc TCL scripts have been written to synchronize preand poststress simulations, as well as the estimation of delay degradation Dp of the power-gated logic block, which is based on technology-dependent propagation delay derating factors (Dp/Vdd ). Fig. 2 shows the lifetime results for the ISCAS85 benchmarks. The plot shows the normalized results with respect to the case of a standard power-gating approach (2.1 years). We dene lifetime as the time required by the circuit to degrade its performance by 15% with respect to its time-zero performance. Each group of bars denotes the lifetime for a benchmark using the various strategies. The group marked with avg represents the average over all benchmarks. Results refer to a given probability (namely, 40%) of the sleep signal, i.e., percent of time spent in the idle state; the latter is a parameter of the characterization step, and any value can be used. Aging will clearly be proportional to the time spent in the idle state. Before discussing the results, we rst detail the specic parameters that identify the various schemes. 1) OS: a sleep transistor with size 20% larger than the nominal case ( = 0.2). 2) FBB: Vb = 0.75 Vdd . 3) RBB: Vb = 2.5 Vdd . 4) p0: Equivalent stress probability of the sleep signal is lowered to 50% using m = n. 5) ABB: Vb = 0.75 Vdd during active periods, and Vb = 2.5 Vdd during idle periods. OS+RBB and p0+RBB are the combinations of the basic solutions.

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TABLE I L EAKAGE OVERHEAD PER Y EAR OF L IFETIME E XTENSION

the threshold voltage results in a signicant degradation of the virtual-Vdd line, with direct consequences on the performance of the power-gated circuit. We have addressed this critical issue by presenting several design solutions for the implementation of NBTI-tolerant power-gating architectures. The analysis of the aging-versusleakage tradeoff, obtained through a SPICE-based exploration framework, shows that, while oversizing the sleep transistor gives the best results in terms of absolute lifetime extension (8.2 on average), a hybrid solution that combines OS with reverse BB yields the best balance between aging and leakage, namely, a 7.7 lifetime extension with negligible leakage overhead. R EFERENCES
[1] M. A. Alam, Reliability- and process-variation aware design of integrated circuits, Microelectron. Reliab., vol. 48, no. 8/9, pp. 11141122, Aug./Sep. 2008. [2] Semiconductor Reliability Handbook, Renesas Electronics, Tokyo, Japan, Nov. 2008. [3] J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, The impact of technology scaling on lifetime reliability, in Proc. IEEE Int. Conf. DSN, Jun. 2004, pp. 177186. [4] G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D. L. Kwong, Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling, IEEE Electron Device Lett., vol. 23, no. 12, pp. 734736, Dec. 2002. [5] W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, and Y. Cao, The impact of NBTI on the performance of combinational and sequential circuits, in Proc. ACM/IEEE DAC, Jun. 2007, pp. 364369. [6] B. C. Paul, K. Kang, H. Kuuoglu, M. A. Alam, and K. Roy, Impact of NBTI on the temporal performance degradation of digital circuits, IEEE Electron Device Lett., vol. 26, no. 8, pp. 560562, Aug. 2005. [7] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, NBTI-aware synthesis of digital circuits, in Proc. ACM/IEEE DAC, Jun. 2007, pp. 370375. [8] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits, in Proc. IEEE ASP-DAC, Jan. 2009, pp. 284289. [9] A. Calimera, E. Macii, and M. Poncino, NBTI-aware sleep transistor design for reliable power-gating, in Proc. ACM/IEEE GLSVLSI, May 2009, pp. 333338. [10] M. A. Alam and S. Mahapatra, A comprehensive model of PMOS NBTI degradation, Microelectron. Reliab., vol. 45, no. 1, pp. 7181, Jan. 2005. [11] M. Anis, S. Areibi, and M. Elmasry, Design and optimization of multithreshold CMOS (MTCMOS) circuits, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 10, pp. 13241342, Oct. 2003. [12] S. Kim, S. V. Kosonocky, D. R. Knebel, K. Stawiasz, and M. C. Papaefthymiou, A multi-mode power gating structure for lowvoltage deep-submicron CMOS ICs, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 7, pp. 586590, Jul. 2007. [13] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual for System-on-Chip Design. New York: SpringerVerlag, 2007. [14] H. O. Kim and Y. Shin, Semicustom design methodology of power gated circuits for low leakage applications, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 6, pp. 512516, Jun. 2007. [15] E. Pakbaznia, F. Fallah, and M. Pedram, Charge recycling in powergated CMOS circuits, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 10, pp. 17981811, Oct. 2008. [16] A. Sathanur, A. Calimera, L. Benini, A. Macii, E. Macii, and M. Poncino, Efcient computation of discharge current upper bounds for clustered sleep transistor sizing, in Proc. IEEE DATE, Apr. 2007, pp. 16. [17] H. Deogun, D. Sylvester, R. Rao, and K. Nowka, Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength, in Proc. IEEE Syst.-on-Chip Conf., Nov. 2005, pp. 147150. [18] A. Sinkar and N. Kim, Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits, in Proc. IEEE ISQED, Mar. 2010, pp. 791796. [19] A. Calimera, L. Benini, A. Macii, E. Macii, and M. Poncino, Design of a exible reactivation cell for safe power-mode transition in powergated circuits, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 19791993, Sep. 2009. [20] F. Brglez and H. Fujiwara, A neutral netlist of 10 combinational benchmark circuits, in Proc. IEEE ISCAS, May 1985, pp. 695698.

As the bar chart shows, all the proposed techniques but RBB yield signicant improvements of the lifetime. RBB is however reported for the sake of comparison as a purely leakage-oriented solution. As a matter of fact, even the combination of RBB with other schemes negatively impacts the effectiveness of the baseline scheme. In general, OS yields the best results, extending lifetime by more than eight times with respect to the baseline. Combination with RBB (i.e, OSRBB) does not signicantly affect the effectiveness of OS. FBB and ABB have comparable results (about 5 lifetime improvement), while p0 is not very effective. Lifetime results must be weighted against their overheads, area, and particularly leakage. Concerning area, the various methods have comparable overheads, ranging from 6% (FBB and RBB) to 8.2% (p0). These gures refer to the overall area overhead, i.e., with respect to the original power-gated circuit. The variance of leakage overhead is much larger, as shown in Table I. The table reports the percentage of leakage power penalty paid for each year of lifetime extension, i.e., leakage/lifetime ratio (LLR). A smaller LLR clearly identies a better solution, i.e., less leakage to obtain the same lifetime. We can observe that OS remains very competitive even from the leakage standpoint (LLR = 2.38%), whereas FBB alone expectedly has the highest LLR (32.76% on average), ending up being the worst scheme. ABB, even if it reduces the leakage cost, owing to the application of reverse bias, still has a signicant overhead (16.2% on average). p0, in spite of its modest lifetime extension, appears to also be quite costly LLR = 28.8% on average, due to large area overhead. The two hybrid solutions justify the introduction of RBB as a strategy: OS+RBB and p0+RBB, although characterized by a reduced lifetime extension due to the use of RBB, can offer the best tradeoff and can be safely applied to extend the lifetime while maintaining under control the standby consumption. OS+RBB in particular has negligible overhead. As a last observation, the RBB entry is not considered here since it actually reduces lifetime, so its LLR would not be meaningful. VI. C ONCLUSION NBTI negatively affects the reliability of sub-100-nm circuits. The pMOS sleep transistors used to implement power gating are a clear example where this situation occurs with dramatic effects. For these devices, even a small change in