UNIT III MICROPROCESSORS MICROPROCESSOR

A microprocessor is a clock-driven semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale integration (LSI) or very-large-scale integration (VLSI) technique. The microprocessor is capable of performing various computing functions and making decisions to change the sequence of program execution. In large computers, a CPU performs these computing functions.The Microprocessor resembles a CPU exactly. The microprocessor is in many ways similar to the CPU, but includes all the logic circuitry including the control unit, on one chip. The microprocessor can be divided into three segments for the sake of clarity. They are: arithmetic/logic unit (ALU), register array, and control unit. A comparison between a microprocessor, and a computer is shown below:

Arithmetic/Logic Unit: This is the area of the microprocessor where various computing functions are performed on data. The ALU unit performs such arithmetic operations as addition and subtraction, and such logic operations as AND, OR, and exclusive OR. Register Array: This area of the microprocessor consists of various registers identified by letters such as B, C, D, E, H, and L. These registers are primarily used to store data temporarily during the execution of a program and are accessible to the user through instructions. Control Unit: The control unit provides the necessary timing and control signals to all the operations in the microcomputer. It controls the flow of data between the microprocessor and memory and peripherals. Memory: Memory stores such binary information as instructions and data, and provides that information to the microprocessor whenever necessary. To execute programs, the microprocessor reads instructions and data from memory and performs the computing operations in its ALU section. Results are either transferred to the output section for display or stored in memory for later use. Read-Only memory (ROM) and Read/Write memory (R/WM), popularly known as RandomAccess memory (RAM).

1. The ROM is used to store programs that do not need alterations. The monitor program of a single-board microcomputer is generally stored in the ROM. This program interprets the information entered through a keyboard and provides equivalent binary digits to the microprocessor. Programs stored

in the ROM can only be read; they cannot be altered. 2. The Read/Write memory (RIWM) is also known as user memory It is used to store user programs and data. In single-board microcomputers, the monitor program monitors the Hex keys and stores those instructions and data in the R/W memory. The information stored in this memory can be easily read and altered.

I/O (Input/Output): It communicates with the outside world. I/O includes two types of devices: input and output; these I/O devices are also known as peripherals. System Bus: The system bus is a communication path between the microprocessor and peripherals: it is nothing but a group of wires to carry bits.

APPLICATION OF MICROPROCESSORS Microprocessor is a multi-use device which finds applications in almost all the fields. Here is some sample applications given in variety of fields. Electronics:

Digital clocks & Watches Mobile phones Measuring Meters

Mechanical:

Automobiles Lathes All remote machines

Electrical:

Motors Lighting controls Power stations

Medical:

Patient monitoring Most of the Medical equipments Data loggers

Computer:

All computer accessories Laptops & Modems Scanners & Printers

Domestic:

Microwave Ovens Television/CD/DVD players Washing Machines

ARCHITECHTURE or FUNCTIONAL BLOCK DIAGRAM OF 8085 The functional block diagram or architecture of 8085 Microprocessor is very important as it gives the complete details about a Microprocessor. Fig. shows the Block diagram of a Microprocessor.

8085 Bus Structure: Address Bus:

The address bus is a group of 16 lines generally identified as A0 to A15. The address bus is unidirectional: bits flow in one direction-from the MPU to peripheral devices. The MPU uses the address bus to perform the first function: identifying a peripheral or a memory location.

Data Bus:

The data bus is a group of eight lines used for data flow. These lines are bi-directional - data flow in both directions between the MPU and memory and peripheral devices. The MPU uses the data bus to perform the second function: transferring binary information. The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 = 256 numbers). The largest number that can appear on the data bus is 11111111.

Control Bus:

The control bus carries synchronization signals and providing timing signals. The MPU generates specific control signals for every operation it performs. These signals are used to identify a device type with which the MPU wants to communicate.

Registers of 8085:

The 8085 have six general-purpose registers to store 8-bit data during program execution. These registers are identified as B, C, D, E, H, and L. They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit operations.

Accumulator (A):

The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator.

Flags:

The ALU includes five flip-flops that are set or reset according to the result of an operation.

The microprocessor uses the flags for testing the data conditions. They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most commonly used flags are Sign, Zero, and Carry.

The bit position for the flags in flag register is,

1. Sign Flag (S): After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign flag is set. Otherwise it is reset. D7 is reserved for indicating the sign; the remaining is the magnitude of number. If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be viewed as positive number. 2. Zero Flag (z): If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is reset. 3. Auxiliary Carry Flag (AC): If D3 generates any carry when doing any arithmetic and logical operation, this flag is set. Otherwise it is reset. 4. Parity Flag (P): If the result of arithmetic and logical operation contains even number of 1's then this flag will be set and if it is odd number of 1's it will be reset. 5. Carry Flag (CY):

If any arithmetic and logical operation result any carry then carry flag is set otherwise it is reset. Arithmetic and Logic Unit (ALU):

It is used to perform the arithmetic operations like addition, subtraction, multiplication, division, increment and decrement and logical operations like AND, OR and EX-OR.

It receives the data from accumulator and registers. According to the result it set or reset the flags.

Program Counter (PC):

This 16-bit register sequencing the execution of instructions. It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register.

The function of the program counter is to point to the memory address of the next instruction to be executed.

When an op code is being fetched, the program counter is incremented by one to point to the next memory location.

Stack Pointer (Sp):

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack.

The beginning of the stack is defined by loading a 16-bit address in the stack pointer (register).

Temporary Register: It is used to hold the data during the arithmetic and logical operations. Instruction Register: When an instruction is fetched from the memory, it is loaded in the instruction register. Instruction Decoder: It gets the instruction from the instruction register and decodes the instruction. It identifies the instruction to be performed. Serial I/O Control: It has two control signals named SID and SOD for serial data transmission.

Timing and Control unit:

It has three control signals ALE, RD (Active low) and WR (Active low) and three status signals IO/M (Active low), S0 and S1.

ALE is used for provide control signal to synchronize the components of microprocessor and timing for instruction to perform the operation.

RD (Active low) and WR (Active low) are used to indicate whether the operation is reading the data from memory or writing the data into memory respectively.

IO/M (Active low) is used to indicate whether the operation is belongs to the memory or peripherals.

Interrupt Control Unit:

It receives hardware interrupt signals and sends an acknowledgement for receiving the interrupt signal. INSTRUCTION SET OF INTEL 8085

An Instruction is a command given to the computer to perform a specified operation on given data. The instruction set of a microprocessor is the collection of the instructions that the microprocessor is designed to execute. The instructions described here are of Intel 8085. These instructions are of Intel Corporation. They cannot be used by other microprocessor manufactures. The programmer can write a program in assembly language using these instructions. These instructions have been classified into the following groups: 1. Data Transfer Group 2. Arithmetic Group 3. Logical Group 4. Branch Control Group 5. I/O and Machine Control Group Data Transfer Group: Instructions, which are used to transfer data from one register to another register, from memory to register or register to memory, come under this group. Examples are: MOV, MVI, LXI, LDA, STA etc. When an instruction of data transfer group is executed, data is transferred from the source to the destination without altering the contents of the source. For example, when MOV A, B is executed the content of the register B is copied into the register A, and the content of register B remains unaltered. Similarly, when LDA 2500 is executed the content of the memory

location 2500 is loaded into the accumulator. But the content of the memory location 2500 remains unaltered. Arithmetic Group: The instructions of this group perform arithmetic operations such as addition, subtraction; increment or decrement of the content of a register or memory. Examples are: ADD, SUB, INR, DAD etc. Logical Group: The Instructions under this group perform logical operation such as AND, OR, compare, rotate etc. Examples are: ANA, XRA, ORA, CMP, and RAL etc. Branch Control Group: This group includes the instructions for conditional and unconditional jump, subroutine call and return, and restart. Examples are: JMP, JC, JZ, CALL, CZ, RST etc. I/O and Machine Control Group: This group includes the instructions for input/output ports, stack and machine control. Examples are: IN, OUT, PUSH, POP, and HLT etc. 1. Data Transfer Group a. MOV r1, r2 (Move Data; Move the content of the one register to another). [r1] [r2]. b. MOV r, m (Move the content of memory register). r [M] c. MOV M, r. (Move the content of register to memory). M [r] d. MVI r, data. (Move immediate data to register). [r] data.

e. MVI M, data. (Move immediate data to memory). M data. f. LXI rp, data 16. (Load register pair immediate). [rp] data 16 bits, [rh] 8 LSBs of data.

g. LDA addr. (Load Accumulator direct). [A] [addr]. h. STA addr. (Store accumulator direct). [addr] [A]. i.LHLD addr. (Load H-L pair direct). [L] [addr], [H] [addr+1]. j. SHLD addr. (Store H-L pair direct) [addr] [L], [addr+1] [H]. k. LDAX rp. (LOAD accumulator indirect) [A] [[rp]] l. STAX rp. (Store accumulator indirect) [[rp]] [A]. m. XCHG. (Exchange the contents of H-L with D-E pair) [H-L] <--> [D-E]. 2. Arithmetic Group ADD r. (Add register to accumulator) [A] [A] + [r].

i.

ii. iii.

ADD M. (Add memory to accumulator) [A] [A] + [[H-L]]. ADC r. (Add register with carry to accumulator). [A] [A] + [r] + [CS]. ADC M. (Add memory with carry to accumulator) [A] [A] + [[H-L]] [CS]. ADI data (Add immediate data to accumulator) [A] [A] + data. ACI data (Add with carry immediate data to accumulator). [A] [A] + data + [CS].

iv.

v.

vi.

vii.

DAD rp. (Add register paid to H-L pair). [H-L] [H-L] + [rp]. SUB r. (Subtract register from accumulator). [A] [A] [r]. SUB M. (Subtract memory from accumulator). [A] [A] [[H-L]]. SBB r. (Subtract register from accumulator with borrow). [A] [A] [r] [CS].

viii. ix.

x.

xi.

SBB M. (Subtract memory from accumulator with borrow). [A] [A] [[H-L]] [CS].

xii.

SUI data. (Subtract immediate data from accumulator) [A] [A] data. SBI data. (Subtract immediate data from accumulator with borrow). [A] [A] data [CS].

xiii.

xiv. xv. 1.

INR r (Increment register content) [r] [r] +1. INR M. (Increment memory content) [[H-L]] [[H-L]] +

xvi. xvii.

DCR r. (Decrement register content). [r] [r] 1. DCR M. (Decrement memory content) [[H-L]] [[H-L]] 1.

xviii. INX rp. (Increment register pair) [rp] [rp] 1. xix. xx.

DCX rp (Decrement register pair) [rp] [rp] -1. DAA (Decimal adjust accumulator) .

The instruction DAA is used in the program after ADD, ADI, ACI, ADC, etc instructions. After the execution of ADD, ADC, etc instructions the result is in hexadecimal and it is placed in the accumulator. The DAA instruction operates on this result and gives the final result in the decimal system. It uses carry and auxiliary carry for decimal adjustment. 6 is added to 4 LSBs of the content of the accumulator if their value lies in between A and F or the AC flag is set to 1. Similarly, 6 is also added to 4 MSBs of the content of the accumulator if their value lies in between A and F or the CS flag is set to 1. All status flags are affected. When DAA is used data should be in decimal numbers. 3. Logical Group ANA r. (AND register with accumulator) [A] [A] ^ [r]. ANA M. (AND memory with accumulator). [A] [A] ^ [[HL]].
iii.

i. ii.

ANI data. (AND immediate data with accumulator) [A] [A] ^ data. ORA r. (OR register with accumulator) [A] [A] v [r].

iv.

v.

ORA M. (OR memory with accumulator) [A] [A] v [[HL]] ORI data. (OR immediate data with accumulator) [A] [A] v data. XRA r. (EXCLUSIVE OR register with accumulator) [A] [A] v [r]

vi.

vii.

viii.

XRA M. (EXCLUSIVE-OR memory with accumulator) [A] [A] v [[H-L]]

ix.

XRI

data.

(EXCLUSIVE-OR

immediate

data

with

accumulator) [A] [A] v data. x. CMA. (Complement the accumulator) [A] [A] CMC. (Complement the carry status) [CS] [CS] STC. (Set carry status) [CS] 1. CMP r. (Compare register with accumulator) [A] [r] CMP M. (Compare memory with accumulator) [A] [[H-L]] CPI data. (Compare immediate data with accumulator) [A] data. The 2nd byte of the instruction is data, and it is subtracted from the content of the accumulator. The status flags are set according to the result of subtraction. But the result is discarded. The content of the accumulator remains unchanged.
xv.

x. xi. xii. xiii. xiv.

RLC (Rotate accumulator left) [An+1] [An], [A0] [A7], [CS] [A7].

The content of the accumulator is rotated left by one bit. The seventh bit of the accumulator is moved to carry bit as well as to the A7 zero bit of the accumulator. Only CS flag is affected. Accumulator Schematic diagram for RLC RRC. (Rotate accumulator right) [A7] [A0], [CS] [A0], [An] [An+1]. The content of the accumulator is rotated right by one bit. The zero bit of the accumulator is moved to the seventh bit as well as to carry bit. Only CS flag is affected. A0

CS

Carry Status

xvi.

CS

A7

A0

Carry Status

Accumulator Schematic Diagram for RRC RAL. (Rotate accumulator left through carry) [An+1] [An], [CS] [A7], [A0] [CS].

xvii.

xviii. RAR. (Rotate accumulator right through carry) [An]

[An+1], [CS] [A0], [A7] [CS]

4. Branch Group
i.

JMP addr (label). (Unconditional jump: jump to the instruction specified by the address). [PC] Label.

ii.

Conditional Jump addr (label): After the execution of the conditional jump instruction the program jumps to the instruction specified by the address (label) if the specified condition is fulfilled. The program proceeds further in the normal sequence if the specified condition is not fulfilled. If the condition is true and program jumps to the specified label, the execution of a conditional jump takes 3 machine cycles: 10 states. If condition is not true, only 2 machine cycles; 7 states are required for the execution of the instruction.
a. JZ addr (label). (Jump if the result is zero) b. JNZ addr (label) (Jump if the result is not zero) c. JC addr (label). (Jump if there is a carry) d. JNC addr (label). (Jump if there is no carry) e. JP addr (label). (Jump if the result is plus) f. JM addr (label). (Jump if the result is minus) g. JPE addr (label) (Jump if even parity) h. JPO addr (label) (Jump if odd parity)

iii.

CALL addr (label) (Unconditional CALL: call the subroutine identified by the operand) CALL instruction is used to call a subroutine. Before the control is transferred to the subroutine, the address of the next instruction of the main program is saved in the stack. The

content of the stack pointer is decremented by two to indicate the new stack top. Then the program jumps to subroutine starting at address specified by the label.
iv. v.

RET (Return from subroutine) RST n (Restart) Restart is a one-word CALL instruction. The content of the program counter is saved in the stack. The program jumps to the instruction starting at restart location.

5. Stack, I/O and Machine Control Group

i.

IN port-address. (Input to accumulator from I/O port) [A] [Port] OUT port-address (Output from accumulator to I/O port) [Port] [A]

ii.

iii. iv. v.

PUSH rp (Push the content of register pair to stack) PUSH PSW (PUSH Processor Status Word) POP rp (Pop the content of register pair, which was saved, from the stack) POP PSW (Pop Processor Status Word) HLT (Halt) XTHL (Exchange stack-top with H-L) SPHL (Move the contents of H-L pair to stack pointer) EI (Enable Interrupts) DI (Disable Interrupts) SIM (Set Interrupt Masks) RIM (Read Interrupt Masks) NOP (No Operation)

vi. vii. viii. ix. x. xi. xii. xiii. xiv.

ADDRESSING MODE To perform any operation, we have to give the corresponding instructions to the microprocessor. In each instruction, programmer has to specify 3 things: Operation to be performed. Address of source of data. Address of destination of result. Types of Addressing Modes Intel 8085 uses the following addressing modes: Direct Addressing Mode Register Addressing Mode. Register Indirect Addressing Mode Immediate Addressing Mode Implicit Addressing Mode Direct Addressing Mode In this mode, the address of the operand is given in the instruction itself. LDA 2500 H Load the contents of memory location 2500 H in accumulator. LDA is the operation. 2500 H is the address of source.

 Accumulator is the destination.

Register Addressing Mode In this mode, the operand is in general purpose register. MOV A, B Move the contents register B to A. of
MOV is the operation.

B is the source of data.

A is the destination.

Register Indirect Addressing Mode In this mode, the address of operand is specified by a register pair. MOV A, M Move data from memory location specified by H-L pair to accumulator. MOV is the operation. M is the memory location specified by H-L registers pair. A is the destination. Immediate Addressing Mode In this mode, the operand is specified within the instruction itself. MVI A, 05 H Move 05 H in accumulator. MVI is the operation. 05 H is the immediate data (source). A is the destination. Implicit Addressing Mode If address of source of data as well as address of destination of result is fixed, then there is no need to give any operand along with the instruction.

CMA Complement accumulator. CMA is the operation. A is the source. A is the destination.

8085 BUS STRUCTURE Address Bus: Consists of 16 address lines: A0 A15 Address locations: 0000 (hex) FFFF (hex) Can access 64K (= 216) bytes of memory, each byte has 8 bits Can access 64K 8 bits of memory Use memory to map I/O, Same instructions to use for accessing I/O devices and memory Data Bus: Consists of 8 data lines: D0 D7

 Operates in bidirectional mode The data bits are sent from the MPU to I/O & vice versa Data range: 00 (hex) FF (hex) Control Bus:
Consists of various lines carrying the control signals such as read /

write enable, flag bits. INTERNAL ARCHITECTURE AND FUNCTIONING OF INTEL 8086. Feature of 8086 Microprocessor
It is a 16-bit p. 8086 has a 20 bit address bus can access up to 220 memory locations

(1 MB)
It can support up to 64K I/O ports. It provides 14, 16 -bit registers. It has multiplexed address and data bus AD0- AD15 and A16 A19. It requires single phase clock with 33% duty cycle to provide internal

timing.
8086 is designed to operate in two modes, Minimum and Maximum. It can pre fetches up to 6 instruction bytes from memory and queues

them in order to speed up instruction execution.

It requires +5V power supply. A 40 pin dual in line package.

ARCHITECTURE OF INTEL 8086 The term architecture, as used in microprocessor circuits, describes the functional components that make up the MPU and the interaction between them. These include the temporary storage devices known as registers,

which are used to hold data, instructions, a n d s t a t u s i n f o r m a t i o n . There are also devices to perform arithmetic and logical operations. Control devices are used to control the flow of information through the MPU. T h e 8 0 8 6 M P U i s d i v i d e d i n t o t w o independent functional parts known as the execution unit (EU) and the bus interface unit (BIU).

Execution unit (EU)

The EU is where the actual processing of data takes place inside the 8086 MPU. It is here that the arithmetic and logic unit (ALU) is located, along with the registers used to manipulate data and store immediate results. The EU accepts instructions and data that have been fetched by the BIU and then processes the information. Data processed by the EU can be transmitted to the memory or peripheral devices through the BIU

Bus Interface Unit (BIU) T h e B I U i s m a d e u p o f t h e address generation and buscontrol unit, t h e instruction queue, and the instruction pointer. It has the task of making sure that the bus is used to its fullest capacity in order to speedup operations. This function is carried in two ways. First, by fetching the instructions before they are needed by the execution unit and storing them in the instruction queue, the 8086 MPU is able to increase computing speed. Second, by taking care of all bus-control functions, the EU is free to concentrate on processing data and carrying out the instructions. The instruction pointer contains the location or address of the next instruction to be executed. Inside the EU The EU is made up of two parts known as the ALU and the general registers. It is here that instructions are received, decoded, and executed from the instruction queue

portion of BIU. The instructions are taken from the top of the instruction queue on the first-in, first-out, or FIFO, basis. ALU The ALU is the calculator part of the execution unit. It consists of electronic c i r c u i t r y t h a t p e r f o r m s a r i t h m e t i c o p e r a t i o n s o r l o g i c a l o p e r a t i o n s o n t h e b i n a r y represented electrical signals. The control system for the execution unit can also bethought of as part of ALU. It provides a path for the flow of instructions into the ALU,the general registers, and the flag register. Flag Register A flag is a flip-flop which indicates some condition produced by the execution of an instruction or controls certain operations of the EU. The Flag Register is a special register associated with the ALU. A 16-bit

flag register in the EU contains nine active flags.

Flag summary
CF (carry flag) indicates if the instruction generated a carry out the

MSB.
OF (overflow flag) indicates if the instruction generated a signed

result that is out of range.

SF (sign flag) indicates if the instruction generated a negative result.

 PF (parity flag) indicates if the instruction generated a result having

an even number of 1s.

ZF (zero flag) indicates if the instruction generated a zero result DF (direction flag) Controls the direction of the string manipulation

instructions.
IF (interrupt-enable flag) Enables or disables external interrupt TF (trap flag) puts the processor into a single-step mode for program

debugging General Purpose Registers EU has eight general purpose registers labeled AH, AL, BH, BL, CH, CL, DH and DL. These registers are a set of data registers, which are used to hold intermediate results. The H represents the high- order or mostsignificant byte and the L represents the low-order or least-significant byte. Each of these registers may be used separately as 8-bitstorage areas or combined to form one 16-bit (one word) storage area. The acceptable register pairs are AH and AL, BH and BL, CH and CL and DH and DL The AH-AL pair is referred to as the AX register, the BH-BL pair is referred to as the BX register, the CH-CL pair is referred to as the CX register, and the BH-BL pair is referred to as the DX register. The AL register is also called as the Accumulator For 16-bit operations, AX is called the accumulator .The 8086 register set is very similar to those of earlier generation 8080 and 8085microprocessors. Many programs written for the 8080 and 8085 could easily be translated to run on the 8086. Stack Pointer Register

A Stack is a section of memory set aside to store addresses and data while a subprogram is being executed. An entire 64 K bytes segment is set aside as stack in 8086 MPU. The upper 16 bits of the starting address for this segment is kept in the stack segment register. The Stack Pointer (SP) register contain the 16-bit offset from the start of the segment to the memory location where a word was most recently stored on the Stack. The memory location where a word was most recently stored is called the top of Stack. Other pointer and Index Registers In addition to the Stack Pointer register, SP, the EU contains a 16-bit Base pointer (BP)register. It also contains a 16-bit Source index(SI) register and a 16-bitdestinationindex(DI) register. These three registers can be used for temporary storage of data just as the general purpose registers. However, their main use is to hold the 16-bit offset of a data word in one of the segments. That is, the pointer and index registers are usually used to point to or index to an address in memory. When used in this manner, these register are address registers that designate a specific location in the memory that may be frequently used by the program. The addresses contained in these registers can be combined with information from the BIU to physically locate the data in the memory.

The Bus Interface Unit The BIU sends out addresses, fetches instructions from memory, reads data from ports and memory. In other words the BIU handles all transfers of data and addresses on the buses for the execution unit. The BIU can be thought of as three functional blocks; Bus control, Instruction queue, and Address control but control the bus-control unit performs the bus

operations for the MPU. It fetches and transmits instructions, data and control signals between MPU and the other devices of the system. Instruction Queue The instruction queue i s u s e d a s a t e m p o r a r y m e m o r y s t o r a g e a r e a f o r d a t a instructions that are to be executed by the MPU. The BIU, through the bus-control unit, pre fetches instructions and stores them in the instruction queue. This allows the execution u n i t t o p e r f o r m i t s calculations at maximum efficiency. Because the BIU and E U essentially operate independently, the BIU concentrates on loading instructions into the instruction queue. This usually takes more time to do than the calculations performed by the execution unit. In effect, the BIU and the EU work in parallel. The instruction queue is a first in, first-out (FIFO) memory. This means that the first instruction loaded into the instruction queue by the bus control unit will be the first instruction to be used the ALU Address control The address-control unit is used to generate the 20-bit memory address that gives the physical or actual location of the data or instruction in memory. This unit consists of the instruction pointer, the segment registers and the address generator.

Instruction Pointer The Instruction Pointer (IP) is a 16- bit register that is used to point to, or tell the MPU, the instruction to execute next. Therefore, the instruction pointer is used to control the sequence in which the program is executed. Each time the execution unit accepts an instruction, the instruction pointer, is incremented to point to the next instruction in the program.

Segment Registers There are four segment registers. They are the code s e g m e n t ( C S ) , t h e d a t a segment (DS), the stack segment (SS), and the extra segment (ES). These registers areused to define a logical memory space or memory segment that is set aside for a particular function. The CS register points to the current code segment. Instructions are fetched from this segment. The DS register points to the current data segment. Program variables and data are held in this area. The SS register points to the current stack segment, stack operations are performed on locations in the SS segment. The ES register points to the current extra segment, which is also used for data storage. Each of the segment registers can be up to 64 kilo bytes long. Each segment is made up of an uninterrupted section of memory locations. Each segment can be addressed separately using the base address that is contained in its segment register. The base address is the starting address for that segment. Address Generator The address-generator unit is used with the segment registers to generate the 20- bit physical address required to identify all the possible memory addresses. The 20 address lines give a maximum physical memory size of 20 address locations, or 1,048,576 bytes of memory. But all the registers in the MPU are only 16 bits wide. The physical address is obtained by shifting the segment base value four bit positions (one hex decimal position) and adding the offset or logical address of the segment.