REPORT

8x8 BOOTH MULTIPLIER USING TWO PHASES BUNDLED DATA PROTOCOL

RADIX-2
SHRUTI MITTAL[2011H123147 ] VIKAS VARSHNEY[2011H123136] MANU RATHODE[2011H123..]

2012

BITS PILANI

TABLE OF CONTENTS

1. 2. 3. 4. 5.

Introduction Design Details Schemetics Novel Design concepts Results

INTRODUCTION

Introduction
Why consider asynchronous circuits? Most digital circuits designed and fabricated today are synchronous. In essence, they are based on two fundamental assumptions that greatly simplify their design: (1) all signals are binary, (2) all components share a common and discrete notion of time, as dened by a clock distributed throughout the circuit. signal

Asynchronous circuits are fundamentally different; they also assume binary signals, but there is no common and discrete time. Instead the circuits use handshaking between their components in order to perform the necessary synchronization, communication, and sequencing of operations. Expressed in synchronous terms this results in a behavior that is similar to systematic ne-grain clock gating and local clocks that are not in phase and whose period is determined by actual circuit delays registers are only clocked where and when needed. This difference gives asynchronous circuits inherent properties that can be (and have been) exploited to advantage in the areas listed below 1.Low power consumption 2.High operating speed 3. robustness towards variation of supply noise 4.No clock distribution problem and clock skew problem. There are lot more advantages which makes it more promising technology in near future. Recently only synopsis is working on this area. Many companies dont prefer to work in this area due to huge design efforts and cost. As it requires nearly three years to make a research done in this area and we need to take care of timing constraint as any input can appear anytime.So we need to take care of its compatibility to outside world. So to take one step towards this asynchronous field and to have a feel of asynchronous design we have designed 8X8 Booth multiplier using 2 phase bundled data protocol. As there are many other protocol we can use like 4 phase bundled data or 4 phase dual rail but it depends on complexity of the circuit more complex circuit can give more efficiency in speed but at the same time it can cause tradeoff with power so we need to take care of power and delay product.

BOOTH MULTIPLIER
In the booth multiplier we used radix-2 format.In the radix two format we make pairs of bits of multiplicand starting from left side while starting this we add zero to left side. For eg. Take multiplicand as 10010111 so now this will be converted to 100101110. Now we will start from left side in pairs of two.. so pairs will be (10),(11),(11),(01),(10),(01),(00),(10) so there will be 8 pairs. Now according to these pairs we will generate magnitude and sign bits and follow this rule. so according to the rule if pair comes 10 then we will take twos compliment of the multiplier if pair comes (11 or 00) then we will take the output as 00000000.if pair comes (01) we will simply put the output as same as multiplier bits.As there are 8 pairs so it means we get 8 rows of result we can not directly add the rows so we need convert the 8 rows into less number of rows. For this we used vellace tree adder and used the 3:2,4:2 compressors ,fulladders,half adders.As we need to use the circuit into piplines so we divided the circuit into different stages and put the latches between them. As the circuit is 2-phase bundled data we used dual edge trigger flip flop.All the circuits and its screen shots are given below. Circuits in steps are as follows 1. Partial product stage 2. Compressors and adders stage 3. Pipeline stage Design details: Partial product stage This stage contains two mux which generates the partial product according to the sign and magnitude used. Compressor and adder stage: 4:2 compressor. It uses two full adders 3:2 compressor: It uses one full adder and one half adder Pipeline stage: In this stage we have used Dual edge triggered flipflops as we have used 2 phase bundled data protocol

Snapshots and Results of Circuits

3:2 compressor

4:2 compressor:

Dual Edge Trigger Flip Flop:

Full Adder:

Half Adder

Magnitude Generator

Muller C:

Sign Generator

Partial Product Generator

Partial Product Generator Using Mux-

Stage 1-pipeline

Stage 2-pipeline

Stage-3-pipeline

Stage 4 -pipeline

Multiplier Circuits:

Multiplier Output

2x1 mux: