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Therefore, VGS, the gate-source voltage can be changed to control the amount of drain current ID flowing in the channel.
8.2.2 Breakdown
Breakdown occurs at point C when ID increases very rapidly. Breakdown can damage the transistor. JFETs should be operated below breakdown in the active region (between point B and C).
o = when = 0 The mathematical relation between the drain current ID and VGS can be given approximately as
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1 -
The above equation can determine ID for any given value of VGS if IDSS and VGS(off) are known. IDSS and VGS(off) are given in the datasheets. NOTE: REFER EXAMPLE 8-3 PAGE 377
gm is greater at the top (near = 0) of the curve as compared to the bottom (near shown in Figure 8. The datasheet normally gives values of gm at = 0 (gm0). Given gm0, we can calculate gm at any point on the curve using the following formula:
) as
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= 0 1 -
If gm0 is not available, we can use the following formula to calculate it: 0 = 2
8.3.1 Self-Bias
Self-bias is the most common type of bias circuit for JFET. Figure 9 shows the self-bias circuit for n-channel (Figure 9a) and p-channel (Figure 9b) JFETs. The gate terminal being grounded through RG results in = 0.
This setup achieves the reverse bias condition of the gate required for proper biasing of JFET. NOTE: REFER EXAMPLE 8-6 PAGE 382
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It is good to bias a JFET near the midpoint of the transfer curve. At the midpoint = 2 = 3.4 = 2 Select a value of RD to get the required VD. Choose RG large enough (mega ohm range). NOTE: REFER EXAMPLE 8-9 PAGE 384
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two points establishes the load line. o Extending the load line to intersect the transfer curve gives us the Q-point. o Note the corresponding values of ID and VGS at the Q-point.
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Figure 13 Variation in transfer curve and Q-point of self-biased and voltage-divider biased JFET of the same type
The change in the drain current value for self-bias is more then the change for the same in voltagedivider. The reason for this is that the slope of the load line for voltage-divider is much gradual then the slope of the load line for self-biased and thus the change in y-axis is small.
As can be seen from the transfer characteristic curve of 2 different JFET, the drain current remains constant thus providing highly stable Q-point.
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Figure 16 Load line intersect the curves inside the Ohmic region
To bias the JFET in the Ohmic region, the load line must intersect the curves inside the Ohmic region as shown in Figure 16. This is done by setting the DC saturation current ID(sat) much less than IDSS. Figure 16 shows 3 Q-points in the Ohmic region. As you move along the load line or change the Q-point, the resistance RDS changes as the slope at each Q-point are different. If the Q-point is moved from = 0 to = 2, the slope at each point is less then the previous one. This means less ID and more VDS which results in increase in RDS. NOTE: REFER EXAMPLE 8-14 PAGE 394
Instead the channel is induced by a positive threshold voltage at the gate that pulls the electrons to make the channel.
This structure makes it possible to have more conduction by pulling more electrons in the channel. Figure 18 shows the schematic symbols of n-channel and p-channel E-MOSFETs.
It operates in depletion mode when < 0 and operates in enhancement mode when > 0. Applying negative VGS at the gate terminal of a D-MOSFET repels the electrons in the n-channel and replaces it by hole. This depletes the channel of any electrons and when = , the channel is totally depleted and drain current ID becomes zero. Applying positive VGS at the gate terminal of a D-MOSFET attracts more electrons in the n-channel.
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This increases or enhances the channel conductivity. Figure 20 shows the schematic symbols of n-channel and pchannel D-MOSFET.
The equation for the drain current in E-MOSFET differs from JFET and is given by = = 2 Where values of ID(on) is specified in the datasheets at a given VGS. NOTE: REFER EXAMPLE 8-16 PAGE 402
2
The curve shows that with positive VGS (n-channel) or negative VGS (p-channel) the channel conduction increases allowing more current through the drain as than IDSS. The same equation of ID as in JFET also applies to D-MOSFET. NOTE: REFER EXAMPLE 8-17 PAGE 403
n-
NOTE: REFER EXAMPLE 8-18 & 8-19 PAGE 405 & 406
1 2
= = = = = = +
Self-Bias
Voltage-Divider Bias
Ohmic Region
= 1 = = =
E-MOSFET Bias
D-MOSFET Bias
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