I. Metal-Semiconductor Contacts: Schottky Barrier Height

Subject-NM6603: Modern Semiconductor Devices
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D. Y. Tang Page 1 3/31/08
I. Metal-semiconductor contacts

Metals are materials in which the highest occupied band is half full of electrons so that
the Fermi level lies in the middle of an allowed band. As a result, the electron density at
the Fermi level is very high and there are available unoccupied states above the Fermi
level, which allow a high density of electrons to participate in carrying current. Thus the
resistivity of metals is very low. The low resistivity of metals is due to a very high
electron concentration.

Metal-semiconductor junctions have long been used as linearly conductive (ohmic)
metallic connections to devices and in integrated circuits. Depending on the type of
semiconductor, such junctions may pass current easily into and out of a junction (labeled
ohmic contacts) or they may be rectifying in allowing current flow in only one direction.
The rectifying property has made possible the rectifier diode, known as the Schottky
(barrier) diode.

The Schottky diode has characteristics that are essentially similar to those of the p-n
junction diode except that for many applications it has a much faster response.

Fig. 1: A schematic of a Schottky barrier junction

Schottky barrier height

To understand the properties of the Schottky barrier junction, we examine the band
profiles of a metal and a semiconductor. The Fermi level E
Fm
in the metal lies in the band
as shown. Also shown is the work function e
m
, which is the energy required to take an
electron out to the free vacuum state. In the semiconductor, we show the vacuum level
along with the position of the Fermi level E
Fs
in the semiconductor, the electron affinity,
and the work function.

We assume that
m
>
s
that the Fermi level in the metal is at a lower position than the
level in the semiconductor. When the junction between the two systems is formed, the
Fermi levels should line up at the junction and remain flat in the absence of any current
as shown in Fig. 3. At the junction the vacuum energy levels of the metal side and the
semiconductor side must be the same. To ensure the continuity of the vacuum level and
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keep the Fermi level flat, the Fermi level must move deeper into the bandgap of the
semiconductor at the interface region. This involves electrons moving out from the
semiconductor side to the metal side. Note that since the metal side has an enormous
electron density, the metal Fermi level or the bandgap profile does not change when a
small fraction of electrons are added or taken out. As the electron move to the metal side,
they leave behind positively charged fixed centers, and a dipole region is produced. The
electric field opposes the electron flow and at equilibrium the band bending is such that
the Fermi level is flat.

Fig. 2: Energy levels in the metal and the semiconductor with respect to the vacuum level (before contact).

Fig. 3: The junction potential is produced when the metal and semiconductor are brought together. Due to
the built-in potential at the junction, a depletion region of width W is created.

In the ideal Schottky barrier, the height of the barrier at the semiconductor-metal
junction, defined as the difference between the semiconductor conduction band at the
junction and the metal Fermi level, is

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( )
s m Fs c s m b
e e E E e e e = + =

The electrons coming from the semiconductor into the metal face a barrier denoted by
eV
bi
as shown in Fig. 3. The potential eV
bi
is called the built-in potential of the junction
and is given by

s m bi
e e eV =

Fig. 4: A schematic of the ideal p-type Schottky barrier formation. (a) Energy levels in the metal and the
semiconductor before contact. (b) The junction potential and the depletion width.

In the fig 4 we show the case of a metal-p-type semiconductor junction where we choose
a metal so that e
m
< e
s
. In this case, at equilibrium the electrons are injected from the
metal to the semiconductor, causing a negative charge on the semiconductor side. The
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band is bent once again and a barrier is created for hole transport. The height of the
barrier seen by the holes is

m s bi
e e eV =

The schottky barrier height for n- or p-type semiconductors depends on the metal and the
semiconductor properties.

The height of the potential barrier can be altered by applying an external bias, and the
junction can be used for rectification.

Capacitance voltage characteristics

Once the Schottky barrier height is known, the electric field profile, depletion width,
depletion capacitance, etc., can be evaluated. The problem is identical to that of the
abrupt p
+
n diode since there is no depletion on the metal side. One again makes the
depletion approximation: 1) there is no mobile charge in the depletion region. 2) the
semiconductor is neutral outside the depletion region. Then, in the presence of an
external potential V, the solution of the Poisson equation gives

( )
( )
( )
2
1
2

=

=
d
bi s
s
d
eN
V V
W
x W eN
x E
(1)

Where E is the electric field and W is the depletion width in the semiconductor. Note that
there is no depletion on the metal side because of the high electron density there. The
potential V is the applied potential, which is positive for forward bias.

The electric field has the form

( )
|
\
|
=
W
x
E x E
m
1 (2)

where
( )
2
1
2
|
\
|

= =

V V eN W eN
E
bi d d
m
(3)

The depletion region charge is given from the depletion width as

( ) [ ]2
1
2 V V N e W eN Q
bi d d d
= = (4)
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The corresponding capacitance for area A of the device is

( ) W
A
V V
N e
A
dV
dQ
A C
s
bi
d s

=
= =
2
1
2
(5)

We have then

( )
d s
bi
N e A
V V
C
2 2
2 1
= (6)

Thus the plot of 1/C
2
and V provides the information on both the built-in potential and
the doping density.

Current flow in a Schottky barrier

The current flow across a Schottky barrier can involve a number of different mechanisms.
The most important and most desirable mechanism is that of thermionic emission in
which electrons with energy greater than the barrier height e(V
bi
-V) can overcome the
barrier and pass across the junction. Note that as the bias changes, the barrier to be
overcome by electrons changes and the electron current injected is thus altered. In
addition to the thermionic emission, electrons can also tunnel through the barrier to
generate current. This can be important if a semiconductor is heavily doped so that the
depletion width is small. Other current mechanisms that are less important in high quality
Schottky barriers may involve minority carrier injection, trap related recombination, etc.

Fig. 5: The forward bias allows electrons to flow from the semiconductor to the metal side,
increasing the current.

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Fig. 6: The reverse bias suppresses the electron flow from the semiconductor side while the flow from the metal side
is unaffected.

Thermionic emission current

If we assume that the tunneling current is negligible, the electrons that across the metal-
semiconductor junction must have energies greater than the barrier height at the junction. As an
electron enters the semiconductor through a contact and travels towards the junction, its path in
the neutral junction is simply determined by the drift-diffusion processes. At the junction it must
pass over the barrier and only those electrons that have energies larger than the barrier will pass.
The current is thus limited by the injection barrier rather than the neutral region drift-diffusion in
high quality semiconductors.

We assume that the electrons in the semiconductor region are distributed according to Boltzmann
statistics. Thus the fraction of electrons with energy greater than the barrier of (V
bi
-V) is

( )

=
T k
V V
e n n
B
bi
b
exp
0
(7)

where n
0
is the electron density in the neutral region. The density n
0
is given in terms of the
effective density of electrons N
c
as

( )

=
T k
E E
N n
B
Fs c
c
exp
0
(8)

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Thus (note that the metal side barrier
Fs c bi b
E E eV e + = ),

( )

=
T k
eV e
N n
B
b
c b
exp (9)

If the electron to be considered to be moving randomly, the average flux of electrons impinging
on the metal-semiconductor barrier is <v>n
b
/4. where ,<v> is the average speed of the electrons.
The corresponding current is then

( )
> <
=
T k
V e
N
v eA
I
B
b
c sm
exp
4
(10)

When the applied bias V is zero, the current flow from the metal into the semiconductor I
ms
must
balance the current flow from the semiconductor to the metal. Thus

( )

> <
= = =
T k
e
N
v eA
V I I
B
b
c sm ms
exp
4
0 (11)

When a potential V is applied, the barrier see by the electrons coming from the metal side is
unchanged and I
ms
remains a constant.

Thus the net current at an applied bias V is

|
|
\
|
= = 1 exp
T k
eV
I I I I
B
s ms sm
(12)

For a Maxwell-Boltzmann distribution of electron, the average velocity is related to the
temperature by the relation

2
1
*
8
|
|
\
|
>= <
e
B
m
T k
v
(13)

Substituting for the effective conduction band density N
c
, we get for I
s
=I
sm
(V=0)

)
`
|
|
\
|
|
|
\
|
=
T k
e
T
ek m
A I
B
b B e
s
exp
2
2
3 2
2 *
h
(14)

The quantity in the parentheses is called the Richardson constant and is denoted by R*.

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It is important to note that the electrons in the semiconductor side see a variable potential barrier
as the applied bias changes, while the current from the metal side remains essentially unchanged.

Fig. 7: The rectifying characteristics of the Schottky diode

Ohmic contacts

Ohmic contacts serve to provide a resistance free pathway to inject charge into or out of a
semiconductor. In the fabrication of discrete devices and in the interconnections of integrated
circuits, it is necessary to establish ohmic metallic contacts to the devices, to the connections
between the semiconductor region and its external terminal, and to interconnect elements in an
integrated circuit. Such contacts should not in any way interfere with the operation of the device
or a circuit, and therefore should exhibit negligible resistance to the flow of current into and out
of the device. The contact should consequently support a negligible voltage drop compared to the
drop across the active region of the device. Such contacts are known as ohmic contacts.

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Fig. 8: Current-voltage characteristics of a Schottky barrier diode and of an ohmic contact.

There are two possibilities for producing ohmic contacts. In the previous section, to produce a
Schottky barrier on an n-type semiconductor, we needed a metal with a work function larger than
that of the semiconductor. Thus, in principle, if we use a metal with a work function smaller than
the semiconductor, one should have no built-in barrier. However, this approach is not used in
practice, because as we noted in the previous section, the Fermi level at the surface of real
semiconductors is pinned because of the high interface density in the gap.

A more commonly used method for establishing an ohmic contact between a metal and a
semiconductor is to make the contact favorable to the tunneling of electrons in both directions.
This can be done by heavily doping a material so that carriers are injected by tunneling through a
very thin barrier. The depletion width on the semiconductor side is

2
1
2
=
d
bi
eN
V
W
(15)

Now if near the interface region the semiconductor is heavily doped, the depletion width could
be extremely narrow. In fact, it can be made so narrow that even though there is a potential
barrier, the electrons can tunnel through the barrier with ease as shown in Fig. 9. The quality of
an ohmic contact is usually defined through resistance R of the contact over a certain area A. The
normalized resistance is called the specific contact resistance r
c
.

Fig. 9: Band diagram of metal-n
+
-n contact. The heavy doping reduces the depletion width to such an extent that the
electrons can tunnel through the spiked barrier easily in either direction

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D. Y. Tang Page 10 3/31/08
For tunneling to take place, it is necessary for the conduction band of one material to be located,
energy-wise, opposite empty states in the conduction band of the other material. At thermal
equilibrium, the Fermi levels of the metal and semiconductor are aligned. With reverse bias
applied, the Fermi level of the semiconductor is depressed so that some electrons in the
conduction band of the metal are at the same energy level at, and across, the tunnel, from empty
states in the conduction band of the semiconductor, as shown in Fig. 10(a). This results in the
tunneling of these electrons and easy current flow from the semiconductor to the metal. When a
forward bias is applied, making the metal positive with respect to the semiconductor, electrons in
the conduction band of the semiconductor are opposite empty states of the conduction band of
the metal, which makes it possible for electrons to tunnel across. The bending of the energy
bands when forward bias is applied is shown in Fig. 10(b).

Fig. 10: Tunneling at a metal semiconductor junction with (a) reverse bias and (b) forward bias.

II. MOS structure

The field effect transistor (FET) is the most important electronic device in modern solid-state
technology. The tremendous versatility of this device combined with high yield and reliability
have allowed this device to become a workhorse for virtually every application.
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D. Y. Tang Page 11 3/31/08

MOS capacitor

A tremendous advantage that Si technology has over other semiconductor is the presence of a
high quality oxide SiO
2
, which can be formed on Si. It is a high degree of perfection of this
interface that has allowed Si to overtake Ge, which was the initial material of choice for
transistor. Also, the Si-SiO
2
interface perfection has been the reason why bipolar devices have
been replaced by field effect devices in many applications.

A MOS capacitor has the configuration as shown in Fig. 11. An oxide layer is grown on top of a
p-type semiconductor and a metal is placed on the oxide. In general, the oxide could be any large
bandgap insulator. The main purpose of the oxide layer is to provide isolation between the metal
and the semiconductor so that there is essentially no current flow between the top metal contact
and the metal contact at the bottom of the semiconductor.

Fig. 11: A schematic of an MOS capacitor

Let us first consider the ideal structure where there are no states in the bandgap regions at the
interface between the oxide and the semiconductor. In reality, because of the mismatch
between the oxide lattice and the Si lattice, there are some defect states at the interface which
will be discussed later. In Fig. 12 we show the important energy levels associated with the metal,
the oxide, and the semiconductor. When the capacitor is formed, the Fermi levels align
themselves so that there is no gradient. The conduction band of the oxide is at a higher position
than the conduction band of the semiconductor. In general, if the work functions in the metal and
the semiconductors are different, the band alignments are as shown in Fig. 13. There is a fairly
high potential barrier between the metal and the semiconductor. At zero applied bias, the band
bending at the semiconductor is determined by the difference in the work functions of the metal
and the semiconductor.

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D. Y. Tang Page 12 3/31/08

Fig. 12: Energy level diagrams for aluminum (metal), silicon dioxide (oxide), and p-silicon (semiconductor).

Fig. 13: Energy level diagram after contact

If one applies an external bias, the band bending can be removed (thus reaching the flat band
condition) by applying a compensating bias V
FB
given by

s m
FS c
s m FB
q
E E
V =
= (16)

where
m
and
s
are the metal and semiconductor work functions,
s
is the semiconductor
electron affinity, E
c
the semiconductor conduction band edge, and E
FS
the Fermi level.

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D. Y. Tang Page 13 3/31/08
The ideal MOS capacitor

The energy band diagram of an ideal p-type semiconductor MOS capacitor at V = 0 is shown in
Fig. 14. An ideal MOS capacitor is defined as follows. (1) At zero applied bias, the energy
difference between the metal work function q
m
and the semiconductor work function q
s
is
zero. In other words, the energy band is flat (flat-band condition) when there is no applied
voltage. (2) The only charges that exist in the diode under any biasing conditions are those in the
semiconductor and those with equal but opposite sign on the metal surface adjacent to the oxide.
(3) There is no carrier transport through the oxide under dc-biasing conditions, or the resistivity
of the oxide is infinite. The ideal MOS capacitor theory will serve as a foundation for
understanding practical MOS devices.

Fig. 14: Energy band diagram of an ideal MOS diode at V=0.

When an ideal MOS capacitor is biased with positive or negative voltages, three cases may exist
at the semiconductor surface. When a negative voltage (V<0) is applied to the metal plate, the
bands near the semiconductor surface are bent upward, as shown in Fig. 15. For an ideal MOS
capacitor, no current flows in the device regardless of the value of the applied voltage; thus, the
Fermi level in the semiconductor will remain constant.

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D. Y. Tang Page 14 3/31/08
Fig. 15: Energy band diagram and charge distribution of an ideal MOS diode in accumulation case.

Previously, we determined that the carrier density in the semiconductor depends exponentially
on the energy difference E
i
- E
F
, that is,

=
kT
E E
n p
F i
i p
exp (17)

The upward bending of the energy bands at the semiconductor surface causes an increase in the
energy difference E
i
- E
F
there, which in turn gives rise to an enhanced concentration, an
accumulation of holes near the oxide semiconductor interface. This is called the hole
accumulation case. The corresponding charge distribution is shown on the right side of Fig. 15.

When a small positive voltage (V > 0) is applied to an ideal MOS diode, the energy bands bend
downward, and the majority carriers (holes) are depleted (Fig. 16). This is called the depletion
case. The space charge per unit area Q
sc
in the semiconductor is given by the charge within the
depletion region:

Q
sc
= - qN
A
W (18)

where W is the width of the surface depletion region.

Fig. 16: Energy band diagram and charge distribution of an ideal MOS diode in depletion case.

When a larger positive voltage is applied, the bands bend downward even more so that the
intrinsic level E
i
at the surface crosses over the Fermi level as shown in Fig. 17.

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D. Y. Tang Page 15 3/31/08

Fig. 17: Energy band diagram and charge distribution of an ideal MOS diode in inversion case.

The electron concentration depends exponentially on the energy difference E
F
E
i
and is given
by

=
kT
E E
n n
i F
i p
exp (19)

In the situation shown in Fig. 17, (E
F
- E
i
) > 0. Therefore, the electron concentration n
P
at the
surface is larger than n
i
, and the hole concentration given by Eq. 17 becomes less than n
i
. The
number of electrons (minority carriers) at the surface is greater than the number of holes
(majority carriers); the surface is thus inverted. This is called the inversion case. As the bands are
bent further, eventually the conduction band edge comes close to the Fermi level. At this point
the electron concentration near the surface increases very rapidly. After this point most of the
additional negative charges in the semiconductor consist of the charge Q, (Fig. 17) due to the
electrons in a very narrow n-type inversion layer 0 < x < x
i
, where x
i
is the width of the inversion
region. Typically, the value of x
i
ranges from 10 to 100 and is always much smaller than the
surface depletion layer width.

Once an inversion layer is formed, the surface depletion layer width reaches a maximum. This is
because when the bands are bent downward far enough strong inversion to occur, even a very
small increase in band bending (corresponding to a very small increase in depletion layer width)
results in a increase in the charge Q, in the inversion layer. Thus, under a strong inversion
condition the charge per unit area in the semiconductor is given by

sc n s
Q Q Q + = (20)

and

m A sc
W qN Q = (21)

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D. Y. Tang Page 16 3/31/08
Where W
m
is the maximum width of the surface depletion region.

The Surface Depletion Region

Fig. 18: Energy band diagram at the surface of a p-type semiconductor

Figure 18 shows a more detailed band diagram at the surface of a p-type semiconductor. The
electrostatic potential defined as zero in the bulk of the semiconductor. At the semiconductor
surface =
s
, is called the surface potential. We can express electron and hole concentrations
as a function of :

( )
( )

=
kT
q
n p
kT
q
n n
B
i p
B
i p

exp
exp
(22)

where is positive when the band is bent downward (as shown in Fig. 18). At the surface the
densities are

( )
( )

=
kT
q
n p
kT
q
n n
s B
i s
B s
i s

exp
exp
(23)

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D. Y. Tang Page 17 3/31/08

From this discussion and with the help of Eq. 23, the following regions of surface potential can
be distinguished:

s
< 0 Accumulation of holes (bands bend upward)
s
= 0 Flat-band condition
B
>
s
> 0 Depletion of holes (bands bend downward)
s
=
B
Midgap with n
s
= n
P
= n
i
(intrinsic concentration)
s
>
B
Inversion (bands bend downward as shown in Fig. 18).

The potential as a function of distance can be obtained by using the one dimensional Poisson
equation:

( )
s
s
x
dx
d

=
2
2
(24)

where
s
(x) is the total space charge density. We shall use the depletion approximation
mentioned above. When the semiconductor is depleted and the charge within the semiconductor
is given by
s
= - qN
A
, integration of Poisson's equation gives the electrostatic potential
distribution in the surface depletion region:

2
1
=
W
x
s
(25)

The surface potential
s
is

s
A
s
W qN
2
2
= (26)

Note that the potential distribution is identical to that for a one-sided n
+
-p junction.

The surface is inverted whenever
s
is larger than
B
. However, we need a criterion for the onset
of strong inversion after which the charges in the inversion layer become significant. A simple
criterion is that the electron concentration at surface is equal to the substrate impurity
concentration

n
s
= N
A
(27)

Since
=
kT
q
n N
B
i A
exp , from Eq. 23 and 27 we obtain

( )

=
i
A
B s
n
N
q
kT
inv ln
2
2 (28)
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D. Y. Tang Page 18 3/31/08

Equation 28 states that a potential
B
is required to bend the bands down to intrinsic condition at
the surface (E
i
= E
F
), and bands must then be bent downward by another q
B
at the surface to
obtain the condition of strong inversion.
As we discussed previously, the surface depletion layer width reaches a maximum when the
surface is strongly inverted. Accordingly, the maximum width of the surface depletion region is
given by Eq. 21 in which s equals
s
(inv), or

( ) ( ) ( )
A
i A s
A
B s
A
s s
m
N q
n N kT
qN qN
inv
W
2
/ ln 4 2 2 2
= = (29)

and
( )
B A s m A sc
N q W qN Q 2 2 = (30)

Therefore, starting from the flat band position, there are three important regimes of biasing in the
MOS capacitor:

i) Hole Accumulation: If a negative effective bias is applied between the metal and the
semiconductor, a negative charge is deposited on the metal and an equal positive charge is
accumulated at the semiconductor-oxide interface. This occurs due to the band bending as shown
in Fig. 15 where the valence bands are bent to come closer to the Fermi level, causing an
accumulation of holes at the interface. The difference between the Fermi level in the metal and
the semiconductor is the applied bias.

ii) Depletion: If a positive effective bias is applied to the metal with respect to the
semiconductor, the bands bend as shown in Fig. 16. The Fermi level in the metal is lowered by
an amount eV with respect to the semiconductor, causing the valence band to move away from
the semiconductor Fermi level near the interface. As a result the hole density near the interface
falls below the bulk value in the P-type semiconductor.

iii) Inversion: If the positive effective bias on the metal side is increased further, eventually the
conduction band at the oxide-semiconductor region comes close to the Fermi level in the
semiconductor. As a result, the electron density at the interface starts to increase. If the positive
effective bias is increased until E
c
comes quite close to the semiconductor Fermi level near the
interface, the electron density becomes very high and the semiconductor near the interface has
electrical properties of an n- type semiconductor. This is shown in Fig. 17. However, it is
important to note that the n-type property is not produced by doping the semiconductor but is
produced by "inverting" the bands by an external bias. This approach of producing n-type
behavior without doping has many advantages over the usual doping. In particular, one does not
have scattering due to dopants, and the carrier freeze out effect can be suppressed. A very high
carrier density can be induced if the insulator has a large bandgap and has a good quality
interface with the semiconductor.

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D. Y. Tang Page 19 3/31/08

Capacitance-voltage characteristics of the MOS structure

An important consideration of the MOS structure is the capacitance as a function of applied
voltage.

In the C-V measurements, a dc bias is applied to the gate, and a small ac signal (~5-10mV) is
applied to obtain the capacitance at the bias applied. The capacitance of the MOS structure is the
series combination of the oxide capacitance C
ox
and the semiconductor capacitance C
s
as shown
in Fig. 19. The semiconductor capacitance is

s
s
s
dV
dQ
C = (31)
and the total capacitance is

s ox
s ox
mos
C C
C C
C
+
= (32)

It is to note that the capacitance values discussed are capacitance per unit area.

Fig. 19: A simple equivalent circuit of the MOS capacitor. The circuit is valid at low frequencies since the resistance
of the device is ignored.

The three important regimes of accumulation, depletion and inversion are reflected in the C-V
characteristics. In the accumulation region (negative V
G
), the holes accumulate at the surface and
C
s
is much larger than C
ox
. This is because a small change in bias causes a large change in Q
s
in
the accumulation regime. The MOS capacitance is then

ox
ox
ox mos
d
C C
= (33)
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D. Y. Tang Page 20 3/31/08

As the gate voltage becomes positive and the channel is depleted of holes, the depletion
capacitance becomes important. The depletion capacitance is simply given by
s
/W, and the total
capacitance becomes

s
ox
ox
ox
s
ox
ox
mos
W
d
C
C
C
C
+
=
+
=
1
(34)

As the device get more and more depleted, the value of C
mos
decreases as shown in Fig. 20. At
the inversion condition, the depletion width reaches its maximum value W
max
. At this point there
is essentially no free carrier density. The minimum capacitance is

( )
s
ox
ox
ox
s
ox
ox
mos
W
d
C
C
C
C
max
1
min
+
=
+
=
(35)

If the bias is further increased, the free electrons start to collect in the inversion regime and the
depletion width remains unchanged with bias. The capacitance of the semiconductor again
increases since a small change in V
s
causes a large change in Q
s
. The capacitance of the MOS
device thus returns towards the value of C
ox
.

( )
ox
x
ox mos
d
C inv C
= = (36)

The capacitance voltage curve for a typical MOS capacitor is shown in Fig. 20. Also shown are
the important regimes and capacitance points discussed above.

In the above discussion we have assumed that the electrons needed in the inversion regime can
be supplied instantaneously as the gate bias is charged. This is not the case in the p-type
semiconductor. The excess electrons needed are introduced into the channel by e-h generation,
by thermal generation processes, or by diffusion of the minority carriers from the p-type
substrate. Since the generation process takes a finite time, the inversion sheet charge can follow
the voltage only if the voltage variations are slow. If the variations are fast, the capacitance due
to the free electrons has no contribution and the capacitance is dominated by the depletion
capacitance. Thus, under the high frequency measurements, the capacitance does not show a
turnaround and remains at the value C
mos
(min). The capacitance in the inversion regime starts to
decrease even at frequencies of 10Hz and at 10
4
Hz it reaches the low value of C
mos
(min).

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D. Y. Tang Page 21 3/31/08

Fig. 20: The dependence of capacitance of an MOS capacitor on voltage. Also shown are the various important
regions in the capacitance-voltage relations.

Interface Traps and Oxide Charge

In addition to the work function difference, the equilibrium MOS diode is affected by charges in
the oxide and traps at the Si-SiO2 interface. The basic classifications of these traps and charges
are shown in Figure B1. They are interface-trapped charge, fixed-oxide charge, oxide-trapped
charge and mobile ionic charge.

Interface-trapped charges Q
j
, are due to Si-SiO2 interface properties and dependent on the
chemical composition of this interface. The traps are located at the Si-Sio2 interface with energy
states in the silicon forbidden bandgap. The interface trap density (i.e., number of interface traps
per unit area) is orientation dependent. In < 100> orientation, the interface trap density is about
an order of magnitude smaller than that in < 111 >. Present-day MOS diodes with thermally
grown silicon dioxide on silicon have most of the interface trapped charge neutralized by low
temperature (450 C) hydrogen annealing. The value of Qj, for <100>-oriented silicon can be as
low as 10
10
cm
-2
,which amounts to about one interface-trapped charge per 10
5
surface atoms. For
< 111>-oriented silicon, Qj, is about 10
11
cm
-2
.

The fixed-oxide charge Qf is located within approximately 30 A of the Si-SiO2 interface. This
charge is fixed and cannot be charged or discharged over a wide variation of surface potential
s.

Generally, Q
f
is positive and depends on oxidation and annealing conditions and on silicon
orientation. It has be suggested that when the oxidation is stopped, some ionic silicon is left near
the interface. These ions, along with uncompleted silicon bonds (e.g., Si-Si or Si-O bonds) at the
surface, may result in the positive fixed-oxide charge Qf. Qf can be regarded as a charge sheet
located at the Si-Si02 interface. Typical fixed-oxide charge densities for carefully treated Si-Si02
systems are about 10
10
cm
- 2
for a < 100> surface and about 5 x 10
10
cm
-2
for a <111> surface.
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D. Y. Tang Page 22 3/31/08
Because of the lower values of Qj, and Qf, the < 100> orientation is preferred for silicon
MOSFETs.

The oxide-trapped charges Q
ot
are associated with defects in silicon dioxide. These charges can
be created, for example, by X-ray radiation or high energy electron bombardment. The traps are
distributed inside the oxide layer. Most of the process-related Q
ot
can be removed by low-
temperature annealing.

The mobile ionic charges Q
m
, such as sodium or other alkali ions are mobile within the oxide
under high-temperature and high-voltage operations. Trace contamination by alkali metal ions
may cause reliability problems in semiconductor devices operated under high bias-temperature
conditions. Under high bias-temperature Conditions mobile ionic charges move back and forth
through the oxide layer, depending on biasing conditions, and thus give rise to shifts of the C-V
curve along the voltage axis. Special attention must therefore be paid to the elimination of
mobile ions in device fabrication. The foregoing charges are the effective net charges per unit
area (in C/cm
2
).

Fig. B1: Terminology for charges associated with thermally oxidized silicon

Effects of oxide charges

In the above discussions we have assumed that there are no fixed charges in the oxide region. In
reality there may be two kinds of charges associated with the oxide. The first are charges in the
oxide near the Si/SiO
2
interface and are due to impurity ions which may be incorporated during
the oxide fabrication process. In addition, there may be interface charges, which are due to the
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D. Y. Tang Page 23 3/31/08
non-ideal nature of the Si-SiO
2
interface. The fixed charge density is not dependent upon the gate
bias, but the interface charge depends upon the applied bias. The two thus have different effects
on the C-V characteristics.

We shall evaluate the influence of these charges on the flat-band voltage. Consider a positive
sheet charge per unit area, Q
o
, within the oxide as shown in Fig. B2. This positive sheet charge
will induce negative charges partly in the metal and partly in the semiconductor. The resulting
field distribution, obtained from integrating Poisson's equation once, is shown in the lower part
of Fig. B2a where we have assumed that there is no work function difference, or q
ms
=0.

Fig. B2: Effects of a sheet charge within the oxide.
(a) Conditions for V
G
= 0. (b) Flat-band condition.

To reach the flat-band condition (i.e., no charge induced in the semiconductor), we must apply a
negative voltage to the metal, as shown in Figure B2b. As the negative voltage increases, more
negative charges are put on the metal and thereby the electric-field distribution shifts downward
until the electric field at the semiconductor surface is zero. Under this condition the area
contained under the electric-field distribution corresponds to the flat band voltage V
FB
:

The flat-band voltage is thus dependent on both the density of the sheet charge Q
o
and its
location x
0
within the oxide. When the sheet charge is located very close to the metal-that is, if x
0

= 0- it will induce no charges in the silicon and therefore have no effect on the flat-band voltage.
On the other hand, when Q
o
is located very close to the semiconductor- x
0
= d, (such as the fixed
oxide charges Qf)-it will exert its maximum influence and give rise a flat-band voltage
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D. Y. Tang Page 24 3/31/08

For the more general case of an arbitrary space charge distribution within the oxide, the flat-
band voltage is given by an expression similar to Eq. 72:

where (x ) is the volume charge density in the oxide. Once we know
ot
(x), the volume charge
density for the oxide-trapped charges, and p
m
(x), the volume charge density for the mobile ionic
charges, we can obtain Q
ot
, and Q
m
and their corresponding contribution to the flat-band voltage:

If the value of the work function difference q
ms
is not zero, and if the values of Qf, Qm, and Q
o
,
are significant (assuming negligible interface traps), the experimental capacitance-voltage curve
will be shifted from the ideal theoretical curve by an amount

Therefore, the presence of the fixed charge simply cause a voltage drop across the oxide given
by

ox
ss
C
Q
V

= (37)

where Q
ss
is the fixed charge density in the oxide. As a result, if Q
ss
is positive the entire C-V
curve shifts to a more negative value. Since the charge Q
ss
is independent of the gate bias, the
entire C-V curve shifts as shown schematically in Fig. 21. The value of Q
ss
can be obtained by
measuring the shift as compared with the calculated ideal curve. Such measurements are very
important for characterizing the quality of MOS devices.

The interface charge has a somewhat different effect on the C-V characteristics. In an ideal
system, there are no allowed electron states in the bandgap of a semiconductor. However, since
the Si-SiO
2
interface is not ideal, a certain density of interface state is produced, which lie in the
bandgap region. In contrast to the fixed charge, electrons can flow into and out of these interface
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D. Y. Tang Page 25 3/31/08
states depending on the position of the Fermi level. The character of the interface states is
defined as acceptor-like and donor-like. An acceptor state is neutral if the Fermi level is
below the state (i.e., the state is unoccupied). The donor state is neutral if the Fermi level is
above it (i.e., the state is occupied) and positively charged when it is empty. As a result, when
the position of the Fermi level is altered, the charge in the interface changes. When the interface
charge is positive, the C-V curve shifts towards negative voltages, while when it is negative, the
curve shifts towards positive voltages. This is shown schematically in Fig. 22. The C-V curve is
thus smeared out due to the presence of interface states. In modern high quality MOS
structures, the interface states density is maintained below 10
10
cm
-2
, so that the effect is
negligible.

Fig. 21: A plot of the high frequency capacitance voltage of MOS capacitors with different values of the fixed oxide
charge. The shift of the C-V curves from an ideal calculated result allows one to calculate the fixed charge value.

Fig. 22: The effect of the interface states is to smear out the C-V curves.

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D. Y. Tang Page 26 3/31/08

III. MOSFET

The MOS structure by itself is usually not used as an electronic device, but the MOSFET device
utilizes the concepts developed. The MOSFET is perhaps the most important electronic devices.
This part of the notes explains MOSFET principles and characteristics, introduces MOSFET
technology and describes MOSFET models and parameters used in circuit simulation.

MOSFET structure

We have shown above how a gate voltage on an MOS structure can change the charge density of
free electrons at the oxide-semiconductor interface. Negative gate voltages attract the holes from
the p-type silicon to the surface (accumulation) while positive voltages larger than the threshold
voltage create a layer of electrons at the surface (inversion). The free electrons can obviously
carry a current in the direction parallel to the interface. Thus, in principle, the gate can modulate
the conductivity of the MOS channel if additional contacts are placed across the channel. This
leads to the MOSFET structure shown in Fig. 23.

Fig. 23: Basic components of a p-substrate MOSFET

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D. Y. Tang Page 27 3/31/08

Fig. 24: Cross-section, perspective view, and symbol of an N-channel MOSFET (NMOS)

In addition to the gate metal, which is isolated from the conducting channel, we have source and
drain ohmic contacts. Thus if a bias is applied between the source and drain, a current will flow
in the channel. The current will be determined by the free charge in the channel, which is
controlled by the gate voltage.

It is obvious from the figure that the MOSFET is essentially a four-terminal device. The four
terminals are as follows: the silicon substrate (bulk) (B), the gate (G), the source (S), and the
drain (D). The metal contacts to the source, drain, and bulk (S, D. and B, respectively). Very
frequently, the bulk and the source are connected together, so that the controlling voltage applied
to the gate, and the driving voltage applied to the drain, can be expressed with respect to the
common reference potential of the short-circuited source and bulk. In this case the three effective
MOSFET terminals, the gate, the drain and the source, can directly be related to the G, D, and S
terminals of the generic transistor. Sometime the bulk and the source cannot be short circuited, or
a voltage is deliberately applied between the bulk and the source. The effect of the bulk-to-
source voltage is called body effect.
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D. Y. Tang Page 28 3/31/08

MOSFET as a switch: the threshold voltage

To describe the principle of MOSFET, again the energy band model is used to elucidate the
response of electrons and holes to the externally applied voltage. It should be noted that
MOSFET effects must be considered in two dimensions. The first dimension is needed to
express the gate voltage-related effects. That is to follow the direction from the silicon surface
into the silicon bulk (labeled as the x-direction). The second direction is needed to express the
drain-to-source voltage-related effects. That is along the silicon surface (labeled as the y-
direction). Because of that, the energy band has to be shown in both the x- and the y-directions.

Zero-effective bias (flat bands)

As already mentioned, the ON and OFF states of the MOSFET are controlled by the gate
voltage, which directly determines the potential at the surface of the silicon. The potential at the
semiconductor surface with respect to its bulk will be denotes by
s
. It appears as natural to take
the zero surface potential as the reference point when different conditions of the silicon surface
(as induced by different gate voltage) are considered. The zero surface-potential condition is also
known as the flat-band condition, as in this case the electric-potential line, hence the potential-
energy lines in the energy band-diagram, are flat. It is to note that the flat bands typically do not
occur for zero gate voltage, due to the effects of work-function difference and oxide charge. The
gate voltage needed to bring the silicon surface into the flat-band condition was called flat-band
voltage.

Fig. 25 illustrates the MOSFET in the flat-band condition. Note that the source and the bulk are
short circuited and taken as the reference potential, and that no drain-to-source voltage is applied
(V
DS
=0). The left-hand side and the right-hand side of the first row of diagrams illustrate the
MOSFET cross sections in the x- and y- directions, respectively. The central diagram illustrates
the MOSFET in three dimensions. The MOSFET is positioned so that the x- and y-directions
coincide with the x- and y-directions in the energy-band diagrams presented in the second row of
diagrams. Again, the left-hand side and the right-hand side represent the energy-band diagrams
along the x- and the y-directions, respectively, while the central diagram is a two-dimensional
presentation of the conduction band. The energy band diagram along x-direction clearly
illustrates the flat-band condition.

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D. Y. Tang Page 29 3/31/08

Fig. 25: MOSFET in cutoff region

The energy-band diagram along the y-direction is shown in bottom right comer. Nonetheless, it
can easily be deduced from the energy-band diagram of the n-p junction. Note that the surface
structure of the MOSFET (along the y-direction) can be represented by two n-p junctions with
the p regions connected to each other. That is, the surface N
+
-P-N
+
structure can be split into N
+
-
P and P-N
+
structures where the p regions are connected to each other. Noting that N
+
denotes
only that the doping level in the N
+
-type regions is high, the energy-band diagram of the N
+
-type
source and p-type substrate (along the y-direction) is constructed in the same way as the energy-
band diagram of the n-p junction. The remaining part (P-type substrate and N
+
-type drain) is a
mirror image of the source- substrate part, and the energy-band diagram is completed by the
mirror image of the n-p junction band diagram.

When illustrating the appearance of mobile electrons and holes, it is important to remember that
the electron and hole concentrations are expressed by the position of the Fermi level (dash-dotted
line) with respect to the energy bands. In the energy-band diagram along the x-direction (bottom
left comer), the Fermi level is close to the top of the valence band, which means a number of
hole positions in the valence band are actually occupied by holes (open symbols). This is the
case in a p-type semiconductor, which is the substrate of the MOSFET. The same situation is
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D. Y. Tang Page 30 3/31/08
seen between the source and drain in the energy band diagram along the y-direction (bottom
right comer). However, in the N
+
regions of the source and drain, the Fermi level is very close to
the bottom of the conduction band, which means a large number of electron positions in the
conduction band are actually occupied by electrons (closed symbols). The Fermi level along the
y-direction is constant, which expresses the fact that no voltage is applied between the drain and
the source (thermal equilibrium).

The energy-band diagram along the y-direction (bottom right comer) illustrates that there is an
energy barrier that separates the electrons from the source and the drain. If the barrier was not
there, and the bottom of the conduction band in the drain was lowered, the electrons would start
flowing from the source into the drain.

As long as there is an energy barrier between the source and the drain, applying a voltage
between the drain and the source (V
DS
) does not produce any electron current flow. The
MOSFET is said to be in cutoff region.

Fig. 26: Output characteristic (Solid line) in the cutoff region

This is expressed by the solid line in Fig. 26, which shows that the drain current I
D
is zero for
any V
DS
voltage. The energy-band diagrams in Fig. 25 are drawn for the particular case of V
DS
=
0, which is indicated on the output characteristic of Fig. 26 by positioning the quiescent point Q
at V
DS
= 0.

Strong Inversion

To set the MOSFET in ON mode, the energy-potential barrier between the source and the drain
has to be reduced. This is achieved by applying positive voltage between the gate and the
bulk/source. A part of the applied voltage will drop across the oxide, while the other part will
appear as the surface potential
s
. The appearance of the positive surface potential
s,
is seen on
the energy-band diagrams as band bending downward from the reference bulk level (remember,
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D. Y. Tang Page 31 3/31/08
potential energy = -q electric potential). This means that the energy barrier at the surface is
being reduced, as can be seen in Fig. 27.

Fig. 27: MOSFET in strong inversion

How much should the energy barrier be reduced before the electrons can start flowing between
the source and the drain? To answer this important question, let us consider the position of the
Fermi level at the silicon surface. To have a significant concentration of electrons at the silicon
surface, so that the source and the drain are joined by a channel of electrons, the Fermi level
should be closer to the bottom of the conduction band than to the top of the valence band.
Normally, the Fermi level is closer to the top of the valence band in a p-type semiconductor.
However, as the bands are bent at the silicon surface, the top of the valence band moves away
from the Fermi level, while the bottom of the conduction band moves toward the Fermi level
(refer to the bottom left energy-band diagram in Fig. 27). Once the Fermi level is closer to the
bottom of the conduction band, the occupancy of electron states in the conduction band is more
likely than the occupancy of hole states in the valence band, and the concentration of electrons
becomes higher than the concentration of holes. At this stage the inversion layer (channel of
electrons) is being created. However, the concentration of electrons is not significant before the
surface potential reaches the value of 2
B
(the strong inversion condition). Beyond that point the
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D. Y. Tang Page 32 3/31/08
band bending slows down rapidly and almost saturates, as illustrated in Fig. 28. Any further
increase in the gate voltage V
GS
is quickly addressed by an adequate increase in the electron
concentration, which forces most of the whole voltage increase V
GS
to appear across the oxide,
leaving the surface potential virtually unchanged.

Fig. 28: The operating point Q is at zero drain current as no driving voltage is applied.

The surface potential in strong inversion is pinned at

B s
2 (38)

where
B
is the Fermi potential. The gate voltage needed to bring the surface potential to this
level is called the threshold voltage, V
T
.

The Fermi potential is an important semiconductor parameter as it expresses the doping type and
the level. The Fermi potential is directly related to the difference between the mid-gap and the
Fermi level (
F i B
F E q = ).

To analyze the threshold voltage, it is reasonable to assume that the electron concentration in the
channel is zero below the threshold voltage, and that it increases linearly with any voltage
increase beyond the threshold voltage. However, this does not mean there is no charge at the
MOS capacitor plates at the onset of strong inversion (V
GS
= V
T
). When positive effective
voltage V
GS
- V
FB
is applied to the gate, the holes from the silicon surface are repelled, leaving
behind uncompensated negative acceptor ions. This charge is called the depletion-layer charge.
The density of this charge, Q
d
, is expressed in C/m
2
. If the charge density at the capacitor plates
(Q
d
in this case) is divided by the capacitance per unit area (the gate-oxide capacitance C
ox
in this
case), the effective voltage drop across the capacitor dielectric is obtained. Therefore,

V
GS
- V
FB
-
s
= Q
d
/C
ox
(for V
GS
< V
T
) (39)

Using the fact that the surface potential is
s
= 2
B
at the onset of strong inversion (V
GS
= V
T
),
the following equation is obtained:

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D. Y. Tang Page 33 3/31/08

ox
d
B FB T
C
Q
V V = 2 (40)

which leads to the following equation for the threshold voltage:

ox
d
B FB T
C
Q
V V + + = 2 (41)

It was shown that the depletion-layer charge density can be calculated as Q
d
= qN
A
W, where W is
the depletion-layer width, which should be obtained from the Poisson equation. The solution of
the Poisson equation enables the Q
d
/C
ox
term to be converted into
B
2 , where is a
technological constant called the body factor. Therefore, the threshold voltage equation is
written in the following form:

B B FB T
V V 2 2 + + = (42)

V
FB
,
B
, and are all technological parameters, therefore the threshold voltage is a technological
parameter.

The threshold voltage represents the value of the gate voltage needed to set the silicon surface at
the onset of strong inversion.

1. The density of channel carriers Q
I
, is negligible for V
GS
< V
T
, as the strong inversion
condition is not reached.

2. The density of the channel carriers in the strong-inversion region is determined by the
value of the gate voltage in excess of the threshold voltage (V
GS
- V
T
) and the gate-oxide
capacitance:

Q
I
= (V
GS
- V
T
) C
ox
(43)

Figure 27 illustrates the MOSFET in strong inversion (MOSFET in the ON mode) with no drain-
to-source voltage applied, V
DS
= 0. The bottom right energy-band diagram (y-direction) shows
the formation of the channel of electrons between the source and the drain. As no drain-to-source
voltage is applied, the bottom of the conduction band in the channel is flat in the Y-direction. As
a consequence, there is no flow of electrons, and the drain current I
D
is zero. The position of the
quiescent point, shown in the output characteristic of Fig. 28, expresses the fact that the drain
current is zero for V
DS
= 0, even though the MOSFET is set in the ON mode.

If the bottom of the conduction band in the drain is lowered with respect to the source, the
energy bands in the channel region will be tilted and the electrons in the channel will start rolling
down into the drain, as illustrated in Fig. 29. The lowering of the bottom of the conduction band
in the drain is achieved by externally applied voltage V
DS
. The bottom right energy-band diagram
in Fig. 29 shows that the energy difference between the source and the drain is exactly qV
DS
.

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D. Y. Tang Page 34 3/31/08
The two main factors influencing the value of the current I
D
are the slope of the energy bands
and the density of electrons in the channel. As the slope is directly proportional to V
DS
, and the
channel electron density is given by Eq. 43, the drain current can be expressed as

( )
DS T GS D
V V V I = (44)

where the proportionality factor involves the oxide capacitance C
ox
. It can be shown that the
factor depends on a number of other parameter, in addition to C
ox
.

Fig. 29: MOSFET in linear region
Equation (44) predicts a linear dependence of the drain current I
D
on the drain-to-source voltage
V
DS
. As Fig. 30 illustrates, this is correct for small V
DS
values. This region of V
DS
voltage is
referred to as the linear region. The reasons the current saturation occurs at larger V
DS
voltages
are considered in next section.
________________________________________________________________________

D. Y. Tang Page 35 3/31/08

Fig. 30: The output characteristics of MOSFET in linear region

Body Effect

It has so far been assumed that the source and the bulk of the MOSFET are short circuited (V
BS
=
0). Although the MOSFETs are very frequently used in this way, there are some applications in
which the bulk and the source cannot be short circuited, or nonzero voltage is deliberately
applied between the bulk and the source. In the case of N-channel MOSFETs, therefore P-type
bulk and N-type source, the voltage applied between the bulk and the source should not be
positive, as it would bias the bulk-to-source p-n junction in the forward mode, opening a current
path between the source and the bulk. Negative bulk-to-source voltages (V
BS
< 0), or equivalently
positive source-to-bulk voltages (V
SB
> 0), set the bulk-to-source p-n junction in reverse mode.
The reverse bias of the bulk-to-source junction increases the threshold voltage of the MOSFET,
which is the effect referred to as the body effect.

To understand the body effect, the MOSFET has to be considered in two dimensions: one normal
to the semiconductor surface (along the x -axis) and the other along the channel (y-axis). Figure
31 provides the energy bands of a MOSFET along those two dimensions for different surface
potentials
s
. In Fig. 31a, the surface potential with respect to the bulk is zero (flat bands in the
P-type substrate along the x-axis). The effect of the applied V
SB
voltage is seen in the energy-
band diagram along the y-axis. It shows that the applied voltage V
SB
splits the Fermi level into
quasi-Fermi levels of the p-type substrate (E
FP
) and n-type source (E
FN
). As a consequence, the
energy barrier between the electrons in the source and the channel is increased by qV
SB
when
compared to the case of V
SB
= 0 (Fig. 25).

Figure 31b illustrates the case of
s
= 2
B
, This is the value of the surface potential that
corresponds to the strong-inversion mode (the channel of electrons formed) in the case V
SB
= 0.
As can be seen from Fig. 31b, the surface potential of
s
= 2
B
does not reduce the energy
barrier between the source and the channel sufficiently in the case of V
SB
> 0. To compensate for
the effect of the V
SB
bias, the surface potential needs to be further increased (therefore, the
energybarrier reduced), and that is exactly by V
SB
. Fig. 31c illustrates that the energy barrier
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D. Y. Tang Page 36 3/31/08
between the source and the channel is reduced to the small strong-inversion value when
s
=
2
B
+V
SB
.

Fig. 31: Illustration of the body-effect: (a) V
sb
voltage increases the barrier between the electrons in the source and
the channel, (b) the surface potential of 2
B
does not reduce the barrier sufficiently for the electrons to be able to
move into the channel, and (c) the surface potential needed to form the channel is 2
B
+ V
SB.
________________________________________________________________________

D. Y. Tang Page 37 3/31/08

In the case of V
SB
> 0, the surface potential in strong inversion is
s
= 2
B
+ V
SB
.

To derive the threshold voltage equation, Eq. (39) has to be modified to account for the fact that
the bulk is not grounded in this case but voltage V
SB
> 0 is applied. To obtain the voltage drop
across the gate oxide, the surface potential
s
(expressed with respect to the bulk potential) is
subtracted from the gate-to-bulk voltage. As the gate-to-bulk voltage is equal to V
GS
+ V
SB
, Eq.
(39) becomes

ox
d
s FB SB GS
C
Q
V V V = + (for
T GS
V V ) (45)

Given that the surface potential is
s
= 2
B
+ V
SB
at the onset of strong inversion (V
GS

=V
T
), the following equation is obtained:

( )
ox
d
SB B FB SB T
C
Q
V V V V = + + 2 (46)
which appears to lead to the same threshold voltage equation as Eq. (41):

ox
d
B FB T
C
Q
V V + + = 2 (47)

There is a difference, however, due to the fact that Q
d
depends on the surface potential. It has
been shown that Q
d
/C
ox
can be convened into
B
2 , when V
SB
= 0. In the case of V
SB
> 0, the
surface potential is not 2
B
but 2
B
+ V
SB
, which means Q
d
/C
ox
converts into
SB B
V + 2 .
Therefore, the threshold voltage equation, which involves the effect of V
SB
voltage, has the
following form:

SB B B FB T
V V V + + + = 2 2 (48)

The threshold voltage increase V
T
, caused by the voltage V
SB
is

( ) ( ) ( )
B SB B SB T SB T T
V V V V V V 2 2 0 + = = = (49)

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D. Y. Tang Page 38 3/31/08
MOSFET as a Voltage-Controlled current Source: Mechanisms of Current Saturation

When the MOSFET is operated as a closed switch (V
GS
> V
T
and V
DS
< V
DSsat
), the normal
electric field from the gate voltage V
GS
holds the electrons in the inversion layer channel, while
the lateral electrical field due to the drain-to-source voltage V
DS
rolls them into the drain. The
channel of electrons expands all the way from the source to the drain, the resistance of which
determines the slope of the linear I
D
- V
DS
characteristic.

To use the MOSFET as a current source, I
D
should become independent of V
DS
. This happens at
larger drain-to-source voltages (V
DS
> V
DSsat
), an effect referred to as current saturation. There
are two different mechanisms that can cause drain current saturation in MOSFETs. These two
mechanisms are considered in the following text.

Channel Pinch-off

As the drain-to-source voltage V
DS
is increased, the lateral electric field in the channel is
increased as well, and may become stronger than the vertical electric field due to the gate
voltage. This would first happen at the drain end of the channel. In this situation, the vertical
field is unable to keep the electrons at the drain end of the channel as the stronger lateral field
sweeps them into the drain. The channel is pinched off at the drain end. The drain-to-source
voltage at which this happens is called the saturation voltage, V
DSsat

An increase of V
DS
beyond V
DSsat
expands the region in which the lateral field is stronger than the
vertical field in the channel, effectively moving the pinch-off point closer to the source. This is
illustrated in the MOSFET cross section along the y-axis, shown in Fig. 32 (upper-right corner).
The region created between the pinch-off point and the drain is basically the depletion layer at
the reverse-biased drain-substrate junction. Note that we are considering the surface area of the
junction, which is influenced by the gate field. Consequently, the surface region of the P-N
junction is not in the reverse-bias mode until the drain voltage reaches V
DSsat
. This is different
from the bulk region of the junction, which is in reverse-bias mode for any positive V
DS
voltage.

________________________________________________________________________

D. Y. Tang Page 39 3/31/08

Fig. 32: MOSFET in saturation region

The voltage drop across the surface depletion region (the reverse bias) is V
DS
- V
DSsat
, which is
the voltage increase beyond V
DSsat
. The remaining part of the drain-to-source voltage, which is
V
DSsat
, drops between the pinch-off point and the source. In this region the vertical field is
stronger than the lateral field, and the inversion layer (channel of electrons) still exists. It is in
fact this part of the source-to-drain region, labeled as channel in Fig. 32, that determines the
value of the drain current.

The voltage drop across the channel of electrons is fixed to V
DSsat
for V
DS
> V
DSsat
. As a
consequence, the drain current remains fixed to the value corresponding to V
DSsat
. This effect is
called drain current saturation, and the V
DS
> V
DSsat
region of the MOSFET operation is
referred to as the saturation region.

The energy-band diagram of the MOSFET along the y-axis (bottom right diagram in Fig. 32)
provides a clearer insight into the effect of current saturation due to channel pinch-off. It shows
very steep energy bands in the depletion region, which represents the situation of a very strong
lateral field in this region. Electrons do not spend much time on this very steep part of the bottom
of the conduction band; they very quickly roll down into the drain. This part of the source-to-
drain region offers little resistance to the electrons. Although an increase of V
DS
beyond V
DSsat

continues to lower the position of the conduction band in the drain, Fig. 32 illustrates that this
does not increase the drain current. The electrons in this shape of energy bands can be compared
________________________________________________________________________

D. Y. Tang Page 40 3/31/08
to a waterfall: the water current depends on the amount of water before the fall (the channel) and
not on the height of the waterfall (qV
DS
- qV
DSsat
).

1. The depletion region has little influence on the drain current.
2. The value of the drain current is limited by the number of electrons that appear at the edge
of the depletion region (the pinch-off point).
3. The number of the electrons in the channel, and therefore at the pinch-off point, is
controlled by the gate voltage and not the drain voltage.
4. As a consequence, the drain current is controlled by the gate voltage, and is independent of
the drain voltage.
5. The MOSFET acts as a voltage-controlled current source.

Fig. 33: The Output (b) and transfer (c) characteristics of MOSFET in saturation region

I
D
- V
DS
characteristics shown in Fig 33 illustrate the effect of drain current saturation. The solid
line shows the complete I
D
- V
DS
dependence in the strong inversion for a fixed V
GS
voltage (V
GS

= 5 V in the example of Fig. 33). The characteristic is linear for small V
DS
voltages. It deviates
from the linear dependence as the increased V
DS
starts depleting electrons from the drain end of
the channel. The drain-to-source voltage value that pinches off the channel at the drain end is the
saturation voltage, V
DSsat
.

The region of drain-to-source voltages between zero and the saturation voltage (0 < V
DS
< V
DSsat
)
is referred to as the triode region. The region of drain-to-source voltages higher than the
saturation voltage (V
DS
> V
DSsat
) is the saturation region.

The dotted lines in Fig. 33b and the I
D
-V
GS
characteristic of Fig. 33c (transfer characteristic)
illustrate the effect of the gate voltage. It is obvious that the current depends on the gate voltage
even in the saturation region. This is because the gate voltage determines the number of electrons
in the channel (in strong inversion), which in turn directly determines the current. This is a useful
property, as it enables the current source (that is MOSFET in saturation) to be controlled by
voltage. Figure 33b also shows that the saturation voltage V
DSsat
is different for different V
GS
________________________________________________________________________

D. Y. Tang Page 41 3/31/08
voltages. This is due to the fact that a much smaller drain-to-source voltage is needed to
overcome the effect of a smaller gate voltage and pinch the channel off at the drain end.

MOSFET modeling

Deriving a MOSFET model means finding an equation to represent the dependence of the drain
current I
D
on the applied terminal voltages V
GS
, V
DS
, and V
SB
, in general form I
D
= f(V
GS
, V
DS
,
V
SB
). Assuming that all channel electrons terminate at the drain, and neglecting drain-substrate
reverse-bias current, the current of the electrons in the channel directly expresses the terminal
drain current I
D
. The electron flow in the channel is caused by the electric field appearing in the
channel due to the drain-to-source bias V
DS
. This current mechanism, known as drift current, is
modeled by Ohms law:

E j = (51)

where j is the current density in A/m
2
, E is the electric field, and is the conductivity. The
conductivity can be expressed in terms of the electron concentration n and electron mobility
0
,
which leads to

nE q j
0
= (52)

It appears the current density of the electrons in the channel j, given in units of A/m
2
can simply
be multiplied by the channel cross-sectional area to convert it into the drain cur-rent I
D
, which is
in unit A. This would implicitly assume a uniform current density. If the current density changes,
it would mean that the average value of the current density is actually taken. If this approach is to
be used, all the other differential quantities should be represented by their average values.
Denoting the channel cross section by X
ch
W, and expressing the average value of the electric
field by V
DS
/L
eff
,

E W qnX W jX
ch ch
=
0
(53)

The following equation is obtained:

DS I
eff
D
V Q
L
W
I
_
0
= (54)

Q
I
in the above equations is the average value of the inversion-layer charge density, expressed in
C/m
2
. For the case of zero, or very small drain-to-source voltage V
DS
, the inversion-layer charge
density is determined only by the gate-to-source voltage V
GS
. It is equal to zero for V
GS
< V
T
, and
equal to (V
GS
- V
T
)C
ox
for V
GS
> V
T
. Therefore, the inversion-layer charge density is uniform
along the channel in the case of small V
DS
. Replacing Q
I
in Eq. (54) by Q
I
from Eq. (43), the
drain current is obtained as

________________________________________________________________________

D. Y. Tang Page 42 3/31/08
( )
DS T GS
eff
ox
D
V V V
L
WC
I =
0
(55)

which becomes equivalent to the intuitively established Eq. (44) when the gain factor is
defined as:

eff
ox
L
WC
0
= (56)

Equation (55) predicts a linear dependence of the drain current on both the gate-to-source and the
drain-to-source voltages. The linear I
D
- V
DS
dependence is experimentally observed for small
V
DS
voltages, the region referred to as the linear region. An example of experimental I
D
- V
DS

dependence is given in Fig. 27. However, the actual current can deviate from this linear
dependence, and even saturate at sufficiently large V
DS
voltages. As mentioned earlier, the
region of V
DS
voltages between 0 and the drain-to-source voltage at which the drain current
saturates (V
DSsat
) is referred to as the triode region.

To model the drain current in the whole triode region (not only its linear part), the influence of
V
DS
voltage on the inversion-layer charge density cannot be neglected, As V
DS
voltage is
increased, the drain end of the inversion layer is being gradually depleted, until it is completely
pinched off at the drain end, which is the point of drain current saturation (V
DS
= V
DSsat
).
Therefore, the V
DS
voltage causes a non-uniform distribution of the inversion-layer charge
density along the channel, as illustrated in Fig. 5.17. It also causes a reduction of its average
value Q
I
, which is reflected in the current fall below that predicted by the uniform (maximum
average) Q
I
.

Q
I
reduction toward the drain end of the channel can be modeled through a threshold voltage
increase caused by the body effect, which varies in strength along the channel. As described, the
increase of strong-inversion surface potential due to the substrate bias is reflected as a threshold
voltage increase. In the example of Fig. 31, the surface potential is increased from the usual 2
B
to 2
B
+ V
SB
due to the reverse source bulk bias V
SB
. In Fig. 31, this is the situation at the source
end of the channel. At the drain end of the channel, the surface potential in strong inversion is
increased further to 2
B
+ V
SB
+V
DS
, to include the reverse bias of the drain-bulk P-N junction
which is V
DS
+ V
SB
- Consequently, the threshold voltage at the drain end of the inversion layer is
larger than at the source end (stronger body effect due to the larger body bias, V
DS
+ V
SB
).
According to Eq. (43), the larger threshold voltage causes a smaller inversion-layer charge
density Q
I
at the drain end of the channel. The varying threshold voltage along the channel can
uniquely be expressed in terms of the surface potential by generalizing Eq. (48) in the following
way:

SB B SB B SB FB T
V V V V V + + + + = 2 2 (57)

As long as
s
is fixed to 2
B
+V
SB
, this threshold voltage equation is equivalent to Eq. (48).
However, if
s
is allowed to take any value between 2
B
+V
SB
(the surface potential at the source
________________________________________________________________________

D. Y. Tang Page 43 3/31/08
end) and 2
B
+V
SB
+V
DS
(the surface potential at the drain end of the channel), the threshold
voltage becomes a differential quantity that varies along the channel due to the surface potential
variation:

( )
s s SB FB s T
V V v + + = (58)

In principle, the average inversion-layer charge density, to be used in Eq. (54), should be
obtained through the following averaging formula:

( ) ( ) [ ]

= =
eff eff
L
ox s T GS
eff
L
I
eff
I
dy C v V
L
dy y Q
L
Q
0 0
_
1 1
(59)

However, the integration with respect to y (the space coordinate along the channel) is not
possible as the surface potential dependence, and for that matter the threshold voltage
dependence on y, is not established. Instead, the averaging is performed as follows:

( ) ( )
( ) ( ) [ ]

+ +
+
+ +
+
=
+ + +
=
DS
SB B
SB B
DS
SB F
SB F
V V
V
s ox s T GS
DS
s
V V
V
s I
SB B DS SB B
I
d C v V
V
d Q
V V V
Q

2
2
2
2
_
1
2 2
1

(60)

Replacing v
T
(
s
) from Eq. (58), and solving the above integral, the following result is obtained:

( ) ( )
)
`
+ + +
|
\
|
= 2
3
2
3 _
2 2
3
2
2
2
SB B DS SB B DS
DS
B FB GS
DS
ox
I
V V V V
V
V V
V
C
Q
(61)

Inserting the obtained equation for the average inversion-layer charge density Q
I
into
Eq. (54), the drain current is obtained as

( ) ( )
)
`
+ + +
|
\
|
= 2
3
2
3
2 2
3
2
2
2
SB B DS SB B DS
DS
B FB GS D
V V V V
V
V V I
(62)

where the gain factor originally defined by Eq. (56), is frequently expressed through
the so-called transconductance parameter K P:

eff eff
ox
L
W
KP
L
WC
= =
0
(63)

Equation (62) represents the MOSFET model in the triode region. The plots of this equation
show that it can be used only in the triode region. In this region the equation correctly predicts I
D

________________________________________________________________________

D. Y. Tang Page 44 3/31/08
increase with V
DS
. It cannot be used in the region where it shows a current decrease, which is the
saturation region, because its derivation has not included the case of channel pinch-off. As the
threshold voltage is larger than the gate-to-source voltage in the pinch-off region, the negative
contribution of the V
GS
- v
T
(
s
) term in Eq. (60) erroneously reduces the value of the average
inversion-layer charge Q
I
which appears as the current reduction in the saturation region.
Nonetheless, the observation that the I
D
current, as predicted by Eq. (62), reaches maximum at
the saturation voltage V
DSsat
helps us find the value of the saturation voltage. Knowing that the
first derivation of I
DS
is zero at V
DS
= V
DSsat
(the maximum of the current I
D
), the saturation
voltage is obtained as

( )

+ + = =
1
4
1
2
2 0
2 SB FB GS B FB GS DSsat
DS
D
V V V V V V
V
I
(64)

The model works in the following way: (1) the saturation drain voltage V
DSsat
is calculated first,
using Eq. (64); (2) if V
DS
< V
DSsat
, V
DS
is used in Eq. (60) to calculate the current; (3) if V
DS
>
V
DSsat
, V
DSat
is used in Eq. (60) to calculate the current.

THRESHOLD VOLTAGE MODIFICATIONS

We derived the ideal MOSFET relations including expression for threshold voltage and for the
current-voltage characteristics. We have now considered some of the nonideal effects including
channel length modulation. Additional effects on threshold voltage occur as the devices shrink in
size. A reduction in channel length will increase the transconductance and frequency response of
the MOSFET, and a reduction in channel width will increase the packing density in an integrated
circuit. A reduction in either or both the channel length and channel width can affect the
threshold voltage.

Short-Channel Effects

For the ideal MOSFET, we derived the threshold voltage using the concept of charge neutrality
in which the sum of charges in the metal oxide inversion layer, and semiconductor space charge
region is zero. We also assumed that the gate area was the same as the active area in the
semiconductor. Using this assumption, we considered equivalent surface charge densities and
neglected any effects on threshold volt that might occur due to source and drain space charge
regions that extend into the active channel region.
Figure A1a shows the cross section of a long n-channel MOSFET at flat-band, with zero source
and drain voltage applied. The space charge regions at the source and drain extend into the
channel region, but occupy only a small fraction of the entire channel region. The gate voltage,
then, will control essentially all of the space charge induced in the channel region at inversion as
shown in Figure A1b.

________________________________________________________________________

D. Y. Tang Page 45 3/31/08

Fig.A1: cross section of a long channel MOSFET (a) at flat band and (b) at inversion.

Figure A2 Cross section of a short-channel MOSFET at flat band.

As the channel length decreases, the fraction of charge in the channel region controlled by the
gate decreases. This effect can be seen in Figure A2 for band condition. As the drain voltage
increases, the reverse-biased space charge region at the drain extends further into the channel
area and the gate will control even less bulk charge. The amount of charge in the channel region,
Q
SD
(max) controlled by the gate, affects the threshold voltage

We can quantitatively determine the short-channel effects on the threshold voltage by
considering the parameters shown in Figure A3. The source and drain junctions are characterized
by a diffused junction depth r
j
. We will assume lateral diffusion distance under the gate is the
same as the vertical diffusion. This assumption is a reasonably good approximation for diffused
junction, comes less accurate for ion implanted junctions. We will initially consider the case
when the source, drain, and body contacts are all at ground potential.
________________________________________________________________________

D. Y. Tang Page 46 3/31/08

Fig. A3: Charge sharing in the short channel threshold voltage model.

The basic assumption in this analysis is that the bulk charge in the trapezoidal region under the
gate is controlled by the gate. The potential difference across the bulk space charge region is 2
B
at the threshold inversion point, and-the built- in potential barrier height of the source and
drain junctions is also approximately 2
B
, implying that the three space charge widths are
essentially equal. We can then write

Using the geometrical approximation, the average bulk charge per unit area the trapezoid
is

from the geometry, we can show that

Then

The value is now used in place of Q'
SD
(max) in the expression for the threshold voltage.
Since , we can find V
T
as
________________________________________________________________________

D. Y. Tang Page 47 3/31/08

Where

V
T
=V
T(short channel)
-V
T(long channel)

As the channel length decreases, the threshold voltage shifts in the negative direction that an n-
channel MOSFET shifts toward depletion mode.

As the substrate doping increases, the initial threshold voltage increases, and the short-channel
threshold shift also becomes larger. The short-channel effects on threshold voltage do not
become significant until the channel length becomes less than approximately 2 um. The
threshold shift also becomes smaller as the diffusion depth rj becomes smaller-so that very
shallow junctions reduce the threshold voltage dependence on channel length.

Narrow-Channel Effects

Figure A4 shows the cross section along the channel width of an n-channel MOSFET biased at
inversion. The current is perpendicular to the channel width through the inversion charge. We
may note in the figure that there is an additional space charge region at each end of the channel
width. This additional charge is controlled by the gate voltage but was not included in the
derivation of the ideal threshold voltage relation. The threshold voltage expression must be
modified to include this additional charge.

If we neglect short-channel effects, the gate-controlled bulk charge can be written as

Where Q
B
is the total bulk charge, Q
BO
is the ideal bulk charge, and Q
B
is the additional bulk
charge at the ends of the channel width. For a uniformly doped p-type -semiconductor biased at
the threshold inversion point, we may write

And

where is a fitting parameter that accounts for the lateral space charge width. The lateral space
charge width may not be the same as the vertical width X
dT
due to the thicker field oxide at the
ends, and/or due to the nonuniform semiconductor doping created-by an ion implantation. If the
ends were a semicircle, then = /2.
________________________________________________________________________

D. Y. Tang Page 48 3/31/08

Figure A4: Cross section of an n-channel MOSFET showing the depletion region along the width
of the device.

We may now write

The effect of the end space charge regions becomes significant as the width decreases and the
factor (X
dT
) becomes a significant fraction of the width W.

The change in threshold voltage due to the additional space charge is

The shift in threshold voltage due to a narrow channel is in the positive direction for the n-
channel MOSFET. As the width W becomes smaller, the shift in threshold voltage becomes
larger.

CONTROL OF THE THRESHOLD VOLTAGE

Control of the threshold voltage is of major importance in the fabrication of MOSFETs since the
manufacturing spread in the value of V
T
, in general, may be relatively large. It is thus important
to adjust or restrict the value of V
T
so that it may conform to the required specifications.

The general expression for the threshold voltage of a MOSFET, assuming that the source and
body are grounded, is given by

________________________________________________________________________

D. Y. Tang Page 49 3/31/08

Let us look into the various components of V
T
and consider what changes may be made to attain
the desired value. In a previous section, we have determined the effect of the applications of a
body bias on V
T
. The flat band voltage, V
FB
, is negative for both P-channel and N-channel
devices. For P-channel devices, Q
dm
is positive and
B
is negative, so that V
T
is negative as
required by PMOS devices. For N-channel devices, both Q
dm
and
B
contribute positive
quantities, so that V
T
may be positive or negative. Most commonly, N-channel devices are
needed in digital circuits that operate in the enhancement mode, so that V
T
must be positive. To
guarantee a positive V
T
the sum of the magnitudes of 2
B
and Q
dm
must be greater than the
magnitude of V
FB
.

In order to increase the contributions of Q
dm
/C
ox
and 2
B
, two changes may be made. The doping
density N
A
and the oxide thickness can be increased. Increasing the impurity density increases
the depletion charge density, Q
dm
, while causing a small increase in q
B
that results in a more
positive value for V
T
. An upper limit is set on the doping by the junction breakdown voltage and
by the high substrate capacitance. Another disadvantage of using a large concentration of
impurities is the decrease of mobility as the doping density increases. The advantage of the
higher speed N-channel devices that is obtained, because of the higher mobility of electrons
when compared to holes, may be lost when the impurity density is increased to high values.

The second contribution that makes V
T
positive is a decrease in the oxide capacitance made
possible by an increase in the oxide thickness. The price to be paid for a smaller oxide
capacitance is a reduction in the drain current, which in turn results in a decrease of the
transconductance in the saturation region, which is translated into a smaller voltage gain.

In spite of the strong dependence of the threshold voltage on the substrate doping, on the oxide
capacitance, and on the ability to cause some improvements in V
T
for N-channel devices, the
values of the substrate doping and the oxide capacitance are determined mainly by other design
considerations. Furthermore, calculations for the threshold voltage do not yield exact results in
practical devices because of variations of oxide thickness, mobility, and oxide positive charges.

The most common method presently employed to improve the threshold voltage of MOSFETs is
ion implantation. This method allows not only for a fairly precise control of V
T
but also makes it
possible to tailor different threshold voltages for transistors on the same wafer, which may
include N-channel and P-channel devices.

The technique of ion implantation is the process of introducing ionized dopants by direct
bombardment of a surface. First, impurity atoms are ionized and are accelerated in a strong
electric field so they acquire energies in the range of 20 to 200keV. The ions are generated when
an arc discharge is caused to occur in a gas containing the dopant. These ions are made to strike
the oxide before the metallic gate electrode is deposited. The depth of penetration of the ions is
precisely adjusted by the accelerating voltage and the density of the ions deposited is determined
by the current of the ions and the duration of bombardment. While the implantation is carried out
at room temperature, the damage to the lattice caused by this method is removed by annealing at
temperatures of 600 C to 1000 C.

________________________________________________________________________

D. Y. Tang Page 50 3/31/08
For N-channel devices, boron ions are used that are made to rest at the siliconsilicon dioxide
interface. When the MOS is biased to strong inversion, the implanted ions act to oppose the
effect of the positive ions present at the oxide surface. The result is a positive shift in the
threshold voltage. The implantation of phosphorus ions causes a negative shift in the threshold
voltage. The shift in V
T
is found from V
T
= -qD
I
/C
ox
, where D
I
is the ion density per square
centimeter, which is negative for acceptor ions and positive for donor ions.

Subthreshold Current

The principal model assumes that the channel-carrier density is zero for V
GS
< V
T
, appearing
abruptly for gate voltages larger than the threshold: Q
I
= (V
GS
- V
T
)C
ox
. In reality, the transition
from full depletion to strong inversion is gradual (the term "strong" inversion indicates that there
would be a "moderate" and even a "weak" inversion). There are mobile carriers in the channel,
even for subthreshold gate voltages. Of course, their concentration is very small and is rapidly
decaying as the gate voltage is reduced below V
T
. Nonetheless, their effect is observable, as they
account for the gradual decay of the drain current from the above-threshold levels toward zero.

The vertical field is very low in the subthreshold region, and it does not take a large drain voltage
to fully sweep the carriers from the drain end. This creates a concentration gradient. Because of
this, and the low level of carrier concentration, the diffusion current dominates the drift current
in the subthreshold region. Consequently, a diode-like exponential current-voltage equation is
used to model the subthreshold current:

KT n
V
I I
s
GS
D subth D
exp
0
(50)

Channel Length Modulation

We assumed in the derivation of the ideal current-voltage relationship that the channel length L
was a constant. However, when the MOSFET is biased in the saturation region, the depletion
region at the drain terminal extends laterally into the channel, reducing the effective channel
length. Since the depletion region width is bias dependent, the effective channel length is also
bias dependent and is modulated by the drain-to-source voltage. This channel length modulation
effect is shown in Fig. A5 for an n-channel MOSFET.

________________________________________________________________________

D. Y. Tang Page 51 3/31/08

Figure A5: Cross-section of an n-channel MOSFET showing the channel length modulation
effect.

The depletion width extending into the p-region of a pn junction under zero bias be written as

For a one-sided n
+
p junction, essentially all of the applied reverse-bias voltage is across the low-
doped p region. The space charge width of the drain-substrate junction is approximately

However, the space-charge region defined by AL, as shown in Figure 12.5, does not begin to
form until V
DS
> V
DS
(sat). As a first approximation, we can write that L the total space charge
width minus the space charge width that exists when V
DS
(sat), or

Where

The applied drain-to-source voltage is VDs and we are assuming that V
DS
>V
DS(sat).

________________________________________________________________________

D. Y. Tang Page 52 3/31/08

Figure A6: Expanded view of cross section near the drain terminal of an n-channel MOSFET
showing the channel length modulation effect.

As a second approximation at determining AL, we can consider Figure A6 and revisit the one-
dimensional Poisson's equation. The electric field E
sat
is the lateral electric field at the point
where the inversion layer charge is pinched off. Neglecting any charges that exist due to current,
we can write

where p(x) = -eN
a
and is a constant for a uniformly doped substrate. Integrating above equation
and applying the boundary conditions gives the electric field in the space charge region defined
by L:

The potential in this region is

where C
1
is a constant of integration. The boundary conditions are (x=0)=V
DS(sat)
and
(x=L)=V
DS
. Substituting these boundary conditions into the equation, we obtain

Solving for L, we can write

________________________________________________________________________

D. Y. Tang Page 53 3/31/08
where

In general, the value of E
sat
is in the range 10
4
< E
sat
< 2 x 10
5
V/cm.

Figure A7: Current-voltage characteristics of a MOSFET showing short-channel effects

Other models used to determine L include the negative charges due to the drain current and
also include two-dimensional effects. These models will not be considered here.
Since the drain current is inversely proportional to the channel length, we may write

Where I
D
is the actual drain current and I

D
is the ideal drain current. Since L is a function of
V
DS
, I
D
' is now also a function of V
DS
even though the transistor is biased the saturation region.
Figure A7 shows some typical I
D
versus V
DS
curves with positive slopes in the saturation region
due to channel length modulation. As the MOSFET dimensions become smaller, the change in
the channel length L becomes a larger fraction of the original length L, and the channel length
modulation becomes more severe.

Device scaling effects

To increase the number of components per integrated circuit chip, the dimensions must be scaled
down. Commercial devices with minimum length (e.g., gate length) of 1 to 2 m are now
________________________________________________________________________

D. Y. Tang Page 54 3/31/08
available, and we expect that in the foreseeable future the minimum dimension will continue to
shrink into the submicron region. As the channels become shorter, many undesirable effects, the
so-called short-channel effects, will arise. We first consider these effects; then we shall consider
how to scale the device dimensions so that short-channel effects can be minimized.

Punch-through Effects

As the channel length L is reduced, the depletion layer widths of the source and drain junction
become comparable to the channel length. If we use an abrupt one-dimensional approximation,
the width of the source junction W
S
and that of the drain junction W
D
are

( )
( )
BS bi D
A
s
D
BS bi
A
s
s
V V V
qN
W
V V
qN
W
+ + =
+ =
2
2
(65)

where V
BS
is the magnitude of the substrate bias. When W
S
+ W
D
= L, punch-through will occur.
At punch-through, the two depletion layers merge and the gate loses control of the current.
Therefore, punch-through is a major limitation of device operation for short-channel MOSFETs.

Mobility variation and Velocity saturation

In a typical circuit application, the biasing voltage V
D
is usually kept at a constant value (say, 5
V). As the channel length becomes smaller, the longitudinal electrical field
y
will increase; the
channel mobility becomes field dependent, and eventually velocity saturation occurs. Even at
very small E
y
, the mobility in the channel is lower than the mobility in the bulk. A measured
result is shown in Fig. 34 as a function of the transverse field E
x
. The mobility for bulk silicon
with N
A
= 10
15
cm
-3
is 1500 cm
2
/V-s. In a MOSFET, the carrier transport is confined within the
narrow inversion region (the inversion layer is about 10 to 100 ), and surface scattering, shown
in the insert of Fig. 34 causes some reduction of the mobility. The average channel mobility is
approximately half that of the bulk mobility.

Figure 35 shows the measured drift velocity of electrons in an n-channel device for a selected
number of transverse field E
x
as a function of the longitudinal field E
y
, At low E
y
(~10
3
V/cm),
the drift velocity varies linearly with E
y
. This results in a constant mobility. The low-field
mobility corresponds to that shown in Fig. 34. As E
y
increases, the drift velocity tends to increase
more slowly; and when E
y
reaches 10
5
V/cm, the drift velocity approaches a saturation velocity
v
s
= 9 10
6
cm/s.

The drain current I
Dsat
is the number of carriers times their velocity, multiplied by q. If v = v
s
, we
have

________________________________________________________________________

D. Y. Tang Page 55 3/31/08
( )
=
i
x
s Dsat
dx x n Zq I
0
(66)

where x
i
is the width of the inversion layer. The integral equals the inversion charge per unit area
Q
n
. At the source end of the channel, this charge can he expressed as (V
G
- V
T
)C
0
. Therefore, Eq.
66 becomes

( )
T G s Dsat
V V ZC I
0
(67)

where the approximation introduced is due to the neglect of the variation in Q
n
along the
channel.

Fig. 34: Mobility versus longitudinal electric field in the inversion channel of an n-channel MOSFET.

________________________________________________________________________

D. Y. Tang Page 56 3/31/08

Fig. 35: Electron drift-velocity in the inversion channel as a function of longitudinal electric field for a selected
transverse field.

Constant-Field Scaling

The principle of constant-field scaling is that device dimensions and device voltage be scaled
such that electric fields (both horizontal and vertical) remain essentially constant. To ensure that
the reliability of the scaled device is not compromised, the electric fields in the scaled device
must not increase.
Figure A8 shows the cross section and parameters of an original NMOS device and Figure 10b
shows the scaled device, where the scaling parameter is k. Typically, k ~ 0.7 per generation of a
given technology. As seen in the figure, the channel length is scaled from L to kL. To maintain a
constant horizontal electric field, the drain voltage must also be scaled from kV
D
. The maximum
gate voltage will also be scaled from V
G
to kV
G
so that the gate and drain voltages remain
compatible. To maintain a constant vertical electric field, the oxide thickness then must also be
scaled from t
ox
to kt
ox
.

________________________________________________________________________

D. Y. Tang Page 57 3/31/08

Figure A8: Cross section of (a) original NMOS transistor and (b) scaled NMOS transistor.

The maximum depletion width at the drain terminal, for a one-sided pn junction, is

Since the channel length is being reduced, the depletion widths also need to be reduced. If the
substrate doping concentration is increased by the factor (1/ k), then the depletion width is
reduced by approximately the factor k since V
D
is reduced by k.
The drain current per channel width, for the transistor biased in the saturation region, can be
written as

the drift current per channel width remains essentially a constant, so if the channel width is
reduced by k, then the drain current is also reduced by k. The area of the device A WL, is
then reduced by k
2
and the power, P = I V, is also reduced by k
2
. The power density in the
chip remains unchanged.

Threshold Voltage - First Approximation

In constant-field scaling, the device voltages are reduced by the scaling factor k. It would
seem appropriate that the threshold voltage should also be scaled by the same factor. The
threshold voltage, for a uniformly doped substrate, can be written as

The first two terms in the equation are functions of material parameters that do not scale
and are only very slight functions of doping concentration. The last term is approximately
proportional to , so the threshold voltage does not scale with the scaling factor k.

________________________________________________________________________

D. Y. Tang Page 58 3/31/08
Generalized Scaling

In constant-field scaling, the applied voltages are scaled with the same scaling factor k as
the device dimensions. However, in actual technology evolution, voltages have not been
reduced with the same scaling factor. There has been reluctance, for example, to change
standardized power supply levels that have been used in previous circuits. In addition,
other factors that do not scale, such as threshold voltage and sub threshold currents, have
made the reduction in applied voltages less desirable consequence, electric fields in MOS
devices have tended to increase as device dimensions shrink.

Consequences of increased electric fields are reduced reliability and increased power
density. As the power density increases, the device temperature may increase. Increased
temperature may affect the device reliability. As the oxide thickness is reduced and the
electric field is increased, gate oxides are closer to breakdown, oxide integrity may be
more difficult to maintain. In addition, direct tunneling of carriers through the oxide may
be more likely to occur. Increased electric fields may also increase the chances of hot-
electron effects, which are discussed later in the L! Reducing device dimensions, then,
can introduce challenging problems that must be solved.

Radiation and hot- electron effects

We have considered the effects of fixed trapped oxide charge and interface state charge
on the capacitance-voltage characteristics of MOS capacitors and on the MOSFET
characteristics. These charges can exist because the oxide is essentially a perfect
dielectric and a net charge density can exist in a dielectric material processes that
generate these charges are ionizing radiation and impact ionization in the drain region of
a MOSFET operating near avalanche breakdown.

MOS devices are exposed to ionizing radiation, for example, in communication satellites
orbiting through the Van Allen radiation belts. The ionizing radiation can produce
additional fixed oxide charge and also additional interface states. In this short discussion
of radiation effects in MOSFETs, we will be concerned only with the permanent effects
that occur in the device characteristics.

Another source can generate oxide charge and interface states: the hot electron effect.
Electrons near the drain terminal of a MOSFET operating near avalanche breakdown can
have energies that are much larger than the thermal-equilibrium value. These hot
electrons have energies sufficient to penetrate the oxide- semiconductor barrier.

Radiation-Induced Oxide Charge

Gamma-rays or x-rays incident on semiconductor or oxide materials can interact with
valence band electrons. The incident radiation photons can impart enough energy to a
________________________________________________________________________

D. Y. Tang Page 59 3/31/08
valence electron to elevate the electron into the conduction band; an empty state or hole
is also produced in the valence band. This process generates electron hole pairs. These
newly generated electrons and holes can move through a material under the influence of
an electric field.

Figure A9 shows the energy-band diagram of an MOS device with a p-type substrate and
a positive gate voltage. The bandgap energy of silicon dioxide is approximately 9 eV.
The figure schematically shows the creation of an electron-hole pair in the oxide by
ionizing radiation. The force on the radiation-induced electron is toward the gate and the
force on the radiation-induced hole is toward the semiconductor. It has been found that
generated electrons in the oxide are fairly mobile, with a mobility value on the order of
20 cm
2
/V-s. At high electric fields, the electron velocity in the oxide also saturates at
approximately 10
7
cm/s so that the electron transit time for typical gate oxide thicknesses
is on the order of a few picoseconds. For positive gate voltages, the vast majority of
radiation-induced electrons flow out through the gate terminal; for this reason, in general
these electrons do not play a significant role in the radiation response of MOS devices.

Figure A9: Schematic of ionizing radiation-induced processes in an MOS capacitor with
a positive gate bias.

The generated holes, on the other hand, undergo a stochastic hopping transport process
through the oxide (shown schematically in Figure A9). The hole transport process is
dispersive in time and is a function of the electric field, temperature, and oxide thickness.
The effective hole mobility in silicon dioxide is typically in the range of 10
-4
to 10
-11

cm
2
/V-s; thus, holes are relatively immobile when com with electrons.

When holes reach the silicon-silicon dioxide interface, a fraction is captured in trapping
sites while the remainder flow into the silicon. A net positive radiation induced charge is
now trapped in the oxide due to these captured holes. This trapped charge can last from
hours to years. As we have seen, a positive oxide charge causes a negative shift in
threshold voltage.
________________________________________________________________________

D. Y. Tang Page 60 3/31/08
The measured areal hole trap densities are in the range of 10
12
to 10
13
cm
-2
depending
upon oxide and device processing. In general, these traps are located %k approximately
50 of the Si-SiO
2
interface. The hole trap is usually associated with a trivalent silicon
defect which has an oxygen vacancy in the SiO
2
structure. The oxygen vacancies are
located in a silicon-rich region near the Si-SiO
2
interface.

Since the threshold or flat-band voltage shift is a function of the amount of trapped
charge, the voltage shift is a function of applied voltage across the oxide. Figure A10
shows the flat-band voltage shift of an MOS capacitor as a function of gate voltage
applied during irradiation. For small values of gate voltage, some radiation-generated
holes and electrons recombine in the oxide. Hence the amount of charge reaching the Si-
Si02 interface and being trapped is less than for a large positive gate voltage, where
essentially all radiation-generated holes reach the interface without recombining with
electrons. If the fraction of generated holes that become trapped is relatively constant,
then the voltage shift becomes independent of positive gate bias, as shown in the figure.
For negative applied gate voltages, the radiation induced holes move toward the gate
terminal. There can be positive charge trapping in the oxide near the gate, but the effect
of this trapped charge on the threshold voltage is small.

Figure A10: Radiation-induced flatband voltage shift in an MOS capacitor as a function
of applied gate bias during irradiation.

One failure mechanism, therefore, caused by the radiation-induced oxide charge n an n-
channel MOSFET in an integrated circuit is a shift from enhancement mode to depletion
mode. The device will be turned on rather than off at zero gate voltage; consequently, the
circuit function may be disrupted or an excessive power supply current may be generated
in the circuit.

The gate voltage in a p-channel MOSFET is normally negative with respect to the
substrate. Radiation-generated holes in the oxide are forced to the gate-oxide interface.
The trapped charge in this region has less effect on the threshold voltage, so threshold
shifts in p-channel MOSFETs are normally smaller if the trap concentration at the gate-
oxide and oxide-semiconductor interfaces is of the same order of magnitude.

Radiation-Induced Interface States

________________________________________________________________________

D. Y. Tang Page 61 3/31/08
We have considered the effect of interface states on the C-V characteristics of an MOS
capacitor and on the MOSFET characteristics. The net charge in the interface of an n-
channel MOS device at the threshold inversion point is negative. This negative charge
will cause a shift in threshold voltage in the positive voltage dire, which is opposite to the
shift due to the positive oxide charge. In addition, since interface states can be charged,
they are another source of coulomb interaction with the inversion charge carrier, which
means that the inversion carrier mobility is a function of the interface state density
through surface- scattering effects. Interface states, then, affect both threshold voltage
and carrier mobility.

When MOS devices are exposed to ionizing radiation, additional interface states are
generated at the Si-Si02 interface. The radiation-induced interface states tend to be donor
states in the lower half of the bandgap and acceptor states in the upper half. Figure 20
shows the threshold voltage in an n-channel and a p-channel MOS as a function of
ionizing radiation dose. We initially see the negative threshold voltage shift in both
devices due to the radiation-induced positive oxide charge. The reversal in threshold shift
at the higher dose levels is attributable to the creation of radiation-induced interface states
that tend to compensate the radiation-induce positive oxide charge.

Figure A11: Threshold voltage versus total ionization radiation dose of (a) an n-channel
MOSFET, and (b) a p-Channel MOSFET.

The buildup of radiation-induced interface states occurs over a relatively long time period
and is a very strong function of the applied electric field in the oxide. Figure A12 shows
the radiation-induced interface state density versus time for several applied fields. The
final interface state density is reached between 100 to 1.000 seconds after a pulse of
ionizing radiation. Almost all models for the generation of radiation-induced interface
states depend on the transport or trapping of radiation-generated holes near the Si-Si02
interface. This transport and trapping process is time and field dependent, supporting the
time and field dependence of the interface state buildup.

________________________________________________________________________

D. Y. Tang Page 62 3/31/08

Figure A12: Radiation-induced interface state density versus time after a pulse of
ionizing radiation for several values of oxide electric field.

Interface states may seriously affect the MOSFET characteristics, which in turn -in affect
MOSFET circuit performance. Radiation-induced interface states can cause shifts in
threshold voltage, affecting circuit performance as we have discussed. A reduction in
mobility can affect the speed and output drive capability of a circuit.

Hot-Electron Charging Effects

We have considered breakdown voltage effects in a MOSFET. In particular, as the
electric field in the drain junction space charge region increases, electron-hole pairs can
be generated by impact ionization. The generated electrons tend to be swept to the drain
and generated holes swept into the substrate in an n-channel MOSFET.

Some of the electrons generated in the space charge region are attracted to the oxide due
to the electric field induced by a positive gate voltage; this effect is shown in Figure A13.
These generated electrons have energies far greater than the thermal equilibrium value
and are called hot electrons. If the electrons have energies on the order of 1.5 eV, they
may be able to tunnel into the oxide; or in some cases they may be able to overcome the
silicon oxide potential barrier and produce a gate current which may be in the range of
femtoampere (fA) (10
-15
A) or perhaps picoamA (pA) (10
-12
A). A fraction of the
electrons traveling through the oxide may be trapped, producing a net negative charge
density in the oxide. The probability of electron trapping is usually less than that of hole
trapping; but a hot-electron induced gate current may exist over a long period of time,
therefore the negative charging effect may build up. The negative oxide charge trapping
will cause positive shift in the threshold voltage. The energetic electrons, as they cross
the Si-SiO
2
interface, can generate additional interface states. The probable cause of
interface state generation is due to the breaking of silicon-hydrogen bonds - a dangling
silicon bond is produced, which acts as an interface state. The charge trapping in interface
________________________________________________________________________

D. Y. Tang Page 63 3/31/08
states causes a shift in threshold voltage, additional surface scattering, and reduced
mobility. The hole electron charging effects are continuous processes, so the device
degrades over a period of time. This degradation is obviously an undesirable effect and
may tend to limit the useful life of the device.

Figure A13: Hot carrier generation, current components, and electron injection into the
oxide.

Types of MOSFETs

So far, we have considered only one type of MOSFETs, which uses P-type substrate
(bulk) and N
+
-type source and drain layers, and needs positive voltage at the gate to turn
the MOSFET on by creating channel of electrons between the source and the drain. As
this type of MOSFET operates with N-type channel (electrons) it is referred to as an N-
channel MOSFET. It is possible to make a complementary MOSFET using an N-type
substrate (bulk) and P
+
-type source and drain layers. In this type of MOSFET, the
channel connecting the source and the drain in ON mode has to be created of holes (P-
type carriers), because of which it is called a P-channel MOSFET. The terms N-channel
and P-channel MOSFETs are frequently replaced by the shorter terms NMOS and
PMOS.

A common characteristic of the above-described N-channel and P-channel MOSFETs is
that they are in the OFF mode when no gate bias is applied. This is because there is no
channel between the source and the drain, and therefore the drain current is zero.
Consequently, these MOSFETs are classified as normally off MOSFETs. The transfer
characteristics of Fig. 36 show that the drain current appears for sufficiently large
positive gate voltages in the case of an N-channel and negative gate voltages in the case
of a P-channel MOSFET. This is because appropriate gate voltages are needed to create
the channel of electrons and holes in N-channel and P-channel MOSFETs, respectively.
As a consequence, these types of MOSFETs are also referred to as enhancement
________________________________________________________________________

D. Y. Tang Page 64 3/31/08
MOSFETs.

Fig. 36: Types of MOSFET

________________________________________________________________________

D. Y. Tang Page 65 3/31/08
MOSFETs can be created with technologically built-in channels. As no gate voltage is
needed to set these MOSFETs in the ON state, they are called normally on MOSFETs.
To turn these types of MOSFETs off, the channels have to be depleted of electrons or
holes, so they are also referred to as depletion-type MOSFETs. Figure 36 illustrates that
negative voltage is needed to stop the drain current in the case of the N-channel
MOSFET, and similarly positive voltage is needed to set the P-channel MOSFET in the
OFF state.

Defining the threshold voltage as the gate voltage at which the channel is just formed (or
depleted), we can say that the threshold voltage of the enhancement type N-channel
MOSFETs is positive, while it is negative in the case of the depletion type N-channel
MOSFETs. The situation is opposite with the P-channel MOSFETs: negative threshold
voltage in the case of the enhancement type, and positive threshold voltage in the case of
the depletion type.

The main MOSFET type is the N-channel enhancement type. The P-channel
enhancement type MOSFET is used as a complementary transistor in circuits known as
CMOS (complementary MOS) technology. The N-channel depletion-type MOSFET is
used as a kind of complementary transistor in circuits using only N-channel MOSFETs
(NMOS technology).

I. Metal-Semiconductor Contacts: Schottky Barrier Height

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Subject-NM6603: Modern Semiconductor Devices

exp , from Eq. 23 and 27 we obtain

is the actual drain current and I

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