Donmez A. - Wideband PLL System As A Clock Multiplier (2009)

Master of Science Thesis
Wideband PLL System as a Clock

Multiplier
Aylin Donmez
August 17, 2009
Wideband PLL System as a Clock
Multiplier
Master of Science Thesis
For obtaining the degree of Master of Science in Electrical Engineering
at Delft University of Technology
Aylin Donmez
August 17, 2009
Faculty of Electrical Engineering Delft University of Technology
Delft University of Technology
Copyright c _ Electrical Engineering, Delft University of Technology
All rights reserved.
DELFT UNIVERSITY OF TECHNOLOGY
DEPARTMENT OF
MICROELECTRONICS
The undersigned hereby certify that they have read and recommend to the Faculty of -
Electrical Engineering for acceptance the thesis entitled Wideband PLL System as a
Clock Multiplier by Aylin Donmez in fulllment of the requirements for the degree of
Master of Science.
Dated: August 17, 2009
Supervisors:
Prof. dr. J. Long
Ir. Gerard Lassche
Ir. Frans Sessink
Ir. Kave Kianush
Summary
In this study, the theory, design and analysis of PLL circuits are examined and a 4.9GHz
5.9GHz Wideband CMOS PLL Frequency Synthesizer is designed and implemented in IBM
65nm digital-process.
The objective of this thesis work is to understand the limitations in Wideband PLL systems
when the application frequency range extends to multiple gigahertz. This study explores the
inband noise contribution of PLL blocks and also investigates solutions to high frequency
operation of phase frequency detectors and charge pumps.
A high frequency phase-frequency detector topology is presented. With this topology, static
phase error of the loop remains close to zero even if the charge-pump has a large amount
of current mismatch. A design which is capable correct operation up to a frequency 1.74
GHz is designed. A high frequency dierential charge pump circuit with glitch suppression
is presented. The VCO of the PLL is implemented with a mutlipath loop ring oscillator.
The VCO has a better supply noise performance compared to conventional ring oscillators
but however it is still not suitable for applications with noisy supply, thus o chip supply
decoupling is used. VCO operates within 4.79GHz 6.54GHz for all process corners. The
frequency divider which is used from project library has a constant division ratio of 6.
Entire PLL design consumes 14.9 mW from 1.2 V supply, under typical conditions. Total
area of the PLL is 1 mm x 800 um including the pads.
M.Sc. thesis Aylin Donmez
ii Summary
Aylin Donmez M.Sc. thesis
Acknowledgments
The past two years I have spent at TU Delft have been a fabulous journey mostly because
of the amazing people I have met, who have been a part of it. I feel to have built a great
knowledge and perspective both in my career and social life.
First and foremost, I would like to thank my company supervisors, Gerard Lassche and Frans
Sessink whose support was always available when needed. I am grateful to Gerard Lassche
for his inestimable guidance and interest in the project. His signicant contribution during
the layout design has been a priceless support. I would like to thank Frans Sessink for his
valuable assistance on system level analysis of PLL, and his trainings on frequency domain
loop analyses in Simetrix have been informative.
I would also like to thank Kave Kianush for giving me this opportunity and sponsoring the
project. I am grateful to valuable inputs and reviews of Prof. John Long as a university
supervisor, during the design reviews.
I also wish to thank some of the other excellent engineers of Catena Microelectronics who have
shaped my point of view on various design phases. I am grateful to Koen van Hartingsveldt
for his precious guidance regarding to RF perspective of the system. I am especially thankful
to Nicole Eisenberg, Ivaylo Bakalski and Mattias Wallberg for resolving countless issues and
being excellent admins during the layout design. I would like to thank Atze van der Goot, for
providing the assistance to get my design processed. I am also thankful to Hans Rosenberg
for his support on test board design.
Words cannot express my gratitude to my dear friend Serpil Sevilay Senturk, for her constant
love, support, and understanding. I can only hope to preserve our heartfelt relationship. My
warmest thanks also go to Tuba Yilmaz, Unal Kocabas, Ibrahim Over for their support, great
friendship, and many wonderful memories. I am truly lucky to have made great friends such
as Remziye Nasuhoglu, Guner Arici, Burak Sozgen and Cigdem Demirel with whom we have
set up the innovative institution More en de Ruif that basically oers fun activities and moral
support services.
Finally, I would like to express my enormous thanks to my mother Muruvvet Donmez, my
father Ibrahim Donmez, my sister Pervin Donmez, and the rest of my family. No matter
how far away they may be physically, they are never far from my heart and mind. All my
endeavors are to deserve their boundless love and support without which I would never have
had the strength and courage to pursue my dreams, and for that I dedicate this thesis to
them.
Table of Contents
Summary i
Acknowledgments iii
1 Introduction 1
1.1 Project Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
VCO Pulling Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Response of a PLL system to VCO Pulling . . . . . . . . . . . . . . . . . 4
1.2 Report Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Background 5
2.1 WideBand PLL Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Interference Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Intrinsic Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Noise in Wideband PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.1 Phase Noise Denition . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.2 Frequency Domain Noise Analysis . . . . . . . . . . . . . . . . . . . . . 8
Input Reference Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Phase Detector Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Noise Injected to Loop by Charge Pump . . . . . . . . . . . . . . . . . . 9
Noise on Control Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VCO Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Divider Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLL Total Output Phase Noise . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Time Domain Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 Jitter Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.2 Time Domain and Frequency Domain Noise Relation . . . . . . . . . . . 18
vi Table of Contents
3 PFD & Charge Pump 19
3.1 Phase Frequency Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 Multiplier Phase-Detectors . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.2 XOR Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.3 Tri State Conventional Phase Detector . . . . . . . . . . . . . . . . . . . 22
3.1.4 High Frequency Limitations of Conventional Phase Detectors . . . . . . . 22
3.1.5 Dynamic Logic Phase Detectors . . . . . . . . . . . . . . . . . . . . . . 25
3.1.6 Phase Frequency Detector Design . . . . . . . . . . . . . . . . . . . . . 27
3.2 Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.1 Current and Pulsewidth Mismatch . . . . . . . . . . . . . . . . . . . . . 31
3.2.2 Timing Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.3 Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.4 Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.5 Clock Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.6 Charge Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.7 Charge Pump Architectures . . . . . . . . . . . . . . . . . . . . . . . . . 34
Single-ended charge pumps . . . . . . . . . . . . . . . . . . . . . . . . . 34
Dierential Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.8 Dierential Charge Pump Design . . . . . . . . . . . . . . . . . . . . . . 36
Switch Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Common Mode Feedback Circuit . . . . . . . . . . . . . . . . . . . . . . 38
Unity Gain Buer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Bias Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Glitch Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4 VCO & Divider 51
4.1 Ring Oscillator VCOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.1.1 Single Loop Ring Oscillator Design . . . . . . . . . . . . . . . . . . . . . 53
4.1.2 Multi Loop Ring Oscillator Design . . . . . . . . . . . . . . . . . . . . . 55
Odd Number of Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Even Number of Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.1.3 Loop Architecture Decision . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2 Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.1 CMOS Digital Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.2 Dierential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2.3 Delay Cell with push pull inverters (DC
1
) [12] . . . . . . . . . . . . . . . 62
4.2.4 Delay Cell with feedback control (DC
2
) [24] . . . . . . . . . . . . . . . . 64
4.2.5 Delay Cell with common mode noise rejection (DC
3
) [15] . . . . . . . . . 66
4.3 Delay Cells Performance List . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.4 Ring Oscillator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.4.1 VCO Tuning Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.5 Layout of the VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.6 Divider Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table of Contents vii
5 Top Level 77
5.1 Loop Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2 Wideband PLL Characteristics Validation . . . . . . . . . . . . . . . . . . . . . . 85
5.2.1 Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.2.2 Phase Noise Measurement and Other Design Metrics . . . . . . . . . . . 85
6 Conclusion and Recommendations 87
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
A PLL Basics 89
A.1 PLL Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
A.1.1 Loop Order and Loop Type . . . . . . . . . . . . . . . . . . . . . . . . . 90
A.1.2 Loop response to a step change in phase . . . . . . . . . . . . . . . . . . 91
A.1.3 Loop response to a step change in frequency . . . . . . . . . . . . . . . 92
Bibliography 95
viii Table of Contents
List of Figures
1.1 VCO Pulling in transceiver systems . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 LO generation from a low frequency reference . . . . . . . . . . . . . . . . . . . 2
1.3 LO generation with injection locked mixing . . . . . . . . . . . . . . . . . . . . 3
1.4 LO Generation with a PLL system . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 PLL Loop Basic Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Noise Contributers in the Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Output spectrum of an ideal oscillator . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Phase noise denition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Input reference noise contribution . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Phase frequency detector noise contribution . . . . . . . . . . . . . . . . . . . . 10
2.7 Charge pump noise contribution . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8 Control line noise contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.9 VCO noise contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10 Divider noise transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.11 Total output noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.12 Digital waveform with jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.13 Waveforms illustrating the period cycles . . . . . . . . . . . . . . . . . . . . . . 16
2.14 Edge to edge jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.15 Cycle to Cycle Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.16 k-cycle jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Ideal phase frequency detector characteristic . . . . . . . . . . . . . . . . . . . . 19
3.2 Analog Multiplier as a Phase Detector . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 Analog Multiplier Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
x List of Figures
3.4 Output Characteristic of Exor PFD . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Exor Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 Tri State Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 UPDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8 UPcharacteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9 Output Characteristic of a PFD at high frequencies [18] . . . . . . . . . . . . . 24
3.10 Waveforms during blind zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11 Architecture proposed by Johansson . . . . . . . . . . . . . . . . . . . . . . . . 25
3.12 Architecture proposed by Mansuri . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.13 Architecture proposed by Tak . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14 Output characteristic in [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Shorter delay problem in reset path . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16 Phase Frequency Detector used in this work . . . . . . . . . . . . . . . . . . . . 29
3.17 PFD output for in phase 1GHz square wave inputs . . . . . . . . . . . . . . . . 29
3.18 PFD outputs at 1GHz when the reference signal leads for 300 ps . . . . . . . . . 30
3.19 PFD Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.20 PFD Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.21 Phase Frequency Detector Layout . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.22 Charge Pump leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.23 Single ended charge pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24 Single ended charge pump architectures a)with current steering switch b)with ac-
tive output buer c)with NMOS switches only . . . . . . . . . . . . . . . . . . . 36
3.25 CPhigh speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.26 Noise voltage at charge pump output . . . . . . . . . . . . . . . . . . . . . . . . 39
3.27 Switch layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.28 Common Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.29 Transconductance of common mode loop . . . . . . . . . . . . . . . . . . . . . 41
3.30 Layouts of common mode circuit and unity gain buer . . . . . . . . . . . . . . 42
3.31 Unity gain buer used in this work . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.32 AC response for dierent input levels of UGB . . . . . . . . . . . . . . . . . . . 45
3.33 CP-Bias Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.34 Layout for CP bias block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.35 Transmission gate as a switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
List of Figures xi
3.36 Modication for Glitch Suppression . . . . . . . . . . . . . . . . . . . . . . . . 47
3.37 Charge pump Full Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.38 Complete Charge pump layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.1 Three-stage ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2 4 Stage Multi Loop Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3 3-stage ring oscillator with multi loop architecture . . . . . . . . . . . . . . . . . 55
4.4 3 stage ring oscillator 1
s
t order model . . . . . . . . . . . . . . . . . . . . . . . 56
4.5 4 stage multiple pass ring oscillator architecture . . . . . . . . . . . . . . . . . . 58
4.6 Simple Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.7 Delay Control in Dierential Gain Stages . . . . . . . . . . . . . . . . . . . . . . 61
4.8 (DC
1
) Delay Cell Proposed by [12] . . . . . . . . . . . . . . . . . . . . . . . . 63
4.9 Phase Noise of DC
1
@ 5.053GHz . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.10 Small signal equivalent model of DC
1
used to calculate PSRR [12] . . . . . . . 64
4.11 (DC
2
) Delay Cell [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.12 Phase noise of DC
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.13 Small Signal Model of DC
2
used to calculate PSRR in [24] . . . . . . . . . . . 65
4.14 Schematic of the DC
3
[15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.15 Small signal model of DC
3
for PSRR calculation . . . . . . . . . . . . . . . . . 67
4.16 Schematic and block schematic of the delay cell used in this work . . . . . . . . 69
4.17 Phase Noise performance of the delay cell used in this work 5GHz . . . . . . . . 70
4.18 Small Signal Equivalent to half circuit for PSRR calculation . . . . . . . . . . . . 71
4.19 Schematic of VCO delay cell used in this work . . . . . . . . . . . . . . . . . . . 72
4.20 VCO delay cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.21 VCO top level layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.22 Block Schematic of the divider used in this work . . . . . . . . . . . . . . . . . . 75
4.23 Jitter performance of the divider . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.24 Divider phase noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1 Loop Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2 Dierential loop lter used in this work . . . . . . . . . . . . . . . . . . . . . . . 78
5.3 Simetrix Model of the Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.4 Loop AC response in Simetrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.5 Noise Behaviour of the loop in Simetrix . . . . . . . . . . . . . . . . . . . . . . 81
xii List of Figures
5.6 Settling Behavior in Fast Corner . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.7 Top level Layout - Core Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.8 Top level layout including the pads . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.9 bonding diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.10 Loop bandwidth measurement setup . . . . . . . . . . . . . . . . . . . . . . . . 85
A.1 Basic phase-locked loop block diagram . . . . . . . . . . . . . . . . . . . . . . . 89
A.2 Loop lter with stabilization zero . . . . . . . . . . . . . . . . . . . . . . . . . . 90
List of Tables
3.1 UGB transistor sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 UGB transistor sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3 Bias Block transistor sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1 Comparison of performance metrics of delay cells . . . . . . . . . . . . . . . . . 68
4.2 VCO Tuning Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.1 PLL Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
xiv List of Symbols
Chapter 1
Introduction
In this work a Wideband PLL system is proposed to reduce the eects of the voltage controlled
oscillator, V CO, pulling in zero-IF and low-IF wireless transceiver systems. The system is
consist of a phase frequency detector, PFD and a charge pump, CP, which are capable
high frequency operation. A dierential loop lter, a xed divide-by-6 divider and a ring
oscillator which is implemented with a novel architecture of multipath conguration are other
components of the system. Wideband PLL is fabricated in a standard CMOS IBM 65nm
process, and is ecient with respect to its die area.
1.1 Project Description
In transceiver systems, both zero IF and low IF transceivers, VCO frequency is the same as
the antenna frequency. This causes the generally known problem, VCO pulling [21] due to
the coupling of RF input signal or the power amplier signal into oscillator. An oscillator
under injection pulling starts oscillating at the injected signals frequency depending on the
injected amplitude. This eect is strongly dependent on the injected signals amplitude and
the frequency oset from the VCO free running frequency.
Two mechanism can be listed as the cause to VCO pulling a given in Figure 1.1;
Transmitted signal may couple to VCO, through a parasitic path.
A similar mechanism occurs when the supply voltage of the oscillator varies. For ex-
ample, in a transceiver system where the power amplier is switched ON & OFF, due
to the nite output impedance of the supply source, supply voltage includes harmonics
from the switching frequency of the PA [21].
Receiver signal may include strong inband interferers which are amplied by the LNA
and may couple to VCO.
When the interferer frequency is close to the LO frequency coupling through the mixer
may pull VCO frequency to interferer frequency. With a buer between VCO and mixer
would increase the reverse isolation and reduce the pulling eect.
2 Introduction
(a) PA leakage to VCO
(b) Large interferer at input
Figure 1.1: VCO Pulling in transceiver systems
VCO Pulling Avoidance
In transceiver systems, VCO central frequency may shift to an undesired frequency due to the
leakage from parasitic paths, or coupling of PA signal to VCO through the bulky inductors
used in VCO, as previously explained. Due to the integer relation between the PA output
frequency and the VCO frequency, this pulling eect increases. There are several options for
LO generation in transceiver systems;
Figure 1.2: LO generation from a low frequency reference
In zero IF transceivers, generally the local oscillator of the transceiver is designed to
operate at RF frequency, f
RF
. Thus the RF spectrum is directly transferred into the
baseband. This architecture relaxes the requirements on IF lter, it is now consist of
1.1 Project Description 3
a low pass lter since the information band after mixing is at baseband. However,
it is clear that such an architecture is more susceptible to 1/f noise and DC osets.
Moreover, in such an architecture, since PA frequency and VCO frequency is designed to
be same, any leakage from transmitted signal to VCO is double mixed with the received
signal leading to pollution of the information band. This eect is generally regarded as
cross talk and it is undesirable.
In some architectures, the local oscillator of the transceiver is designed to operate at
2 f
LO
. It is followed by a quadrature divide by 2 block in order to perform image
rejection. The coupling eect of PA to VCO resonator is then reduced, however 2nd
harmonic of transmitted signal still couples to VCO and receiver suers from pulling
eects.
Another solution would be the implementation of a low frequency VCO followed by
a frequency multiplier as given in Figure 1.2. This frequency multiplication can be
performed with an injection locked divider and a mixer as illustrated in Figure 1.3.
This conguration allows the usage of an LO frequency that has a non integer relation
between the PA frequency. However, main draw back of this system is the spurious
components produced after mixing.
Figure 1.3: LO generation with injection locked mixing
Alternatively, a PLL loop could be a candidate for a system. Reference oscillator which
could be implemented with an LC oscillator runs at a lower frequency and the LO
frequency is generated by a PLL loop. VCO of the PLL loop can be implemented with
a simple ring oscillator.
Figure 1.4: LO Generation with a PLL system
4 Introduction
Response of a PLL system to VCO Pulling
As a negative feedback control system, PLL would try to compensate for the phase error at
the output of the PLL phase detector. Thus, PLL responds to any phase-frequency changes.
However, the rate of change in phase-frequency is also important since there exist a limit
in phase-frequency change that drives the loop out of stability. Brief explanation on this
limitation is given in Appendix A.
Depending on the frequency oset of the injected signal, PLL sensitivity to the injected signal
also changes. Since the PLL suppresses the eect of the injection within the PLL bandwidth,
the injection eects within PLL bandwidth reduce.
A wideband PLL system oers a solution to VCO pulling from two perspectives; Firstly, The
non integer relation between the reference VCO and the transmitter frequency reduces the
pulling. Secondly, because of the wide loop bandwidth the injection pulling is also suppressed.
1.2 Report Outline
The goal of this thesis is to review the theory, design and analysis of PLL circuits and complete
a detailed design of a 4.9 5.9 GHz Wideband CMOS PLL Frequency Synthesizer.
Chapter 2 presents the noise fundamentals of PLLs and explains how noise is dened both
in time and frequency domains. Transfer functions are derived to calculate the output noise
contribution of the loop components. Relation between time domain and frequency domain
analysis is also given briey.
Chapter 3 concentrates on the phase frequency detector and charge pump design up to their
nal phase; layout extraction. In this chapter, high frequency operation of these components
are explained, and techniques that oer a solution to problems that occur from high frequency
operation, are described.
Chapter 4 discusses the methods of high frequency operation in ring oscillators. Frequency
improvement in multi loop architectures are investigated and gain stages that can be used
in multiloop conguration are identied. Since the gain of ring VCOs, K
V CO
, is suciently
high, techniques to reduce K
V CO
are derived. Layout limitations on operating frequency of
the VCO are also given in this chapter.
Chapter 5 is a review of overall performance of the Wideband PLL. It explains how the
stability of the loop is satised for all the operating range. Top level layout routings are also
explained in this chapter.
Chapter 6 is a review of the thesis, conclusions and recommendations are given.
Chapter 2
Background
2.1 WideBand PLL Basics
A phase locked loop is a feedback system that functions on the phase dierences of its two
periodic inputs. This property of a PLL system is the basic distinction from other feedback
systems where the change in voltage or current magnitudes is of importance. In a simple
PLL loop phase frequency detector, PFD, produces output that carries the information on
the excess phase of the PLL inputs. Charge pump, CP, supplies the required current, based
on the phase frequency detector output. CP current is converted into voltage by means of
the loop lter impedance. Loop lter has always a low pass characteristic and high frequency
components in the control voltage are ltered out by the loop lter.
Figure 2.1: PLL Loop Basic Components
The loop is considered to be locked when the excess phase is constant with the time. In
wideband PLLs main concern is the high frequency limitations of the PFD and CP. Phase
frequency detector is possibly congured based on either a mixing function or sequential
logic. The frequency divider in the loop divides the output frequency by N, division ratio,
thus produces an input signal to phase frequency detector. Since frequency is the derivative of
phase, output phase is also divided by N. As a result, when the loop is locked below relation
is valid for input
IN
and output phase
OUT
;
IN
=
1
N
OUT
6 Background
IN
=

IN
=
1
N
OUT
=
1
N
OUT
OUT
= N
IN
Detailed information on loop dynamics can be found in Appendix A.
2.2 Noise
2.2.1 Interference Noise
Interference noise is mainly caused by the undesirable interaction between the circuit blocks
in a system-on-chip architecture. In many chips all of the clocks and events are harmonically
related to each other thus interference noise may be regarded as cyclostationary in its nature
[3]. Power supply noise or electromagnetic interference between wires are the two most com-
mon sources of the interference noise. This kind of noise can be reduced down to a signicant
extent by a careful layout techniques.
2.2.2 Intrinsic Noise
Intrinsic noise is mainly originated from the elemental properties of devices and circuits. In
contrast to interference noise, intrinsic noise refers to random noise signals that can be reduced
but never eliminated. Here, a brief descriptions of electronic components is given.
Resistors produce a type of noise, called thermal noise. It is originated by kinetic energy
gained by the free charge carriers [26]. Thermal energy causes carriers to move randomly
instead of following polarities.
Diodes produce a type of noise called shot noise. The diusion mechanism in diodes is the
origin of this type of noise. The displacement of individual carriers is a random process, there
occurs slight uctuations across the junction. It has a white power spectral density.
MOS Transistor operates as a gate modulated resistance between the source and drain area.
Thus its noise is mainly thermal origin.
2.3 Noise in Wideband PLLs
Output spectrum of an oscillator is basically determined by the transfer functions of each block
to output. Thus, PLL response to noise contributions of each block is greatly important. In
Wideband PLLs, phase noise of oscillators and charge pump are critical issues that basically
determine the system performances. PLL inband noise is dominated by charge pump while
the vco has considerable superiority in the noise outside the loop bandwidth. The response
of a PLL system to abrupt phase changes, non idealities such that spurious peaks, noise etc.
shall be well characterized.
Location of various signal noise sources are seen in Figure 2.2. Analysis of PLL noise transfer
functions reveals more insight on the noise shaping eect of PLL loop.
2.3 Noise in Wideband PLLs 7
Figure 2.2: Noise Contributers in the Loop
2.3.1 Phase Noise Denition
The most desirable specication of any type of oscillator is its spectral purity. An ideal
oscillator has an impulse in its spectrum at its oscillation frequency,
O
. However, in most
practical applications total power of such an oscillator is distributed over its harmonics (i.e.
2
O
, 3
O
, 4
O
...) as shown in Figure 2.3. Thus, instantaneous output wave expression for a
practical oscillator can be given as;
V (t) = V
o
+A
0
(t) sin(
O
t +(t))
+ A
1
(t) sin(2
O
t +(t))
+ A
2
(t) sin(3
O
t +(t))
+ higher order harmonics (2.1)
where A(t) and (t) are the expressions for the amplitude and phase uctuations. Two
dierent types of non ideality terms appear at the output spectrum of a practical oscillator;
Random phase uctuations, are basically originated from the internal noise compo-
nents of the oscillator, such as 1/f noise, shot noise. Internal noise sources, being random
in nature, set a natural limit to the minimum attainable phase noise performance. It is
measured as the random phase uctuations at zero crossings of the signal.
Spurious tones or signals, are distinct components in the spectrum and they are
generally considered as interferers. These external noise sources are deterministic and
they do not have a direct relation with the oscillator spectrum. Tones in power supply,
tones in control voltage of oscillator or clock signals coupled via bias current appear in
oscillator output spectrum and appoint a critical specication for the PLL system.
As seen in Figure 2.3 these phase noise components have dierent amplitude behavior. Typ-
ically phase noise is dened as the ratio of noise power in 1 Hz bandwidth at an oset, f
m
,
to the total signal power, as shown in Figure 2.4. Thus, single side band, (SSB), phase noise
is specied in dBc/Hz,(dB relative to the carrier) at a given frequency oset as;
L(f
m
) =10log
_
P
NOISE
(f
m
)
P
SIGNAL
_
8 Background
Figure 2.3: Output spectrum of an ideal oscillator
Figure 2.4: Phase noise denition
2.3.2 Frequency Domain Noise Analysis
In the linear noise model of the PLL loop given in Figure 2.2,
ref
stands for the noise that
appears at the reference input to the PFD and it has the form rad/
Hz. It is comprised of
the noise components such as reference crystal oscillator, crystal buer and reference divider
if available.
div
represents the output noise of divider in rad/
Hz.
vco
is the phase noise
of the free running oscillator, it is also expressed in rad/
Hz.
pfd
is the noise of the phase
frequency detector that appears at PFD output.
n,cnt
is the noise voltage at VCO control
line in consequence of loop lter noise or any noise sources coupled to control line.
n,cnt
is expressed in V/
Hz. i
n,cp
represents the noise current of charge pump and has a unit
of A/
Hz. Noise contribution of each block are studied separately here that other noise
contributions are assumed to be zero while calculating contribution of one block.
Input Reference Noise
Input reference noise is one of dominant noise sources in a PLL loop. For the cases that input
signal is not a pure sinusoid i.e. input phase varies with time, transfer function of excess
phase from reference input to VCO output is given as in Equation-2.2;
H
ref
(s) =

out
(s)
ref
(s)
=
F(s) K
pfd
K
vco
s
1 +F(s) K
pfd
K
vco
Ns
(2.2)
For any type of loop lter, F(s), as input phase varies very slowly, i.e. as s 0, H
ref
N,
transfer function converges to a constant, N, division ratio. And for innitely fast changes
transfer function converges to 0 indicating that PLL system does not respond to high fre-
quency inputs. As a result noise from reference input has a low pass characteristic. Thus,
H
ref
corresponds to low pass ltering of the reference noise multiplied by the division ratio,
N.
(a) Input reference noise (b) Transfer function of reference
input
(c) Total reference noise appear-
ing at output
Figure 2.5: Input reference noise contribution
Power spectral density of the reference phase noise contribution is given in Figure ??. In this
gure, loop lter is supposed to have a single pole and a stabilization zero. Reference noise
only has
1
f
2
component which is practically not the case. For low frequencies, output power
spectrum has the same slope with the input reference power spectrum, however its magnitude
is multiplied by N
2
. At cuto frequency additional slope of 20dB/dec is introduced by the
loop lter.
Phase Detector Noise
Phase detector noise is generally much smaller than the reference noise and in most cases it is
skipped in calculations. Phase Detector of the PLL loop exhibits the transfer function given
with Equation 2.3.
H
pfd
(s) =

out
(s)
pfd
(s)
=
F(s)
K
vco
s
1 +F(s) K
pfd
K
vco
Ns
(2.3)
Disregarding of the loop lter type, for frequencies close to 0, s 0, transfer function
converges to
N
K
pfd
. This result means that for low frequencies phase detectors noise magnitude
appears at the output of PLL with multiplied by
N
K
pfd
.
For frequencies s , transfer function goes to 0 with 20dB slope meaning that outside
the loop bandwidth phase detectors noise is not dominant contributer to VCO output noise,
which is a sensible result. PLL loop responds to PFD noise in the same way as reference
input. Only the magnitude of transfer function at low frequencies is now
N
K
pfd
.
Noise Injected to Loop by Charge Pump
For a practical PLL system, when the loop is locked the average current transfer to the loop
is zero. However, charge pump noise current is injected to the loop lter during the non zero
UP & DN pulse widths. Charge pump noise current can be calculated as in Equation 2.4.
10 Background
(a) Phase frequency detector
noise
(b) Transfer function of PFD (c) Total phase detector noise ap-
pearing at output
Figure 2.6: Phase frequency detector noise contribution
i
2
n
cp
= 2

dz
T
ref
I
2
CP,noise
(2.4)
where I
CP,noise
stands for the total current noise density of the charge pump in A/
Hz.
dz
is the duration of the UP & DN pulse widths during the lock condition. Factor of 2 refers
to the noise contributions of both UP & DN pulses. T
ref
is the period of the reference input
signal. The magnitude of charge pump current noise power density i
2
n
CP
is proportional to the
duty cycle of the charge pump and the frequency of the reference input as seen in Equation
2.4. Thus, for high frequencies, switching of the UP & DN current sources becomes more
critical.
Charge pump of the PLL loop exhibits the transfer function given with Equation 2.5.
H
CP
(s) =

out
(s)
i
n
cp
(s)
=
2
I
CP
F(s) K
pfd
K
vco
s
1 +F(s) K
pfd
K
vco
Ns
(2.5)
Here noise current of charge pump is assumed to be white. For frequencies s 0, transfer
function converges to;
20log(
2N
I
CP
)
Magnitude of low frequency noise contribution of charge pump current is multiplied by
20log(
2N
I
CP
). For frequencies higher than the loop bandwidth, transfer function has a 20dB
of slope and goes to 0. As a result, it can be concluded that charge pump noise is dominant
within the loop bandwidth and its contribution is negligible outside the loop bandwidth.
In a practical charge pump circuit, non ideal eects such as leakage currents, magnitude
mismatch between UP & DN currents or switching time mismatch between UP & DN currents
are critical in reference spur calculation. However, they are not critical issues in CP noise
contribution as Equation 2.4 adequately includes the parameters that control CP noise.
(a) Charge pump noise (b) Transfer function of CP
(c) Total charge pump noise ap-
pearing at output
Figure 2.7: Charge pump noise contribution
Noise on Control Line
Thermal noise originated from the loop lters resistance, power supply noise coupled to
control line or voltage buer used in control line contributes to total PLL output noise.
These contributors are investigated here in details.
Loop Filter Noise
Low pass lter of the PLL loop exhibits the transfer function given with Equation 2.6.
H
lpf
(s) =

out
(s)
lpf
(s)
=
K
vco
s
1 +F(s) K
pfd
K
vco
Ns
(2.6)
It is interesting that loop lters noise transfer function is dependent on the type of the
low pass lter. In case the loop is a 1
st
order, i.e F(s) = 1 the transfer function has a
low pass characteristic as seen in Equation 2.7.
For F(s) = 1
H
lpf
(s) =

out
(s)
lpf
(s)
=
K
vco
s +
K
pfd
K
vco
N
(2.7)
However, if the lter has a zero and a pole,i.e.;
12 Background
F(s) =
1+s
1
s
2
transfer function characteristic becomes band pass. The closed loop noise power density
contribution of loop lter to output is then given in Figure 2.8;
(a) Loop Filter noise voltage (b) Closed loop transfer function of loop l-
ter
(c) Total loop lter noise appearing at out-
put
Figure 2.8: Control line noise contribution
H
lpf
(s) is the bode plot of the noise transfer function and only the thermal noise of
loop lter resistance is taken into account. However if loop lter is implemented in an
active conguration, it is likely that active part of the circuit contributes to the output
noise of the loop lter as well.
Power Supply Noise Transfer through VCO Control Line In a PLL system the
magnitude of phase noise, i.e., the amount of jitter is strongly dependent of the power
supply voltage. It is generally assumed that the maximum supply voltage variation is
10% percent.
An oscillator under power supply noise interference, can be regarded as a voltage con-
trolled oscillator that has power supply as control input. Its dependence on V
dd
is
considered as supply sensitivity or supply gain. This gain is measured easily by observ-
ing the output frequency spectrum of VCO while the actual control inputs are zero. If
this gain is expressed as K
vdd
, phase noise induced by power supply noise can be given
as in Equation 2.8 [6];
S
vdd
(s) =
K
2
vdd
f
2
S
N
vdd
(s)
(2.8)
Oscillator phase noise due to impulsive supply noise;
H
vdd
(s) =

out
(s)
vdd
(s)
=
K
vco
s
1 +F(s) K
pfd
K
vco
Ns
(2.9)
The resulting supply noise transfer function is pretty similar to the H
lpf
and it has a
bandpass lter characteristic as shown in Figure 2.8. Thus its low frequency components
are rejected by the loop [3].
VCO Noise
Another noise source, in fact the dominant noise in the band of interest, is VCO phase noise
and can be modeled by transfer function given in Equation 2.10;
H
vco
(s) =

out
(s)
vco
(s)
=
1
1 +F(s) K
pfd
K
vco
Ns
(2.10)
For any type of loop lter, F(s), as s 0, H
vco
= 0, and as s , H
vco
= 1. When the
loop lter has a zero and a pole, i.e. ;
F(s) =
1+s
1
s
2
it can easily be seen that transfer function has two zeros at the origin realizing a high pass
characteristic with +40dB/dec slope for low frequencies. The zeros at the origin acquires
that for small changes of
vco
, output phase noise is negligibly small. When the PLL loop
is locked, excess phase of VCO is sensed and converted into voltage via PFD, CP and loop
lter path. Thus the voltage variations on the control line compensates for the small phase
variations in VCO performing a negative feedback.
(a) VCO open loop noise (b) Transfer function of VCO (c) Total VCO noise appearing
at output
Figure 2.9: VCO noise contribution
For very fast changes of input phase VCO phase noise is transferred to output with a gain
of 1. This property reveals an interesting conclusion that phase noise of VCO is subject to
integration.
14 Background
One basic solution is increasing the loop bandwidth of PLL system i.e. lowering the lock time
of PLL; however this would cause the low pass lter response to higher frequencies leading
more instable VCO control voltage.
The loop bandwidth should be as larger as possible, in order to minimize the output phase
noise due to the VCO intrinsic phase noise. On the other hand, it is essential to keep the loop
bandwidth smaller than the reference signal in order to keep the loop stable and suppress the
reference spurs.There is a strict trade o on keeping the in-band phase noise minimum and
retaining the spurious levels.
Divider Noise
Frequency divider of the PLL loop theoretically converts the high input frequency to lower
frequencies by a factor of the division ratio. This division ratio may be integer or fractional
based on the application. Modeling the noise of frequency divider of the PLL is mode critical
than the other blocks in the loop [14]. This is mainly because the condition that dividers are
generally followed by blocks that are sensitive to the threshold crossings of the divider output
signal. This reveals an interesting property that overall noise behavior of the PLL loop is
aected by the divider only during the threshold crossings.
Divider of the PLL loop exhibits the transfer function given with Equation 2.11.
H
div
=

out
(s)
div
(s)
=
F(s) K
pfd
K
vco
s
1 +F(s) K
pfd
K
vco
Ns
(2.11)
It has the same transfer function as the reference signal. This is an expected result, because
it is one of the two inputs of the phase-detector. For any loop lter F(s), H
div
(s) = N for
s=0, and H
div
(s) = 0 for s = .
(a) Divider Open Loop Noise (b) Transfer Function of Divider (c) Total divider noise appearing
at output
Figure 2.10: Divider noise transfer function
Intrinsic noise contribution of divider generally has a at spectrum, white noise oor, except
from the 1/f, icker noise eect [14]. Ignoring the 1/f components, the transfer function
H
div
corresponds to a low pass ltering of the divider noise multiplied by N as given in Figure
2.10. As a result, noise from the divider has a low pass characteristic.
2.4 Time Domain Noise Analysis 15
PLL Total Output Phase Noise
Phase noise contribution of each block to the output in a PLL is already calculated in above
sections. Overall PLL phase noise is achieved by using the Equation 2.12.
S
out
(f) = S
ref
(f) [H
ref
(j2f)[
2
+S
pfd
(f) [H
pfd
(j2f)[
2
+S
i
n
cp
(f) [H
CP
(j2f)[
2
+ S
lpf
(f) [H
lpf
(j2f)[
2
+S
vdd
(f) [H
vdd
(j2f)[
2
+S
vco
(f) [H
vco
(j2f)[
2
+ S
div
(f) [H
div
(j2f)[
2
(2.12)
Observation of Equation 2.12 shows that at low frequencies, the reference signal, the phase-
detector, the loop lter and the divider are the signicant noise contributors within the
bandwidth of the PLL. At oset frequencies higher than the PLL bandwidth, the phase noise
of the PLL is approximately dominated by VCO.
Figure 2.11: Total output noise
In order to minimize the reference noise contribution, the loop bandwidth must be set to
smaller values as possible. However, in this case acquisition time increases, acquisition range
decreases and the stability degrades. To minimize the VCO noise contribution at high fre-
quencies, the loop bandwidth must be maximized. In this case, acquisition time is decreased,
acquisition range is increased and stability is improved. In applications where the input has
negligible noise, like a crystal oscillator, the loop bandwidth is maximized for an improved
performance.
2.4 Time Domain Noise Analysis
Noise sources such as thermal noise, frequency modulation (FM), amplitude modulation
(AM), phase modulation (PM), and spurious components that are produced by the system
contribute to total noise that causes jitter in the clock signal and this total noise is accepted
as a general measure in calculation of jitter.
Jitter is the instantaneous variations in the phase of a signal that causes the signal deviate
from the ideal position. In a PLL system this momentary variations can be observed as the
16 Background
time variations in zero crossings of the signal. The expected crossings in a signal never occur
exactly where desired as given in Figure 2.12. Dening and measuring the timing accuracy of
those crossings (jitter) is a critical measure of the performance of communication systems.
Figure 2.12: Digital waveform with jitter
In a system where the blocks are generally driven by square wave signals, it is more convenient
to express the noise in terms of jitter. To draw a complete picture of jitter control mechanism,
jitter metrics have to be well dened.
2.4.1 Jitter Metrics
Transitions of any type of periodic signal can be expressed as the sequence of positive edge
threshold crossings,
i
. Ideally, for a noise-free signal, the following condition should be
valid for all cases ;
i
= iT where T represents the period of the signal. When the clock signal
is noisy,
i
can be given in a statistical form as
i
= iT +
i
.
Figure 2.13: Waveforms illustrating the period cycles
Edge to Edge jitter
J
ee
is a measure of jitter as the dierence between the threshold crossings of noise free
reference trigger and its response [14]. In other words it is the delay variations of input
and output of a driven block under a noise free reference input assumption. J
ee
is an
input referred jitter metric dened only for the driven systems such as phase frequency
detectors, dividers or clock buers. Since a xed noise free reference signal is assumed,
2.4 Time Domain Noise Analysis 17
J
ee
can not be used for autonomous systems such as VCOs. J
ee
is illustrated in Figure
2.14.
Thus edge to edge jitter is given as;
J
2
ee
(i) = var(
i
iT) = var(
i
) = var(
i
) (2.13)
Figure 2.14: Edge to edge jitter
Cycle to cycle jitter
Cycle to cycle jitter is the probability distribution of dierences in the period length
of adjacent clock cycles [14]. For calculation of cycle to cycle jitter, a new form for
sequence period is considered as T
i
=
i+1
i
. J
cc
is calculated as;
J
2
cc
(i) = var(T
i+1
T
i
) (2.14)
J
cc
is a measure for short term jitter and it is used for both driven and autonomous
Figure 2.15: Cycle to Cycle Jitter
systems.
K-cycle jitter
K cycle jitter is the standard deviation of k cycles,
i+k
i
, in a periodic signal. It is a
measure of uncertainty in the length of k cycles and expressed in time units [14]. For
k=1, J
1
stands for the standard deviation of a single period, and often represents the
period jitter.
J
2
k
(i) = var(
i+k
i
) (2.15)
Figure 2.16: k-cycle jitter
18 Background
2.4.2 Time Domain and Frequency Domain Noise Relation
Phase noise is a continuous stochastic process modeling the random changes in the phase of
periodic signal that has a constant frequency while jitter arises from the uncertainty at the
sampling point of a periodic signal [14]. These two concepts are dierent in their nature and
the relationship between two is not obvious.
However, if two noise domains can be separately analyzed and can be related to each other by
means of noise power denition in each domain, simplied relationship between two domains
can be obtained.
Noise power in frequency domain can be given as the integral of all noise components over a
frequency range from 0 as;
P
AV
=
_

0
S
(f)df (2.16)
where average noise power in time domain is given as;
P
AV
=
2
(2.17)
As a result, the relation between two domain noise analysis becomes;
=
_

0
S
(f)df (2.18)
Detailed derivations can be found in [14].
Chapter 3
PFD & Charge Pump
3.1 Phase Frequency Detectors
Phase-detectors are the circuit blocks of PLL systems that are a type of comparator providing
a DC output signal proportional to the input phase dierence between two input signals,
REF

DIV
=
ERR
. This error signal is produced through PLL loops feedback system.
This may be written as in Equation 3.1.
V
D
= K
PFD
ERR
(3.1)
where V
D
is the average output voltage,
ERR
is the phase dierence between the input signals
and K
PFD
is the phase-detector gain in volts per radian, V/rad.
In ideal case output voltage is linearly dependent on the input phase dierence as seen in
Figure 3.1. However, in practice the response of the phase-detectors is generally nonlinear
and repeats in a cyclic fashion over a limited phase range. The response is usually linear
in a narrow phase range close to the point at which the loop will normally lock, and the
slope of the characteristic in this range gives the phase-detector gain K
PFD
. Phase frequency
detectors can be grouped into two as; multiplier and sequential phase detectors.
Figure 3.1: Ideal phase frequency detector characteristic
20 PFD & Charge Pump
3.1.1 Multiplier Phase-Detectors
Multiplier phase-detectors rely on the DC component that results when multiplying two
alternating input signals. The input signals are mostly sinusoidal for this type of phase-
detectors and the DC component at the output is dependent on the phase dierence between
the inputs. The simplest example of a multiplier type phase-detector is the analog multiplier
of Figure 3.2. This multiplier block usually consists of a double-balanced mixer or four
Figure 3.2: Analog Multiplier as a Phase Detector
quadrant multiplier that performs the multiplication operation of the input signals. Phase
detection behavior of a simple analog multiplier can easily be understood from considering
two input signals x
1
(t) = A
1
cos(
1
t +
1
) and x
2
(t) = A
2
cos(
2
t +
2
). Multiplication result
from these two signals can be given as in Equation 3.2;
V
D
= K x
1
(t) x
1
(t)
=
KA
1
A
2
2
cos [(
1
2
)t + (
1
2
)] + cos [(
1
+
2
)t + (
1
+
2
)] (3.2)
When two input signals are equal in frequencies, i.e.
1
=
2
, output component becomes
a DC term that is proportional to the phase dierence of the input signals. In Figure 3.3,
output voltage with respect to the input phase dierence is given.
Figure 3.3: Analog Multiplier Output
Gain of such characteristic is given by the derivative of its output voltage with respect to the
input phase dierence as below;
K
PFD
=
V
D
ERR
=

ERR
_
KA
1
A
2
2
cos
ERR
_
=
KA
1
A
2
2
sin
ERR
(3.3)
3.1 Phase Frequency Detectors 21
This function is periodic with the phase error. Phase detectors gain is zero when phase error
zero and it is maximum when the phase error 90
o
and equal to the maximum output voltage
of multiplier. and phase detector gain varies sinusoidally with the phase dierence. When
the output voltage is zero, i.e. the phase dierence between input signals is 90
o
, locking in
multiplier type phase detectors can be considered as quadrature phase detector.
Thus the loop locks for a phase dierence of 90
o
producing zero output. This makes the useful
phase detection range to be limited by /1.
As
ERR
departs from 90
o
, the slope of cos
ERR
and hence the equivalent K
PFD
decreases.
Also K
PFD
is a function of input signal amplitudes, A
1
and A
2
, which is an undesirable
attribute, because a PLL employing such a phase-detector exhibits amplitude dependent
static and dynamic behavior.
Another disadvantage of multiplier-type phase-detectors is, they produce zero DC out-
put when the input signal frequencies are dierent,
1
,=
1
. As a result, the ac-
quisition performance of the loop depends on how much the dierence component at
=
1
,=
1
is passed by the loop-lter.
3.1.2 XOR Phase Detector
Similar operation principle is useful in explanation of XOR phase detectors. XOR component
may be considered as an overdriven analog multiplier. However, in this case output voltage
is not a function of input signal amplitudes since the output swing is between logic levels,
ground and supply voltage, V
DD
.
Figure 3.4: Output Characteristic of Exor PFD
Output characteristic of XOR gate with respect to its input phase oset is given in Figure
3.4. Since the output voltage of an XOR phase-detector varies between the two logic levels, a
DC oset equal to the mean of logic 1 and logic 0 levels, V DD/2, needs to be provided at the
loop-lter for the detector to function correctly [21]. In other words, XOR phase-detectors
also lock for a static phase error of 90
0
, at the middle of the linear range, which is /2 rads.
The phase-detector gain is;
K
PFD
=
V
DD
(3.4)
On the other hand, XOR produces output voltage on both rising and falling edges of the
input signals, thus the output signal has double frequency component as seen in Figure 3.5.
Figure 3.5: Exor Output Waveforms
3.1.3 Tri State Conventional Phase Detector
A Tri State conventional phase detector is consist of two D type ip ops and an AND gate for
reset path. Output of the block takes one of the values from (0,0),(0,1),(1,0),(1,1). However
during the state (0,0), the PFD does not respond to any input signal. Thus ip ops have to
be reset after a certain reset delay time.
Figure 3.6: Tri State Phase Frequency Detector
At the rising edge of REF, U signal is activated and kept high till reset. At the rising of DIV,
D signal is activated and it is kept high till reset comes. The dierence is phase/frequency of
the input signal corresponds to the dierence of U and D signals high duration.
Thus if the reference input leads the divider output, mean value of U signal becomes the term
that is proportional to the phase dierence while D signal is logic 0. Opposite is also valid for
divider leading the reference. The dierence between the mean values of the output signals
determines the phase detectors gain characteristic which is given in Figure 3.8. The amount
of gain is given by;
K
PFD
=
V
DD
2
(3.5)
3.1.4 High Frequency Limitations of Conventional Phase Detectors
Operation of a conventional phase frequency detector is explained in previous sections. Rising
edge of reference signal sets the output U high. Following rising edge of divider output sets
Figure 3.7: UPDN
Figure 3.8: UPcharacteristic
the D signal high thus creating a reset pulse at the output of the AND gate. This pulse
resets both of the outputs to zero. When both outputs are set to low, the reset pulse also
is inverted so that the circuit is made ready for following transitions. Certain gate delays of
the transistors and the delay of the AND gate used in reset path determines a certain time
interval, R, for the reset operation.
Thus the output signals are kept high during a certain time interval which is dened as reset
delay, R. This time interval, that is required to make the circuit ready for next transitions,
puts some limitations to the maximum operation frequency.
Figure 3.9: Output Characteristic of a PFD at high frequencies [18]
Figure 3.9 shows the characteristic of a phase frequency at high frequencies. During the time
interval t
REF
R, t
REF
, where t
REF
is dened as the period of reference signal, the phase
detector is not ready for new transitions. Thus the rising edge of reference or divider clock
is lost. Solid line in Figure 3.9 corresponds to the output characteristic when the time delay,
R, equals to .
With such a phase frequency characteristic, loops lock to a phase dierence of 0
o
and the
linear range that gain is constant becomes . Generalized input phase dierence range can
be given as 2(1 R/t
REF
). Thus the detection range becomes inversely proportional
to the input frequencies. As the reference frequency increases, assuming the reset delay
constant, detection range degrades considerably.
Waveforms in Figure 3.10 show the case that is likely to happen during the reset delay. During
the interval that both outputs and reset signal are activated, new transition of reference is
ignored and after reset pulse ends divider signal activates the D pulse thus making the mean
dierence of output voltage negative although the reference frequency is higher. This phe-
nomenon causes a negative output voltage during t
REF
R, t
REF
, that is demonstrated
in Figure 3.10.
On the other hand, this time interval range t
REF
R, t
REF
may be considered as blind
zone. During this zone phase detector outputs wrongly. This wrong output voltage increases
locking time. During the loop settling the frequency would lose lock since the PFD produces
wrong output signals periodically. With increasing reference frequency, settling of PLL in-
creases.It can be concluded that, during the time interval t
REF
R, t
REF
conventional
PFD loses edges and the following input sets the output to a negative voltage.
Figure 3.10: Waveforms during blind zone
3.1.5 Dynamic Logic Phase Detectors
In case D type ip ops are implemented in a true state pre-charge, TSPC, dynamic logic,
it may easily be expected that operation frequency increases remarkably. Basic property
that allows high frequency operation with dynamic logic is simplicity of ip op circuit thus
reduced the number of gate delays.
There are many applications of dynamic phase frequency detectors available in literature as in
[10]. Here few of them are generally discussed and compared from their operating frequency,
linear input range, power consumption, jitter production perspectives.
Figure 3.11: Architecture proposed by Johansson
Simple precharged phase frequency detector of [13] which is given in Figure 3.11, makes
use of one clocked inverter for phase detection and one normal inverter to produce output
thus the delay between the reference input and U signal, i.e., intrinsic ip op delay becomes
t
INV
+t
INV
C
, where t
INV
is the delay of a single inverter and t
INV
C
is the delay of a clocked
inverter. However main drawbacks of such a phase detector are;
Its output voltages are both active during the lock of the system. This property requires
a perfect matching in sink and source current sources of the charge pump.
Since the output is produced with rising edge of input signal and kept constant during
high level of input, deviation from 50 duty cycle degrades the performance.
Linear range is limited within .
Architecture of Figure 3.12, proposed in [17] nds a solution to the improvement of the linear
range by preventing phase detector produce wrong output signals during t
REF
R, t
REF
.
Figure 3.12: Architecture proposed by Mansuri
This is achieved by making use of two inverter based latch structures. Output signal is made
level sensitive to the input reference signal, thus even the rising edge is lost, phase detector is
capable of producing correct output signals with improved input phase range. PFD output
becomes high at the end of reset output signal width stays constant i.e. gain of PFD saturates
for phase dierences greater than t
REF
R.
However in such a circuit input reference pulse is generated through a clock generator circuit
with a certain inverted delay block. This block determines the input pulse width that needs to
be set to a width slightly smaller than the reset delay. Few disadvantages exist originated from
this delay line such as; This delay line used for pulse generation is expected to set a certain
limitation on operating frequency. Moreover, this delay increases the power consumption of
the block.
Another type of dynamic ip op circuit from [10] is given Figure 3.13. Operation principle
of this circuit is as follows; at initial state, REF, DIV, reset, UP and DN signals are assumed
to be logic low. Thus node X is precharged to VDD. At the rising edge of the reference signal
UP
N
node is discharged to 0, thus producing an UP pulse. The same principle holds for the
divider signal, that rising edge of the divider signal sets DN signal to VDD. When both UP
Figure 3.13: Architecture proposed by Tak
and DN signals are received, outputs are reset through a NOR gate. For the following periods
of reference signal, same principle holds.
Reference signal is applied to input through a delay block that precharges the node X to
VDD together with reset signal with an AND operation. At the rising edge of reference signal
delayed input should still be logic low. Otherwise the edge information would be lost. On the
other hand, inserted delay should be slightly smaller than reset delay to prevent PLL losing
lock for 0 phase dierence. If the inserted delay is bigger than reset delay, than the input
clock information of previous period activates the outputs after reset.
Figure 3.14: Output characteristic in [10]
A good arrangement of these delay lines result in the characteristic given in Figure 3.14. Here
corresponds to the total time delay including reset path, t
REF
, and gate delays of the
transistors.
3.1.6 Phase Frequency Detector Design
The phase-detector used in this work is similar to the one given in Figure 3.13 with a small
dierence as given in Figure 3.16 where NOR gate is replaced with an AND gate. The reason
for this can be explained as below;
The goal of PFD design is to minimize delay from the reference or divider to output pulses
in order to satisfy high frequency operation. In this topology this delay equals to total delay
through one NMOS gate and the output inverters, X
1
or X
2
. In IBM 65nm technology,
transition times of a single inverter, t
INV
, are in the order of 10ps. Driving capability of
the inverter is also important in order to avoid additional delay in between PFD and charge
pump which would be introduced by the additional buer circuitry. t
REF
in Figure 3.16 is
simply one gate delay and in the order of 10ps.
With the original structure the outputs are reset with a NOR gate. In order to do so, negative
outputs are applied to the NOR gate. Total reset delay of this structure is t
REF
and the
delays through the transistors. With the rising-edge of the reference signal, UP output is
set high after a transition time equal to the delay of transistors and the inverter, t
INV
.
When the rising-edge of the VCO output arrives, DN output starts to rise. However, when
negative of DN output, DN
N
, reaches the threshold of the NOR gate, both outputs are reset
immediately as a result of the short reset-path delay, as given in Figure 3.15. If the delay
is increased from
tot
to
tot
+ t
ex
, UP will be high for t
ex
seconds longer and the charge
deposited on charge pump will increase by I
CP
t
ex
.
To solve this phenomenon, it is obvious that the reset-path delay must be more than the
transition delay from reference input to a correct UP output, or similarly the transition delay
from VCO output to a correct DN signal. This additional delay can be introduced with an
AND gate with UP and DN inputs instead of negative ones as in Figure 3.16.
Figure 3.15: Shorter delay problem in reset path
The output frequency of the PLL systems is in 4.9GHz5.9GHz. With a xed division ratio of
6, required operation frequency for phase frequency detector should be 984MHz minimum.
This frequency is considered to be minimum since PFD frequency range should also include
parasitic eects from extraction.
Figure 3.17 shows the output waveforms of the extracted PFD, when the reference input and
the divider output are in phase 1GHz square wave signals. Both UP and DOWN signal paths
must be identical for symmetrical operation. This simulation is included here in order to
show that this property assures the symmetrical operation in charge pump. In Figure 3.18,
R
EF
is leading V CO for 300ps.
Figure 3.16: Phase Frequency Detector used in this work
Figure 3.17: PFD output for in phase 1GHz square wave inputs
Figure 3.18: PFD outputs at 1GHz when the reference signal leads for 300 ps
In both gures, propagation delay from an input to a correct UP or DN output is marked as
82ps and total reset delay of the PFD after extraction is 288ps allowing a maximum operation
frequency of 1.74GHz. Power consumption during locked condition under typical operation
is 0.246 mW from 1.2 V power supply.
Figure 3.19: PFD Characteristic
In Figure 3.20, output jitter of the phase frequency detector is given. The period jitter, (i.e.,
the standard deviation of the length of a single period which is measured as Jc k-cycle jitter
when k=1) is 140fs as can be seen from Figure 3.20.
In Figure 3.21, layout of the phase frequency detector is given. Area consumption for the
layout was not a design constraint thus no extra eort for area compaction is performed due
to limited layout time, but carefully drawn layout can reduce the current are consumption
3.2 Charge Pumps 31
Figure 3.20: PFD Output Jitter
area considerably.
3.2 Charge Pumps
3.2.1 Current and Pulsewidth Mismatch
The current sources I
UP
and I
DN
when implemented using MOS transistors, charge pump
suer from current mismatches. When the UP current source is implemented with PMOS
and DN current source with NMOS, for same amount of current sources would have certain
switching speed dierence. This mismatch gives rise to a change or ripple in the control
voltage Vc at each phase comparison. Phase oset due to charge pump mismatches is given
by Equation 3.6;
CT
MIS
= 2
T
ON
T
REF

I
I
(3.6)
To minimize phase error originated from current mismatch, turn on time of current sources
should be minimized.
3.2.2 Timing Mismatch
For the cases that charge pump is single ended, inverted UP signal is required to switch on
the PMOS current source. This introduces certain amount of timing mismatch between the
UP and DN inputs. When there is a certain time delay, between inputs then the phase oset
is given by;
Figure 3.21: Phase Frequency Detector Layout
TIME
MIS
= 2
T
ON
T
REF

T
D
T
REF
(3.7)
3.2.3 Leakage Current
One of the basic problems in charge pumps is the leakage current which may be caused
by the charge pump itself, loop lter impedance, or the VCO control line. The amount of
leakage current can be as high as 1nA in sub micron CMOS [23] . The loop response for
this DC leakage current is a dierence between the UP and DN signals that would produce
the same amount of current equal to leakage current over one period. In other words, charge
pump outputs a certain phase oset to compensate for this leakage current. This phase oset
might be negligible for the cases that charge pump current is high however since the loop
compensation current is periodic with f
REF
, this gives rise to spurious component at the
output spectrum.
The phase oset originated from leakage current can be calculated as;
LEAK
= 2
I
LEAK
I
CP
(rad) (3.8)
Thus total spurious component at the output is given by the total phase oset caused by
these components;
3.2 Charge Pumps 33
Figure 3.22: Charge Pump leakage current
TOT
=
LEAK
+
CT
MIS
+
TIME
MIS
= 2(
I
LEAK
I
CP
+
T
ON
T
REF

I
I
CP
+
T
ON
T
REF
T
D
T
REF
) (3.9)
The magnitude of the spurious breakthrough is directly related to the total phase oset and
is calculated as [23];
P
SPURIOUS
= 20 log
_
N f
BW

TOT
2f
REF
_
20 log
_
f
REF
f
P1
_
(3.10)
where N is the division ratio, f
BW
is the loop bandwidth, f
P1
is the 1
st
pole frequency of
the loop lter. It can be concluded that to reduce the amplitude of the reference spurs,
division ratio, loop bandwidth and total phase mismatch should be minimized while increasing
reference frequency.
3.2.4 Charge Injection
When the switches are ON, nite amount of charge is held in the channel. The charge that
is held during ON time ows partially through both drain and source of the device. The
amount that is injected through the load capacitance gives rise to control voltage even the
inputs are OFF. This leads to wrong output signal. However if the MOS transistor is turned
o while in saturation then all the channel charge ows into the source leaving the drain
terminal unaected. C
gd
capacitance of a MOS transistor in triode region is given as;
C
gd
= C
gs
=
C
gg
2
=
WLC
ox
2
(3.11)
For this condition gate to drain capacitance is larger compared to the capacitance magnitude
in saturation. Thus it is always desirable to keep the output transistors in saturation in order
to minimize the glitch current.
In practical applications, this is hardly the case. Switches are generally operated in triode in
order to have small on resistance. There is constant amount of charge in the channel which
is held when the switches are active and this charge is injected into the output nodes when
the switches are turned o. When the input voltage of the switches has a transition time of
T while changing from logic low to high, the amount of the glitch current can be given as
in Equation 3.12;
I
glitch
= C
gd
(V
H
V
L
)/
T
= C
gd
S (3.12)
where S is the slew rate of the input voltage during the transition. Thus this equation reveals
an interesting property that the amount of glitch current gets larger with increasing C
gd
capacitance and fast transitions. The amount of glitch current can be as large as the charge
pump current or even larger than it but owing in the opposite direction.
As a result charge injection in charge pumps is a serious problem that should be carefully
taken care of.
3.2.5 Clock Feedthrough
This is due to the parasitic capacitances C
gd
and C
gs
. The error occurs when the fast rise and
fall edges of a clock signal get coupled into the signal node via the gate to source and gate to
drain overlap capacitances. This rise in signal level at times forward biases the junction diodes
and leads to an injection error into the substrate leading to wrong operation if conducted by a
high impedance node. However clock feed through error is signal independent and manifests
itself as an output voltage.
3.2.6 Charge Sharing
This occurs when the output of a switch (for example a PMOS device) is set to high and
then the switch is turned OFF. Than the cascade connected device is activated and its voltage
dependent parasitic capacitances, C
gd
and C
gs
, are maximized. Since the gate of this device is
oating, these parasitic capacitances share the gate charge and conduct it to both source and
drain. This causes glitches at the output of this device, i.e the loop lter. This phenomenon
occurs also in charge pumps causing glitches loop lter voltage. For High frequency high
bandwidth applications of PLL, parasitic capacitances become comparable with the loop
lter. This increases the charge sharing eect.
3.2.7 Charge Pump Architectures
Charge pump architectures can be classied into groups by the form of operation; single ended
and dierential operation.
Single-ended charge pumps
Single-ended charge pumps are widely used since they do not require complex congurations.
Moreover with tri-state operation, single ended architectures oer low-power consumption
compared to dierential architectures. Single ended architectures typically have three types
of switching locations; drain, gate and source switching.
3.2 Charge Pumps 35
Drain switching ; For these architectures, switch is located at the drains of the current
mirror. A very simple conguration for drain switching is given in Figure 3.23 (a). When
the switch is turned OFF, drain of down current mirror is pulled to ground. When the
switch is turned ON, this time drain voltage is increased to voltage level of the loop
lter. During this operation, a high current peak occurs because of the voltage dierence
of the two series on resistors of the switch transistor and current mirror transistor, M
1
.
For PMOS side, the same situation also occurs and the amount of these pmos or nmos
current peaks vary with the output voltage.
For the cases that switch is located at the drains of current mirror transistors, clock
feed-through arises. Switch is directly connected to the loop lter thus high amplitude
current spikes that occur at the very beginning of pump up/down action are injected
directly to the loop lter.
Figure 3.23: Single ended charge pumps
Gate switching [27]; In Figure 3.23 (b), a charge pump architecture with gate switch-
ing is given. With this topology it is guaranteed that current mirrors are always kept in
saturation. Switching time is dependent on the transconductances of the mirror tran-
sistors M
4
and M
3
. In order to meet high frequency operation specications, charge
pump current may not be scaled down since switching time is dependent on the g
m
s of
M
4
and M
3
. This may set a limit for high frequency operation.
Source switching ; The switch can also be located at the source of the current mirror
satisfying that current mirrors are in saturation all the time. In contrast to gate switch-
ing, now switching time is not a function of g
m
s of M
4
and M
3
. This conguration
gives faster switching than gate switching since switch is connected to a node with low
parasitic capacitance.
There also exist other variations of single ended charge pump architectures as given in Figure
3.24.
In Figure 3.24 (a) a single ended charge pump with current steering technique is proposed
[11]. Operation principle is similar to to the one given in Figure 3.23 (a) however the switching
is improved by using the current switch. Thus it provides faster switching.
Another single ended topology with an active amplier is given in Figure 3.24 (b). With this
unity gain amplier the voltage at the drain of M
1
and M
2
is set to the voltage at the output
Figure 3.24: Single ended charge pump architectures a)with current steering switch b)with active
output buer c)with NMOS switches only
node when the switch is o to reduce the charge sharing eect when the switch is turned on.
This architecture is useful when the parasitic capacitance is comparable to the value of the
capacitor in the loop lter.
In Figure 3.24 (c), intrinsic mismatch between NMOS and PMOS switches is avoided with
NMOS only implementation of charge pump topology. Since the current does not ow in the
current mirror, M
6
and M
7
, when UP switch is turned OFF, the current mirrors still limit
the performance unless large current is used. Thus the main drawback of this architecture is
the lower speed due to the turning-o of the PMOS current mirror.
Dierential Charge Pumps
A higher switching technique is dierential switch that uses the current steering technique.
This improves the switching speed however the mismatch between the PMOS and NMOS
current sources. Fully dierential charge-pumps are preferred in low-voltage low-jitter PLLs
due to their increased supply and substrate noise rejection and higher voltage swing. On
the other hand the leakage currents appear as a common mode glitch thus reducing spurious
breakthrough of the reference signal.
A dierential charge-pump based on current steering decreases the severity of current mis-
match problem. Any current mismatch between the NMOS and the PMOS transistors then
appears as a common mode glitch, which is therefore suppressed by the following stages in a
phase-locked loop.
3.2.8 Dierential Charge Pump Design
Previous section gives a brief description of the problems that occurs with charge pump
operation. The main problem is the current-mismatch, which arises as a result of the extra
delay added to the reset-path of the PFD to eliminate the dead-zone. Ideally, a charge-pump
PLL does not suer from current-mismatch once it is locked, because the UP and DOWN
3.2 Charge Pumps 37
currents remain o all the time. However, in practical applications, after the additional reset-
delay, the loop locks for a nite phase-error if there is a current-mismatch. The phase-error
in terms of the mismatch ratio is given in Equation 3.9. As long as the reset-delay or the
mismatch increases, the phase error also increases.
Figure 3.25: CPhigh speed
Figure 3.25 shows a fully dierential charge-pump, which uses current steering technique.
When the charge pump is not active, i.e. there is no dierence between UP and DN current
pulses, charge pump current is directed to a dummy branch. The advantage of this architec-
ture is that when the output switches are turned o, the currents in transistors M
9
and M
11
or similarly M
10
and M
12
remain constant, and is just steered to the other branch. With
this architecture current sources are always on and in saturation, thus charge sharing eects
due to the switching are minimized. However the output common mode voltage needs to be
controlled in order to satisfy that full output swing can be used.
Switch Design
Transistors M
1
to M
8
are simple switches processing the information received from the phase
frequency detector. As to lower the on resistance of these switches, it is desirable to maximize
their sizes. If the channel resistance is not suciently low then there is a certain voltage drop
across the switch which limits the available the output range for control voltage. When the
switches are too large, another limitation reveals that their parasitic capacitances increases
the slewing and slows down the switching operation. High frequency operation may not be
performed when the switches are too large. Channel resistance of a MOS transistor operating
in triode is given as in Equation 3.13 [20];
r
on
=
1
i
D
/v
DS
=
1
KW
L
[(V
gs
V
T
)V
DS
V
2
DS
2
]
V
DS
=
L
KW(V
gs
V
T
) V
DS
(3.14)
A good switch design is performed with a good compromise of channel resistance and gate
drain capacitance. However channel resistance is proportional to L while the gate drain
capacitance is proportional to W L as given in Equation 3.11. Thus, for a minimum length
device, there exist an optimum device width.
On the other hand, switch size is critical parameter, also in noise contrubition of the charge
pump. Noise voltage contribution of a switched transistor can be derived from its thermal
equivalent noise resistance as [20];
e
2
r
on
= 4KTr
on
V
2
/Hz =
2KTr
on
V
2
/rad/s (3.15)
Noise contribution theory also claims that on resistance of the switches should be minimized
in order to reduce charge pump noise contribution.
Simulations and Layout
In Figure 3.26 noise voltage at charge pump output is given. Dierent curves refers to
swept switch sizes. If the switch sizes are too small, (i.e. 5u), in band noise contribution
of switches can be as high as 5dB additional. However after a certain switch size, noise
levels stay almost same. As a result switch sizes is chosen as 20u and switch layout is
given in Figure 3.27.
Common Mode Feedback Circuit
With fully dierential architectures, output common mode voltage is not well dened. Charge
pump architecture used in this design is a fully dierential one. When the currents owing
through each branch are not balanced, output voltages may increase or decrease. In other
words, when the output switches are both OFF, output node voltages are not dened. Thus
a control mechanism is required to set these voltages to a proper value. The circuit given in
Figure 3.28 is used in this work for common mode signal stabilization at output.
Operation of this block can be briey expressed as follows; For the case that both OUT+ and
OUT are equal to each other in magnitude but they have opposite signs, the current in M
1
and M
3
would be equal to each other while the current in M
2
and M
4
would be equal too.
This relation holds as the magnitudes of the input dierential voltage stays the same. As
long as OUT+ and OUT are equal in magnitude but have dierent polarities, the current
3.2 Charge Pumps 39
Figure 3.26: Noise voltage at charge pump output
Figure 3.27: Switch layout
Figure 3.28: Common Mode Circuit
into the diode connected transistor M
7
would stay constant. It is concluded that this type of
circuit does not respond to dierential signals.
When the common mode voltage is not equal to V
CM
, for example common mode voltage at
OUT+ and OUT is bigger than V
CM
, than the current through M
2
and M
3
increases the
sourcing current from the diode M
7
. This current can be copied and added to charge pump
current. Increase in charge pump current pulls down the output nodes to lower voltage, thus
performing negative feedback on common mode voltage. The output currents are injected
into the nodes in the charge pump shown in Figure 3.25.
However, it has to be carefully designed that common mode loop always have additional poles
and zeros to the system. The injection of common mode signals can cause the system become
unstable thus common mode circuit has to be compensated. During the design of such a
common mode loop, it is an important consideration that phase margin and step response is
veried.
Common mode feedback circuit should respond to slow changes at output nodes, how-
ever its bandwidth should still be bigger than the loop bandwidth. In Figure 3.29, its
low frequency transconductance is shown as 300/V . Layout for common mode circuit
is given in Figure 3.30(a).
Transistor sizes are given in Table 3.1.
3.2 Charge Pumps 41
M
15
, M
16
12u/0.2u
M
17
, M
18
, M
19
, M
20
25u/60n
M
21
, M
22
8u/0.2u
Table 3.1: UGB transistor sizes
Figure 3.29: Transconductance of common mode loop
(a) CM (b) UGB
Figure 3.30: Layouts of common mode circuit and unity gain buer
3.2 Charge Pumps 43
(a) Unity Gain Buer (b) UGB Schematic
Figure 3.31: Unity gain buer used in this work
Unity Gain Buer Circuit
In single ended charge pump architectures charge injection of the switches can be eliminated
with correct placement of the switches, (i.e. drain, gate, source switching) as mentioned
in Section 3.2.4. However, with dierential architectures, switches are located at the output
nodes, and the topology suers from charge injection of both the switches and common source
nodes X and Y or X
and Y
, (nodes are shown in Figure 3.25. The charge injection from

nodes X and Y is typically much greater than that of the switches, and modications has to
be made to reduce these eects.
On the other hand when the dummy branch is inactive, the nodes V
DX
and V
DY
in Figure
3.25, are not dened. Therefore a buer is required to hold the voltage of the replica node to
the same voltage as that of the output node.
The advantage of this architecture is that when the output switches are turned o, the
currents in transistors M
9
and M
11
or similarly M
10
and M
12
remain constant, and is just
steered to the other branch. This means that the voltages at nodes X and Y or X
and Y
stay approximately constant, minimizing charge sharing. The opamps used in the buered
charge pump are in a standard rail to rail input topology [28].
In a simple rail-to-rail input stage, an n-channel dierential pair and a p-channel dierential
pair are used in parallel as shown in Figure 3.31(b). There are basically three operation
regions; when the common mode voltage, V
CM
is near the negative power supply, V
ss
, or G
nd
in this work, only the p-channel pair operates. For V
CM
, near the positive power supply, V
dd
,
only the n-channel pair operates. For V
CM
around mid-rail, both dierential pairs operate.
As a result, at least one of the two dierential pairs will be operating for any V
CM
between
the rails.
Since there are three regions of operation for the input stage of the unity gain buer, there are
three dierent regions for the total transconductance, g
mT
, which is given, in strong inversion,
by;
g
mT
= g
mn
+g
mp
=
_
2K
n
I
n
+
_
2K
p
I
p
where K
n
and K
p
are the transconductance parameters of the n and p channel input
transistors.When the current sources are implemented with a constant current sources, g
mT
varies depending on the operation region. This may lead to a complexity in frequency com-
pensation, thus the loop may be driven out of stability. In Figure 3.32, AC response of the
closed loop for dierent common mode input is given. Minimum and maximum bandwidths
are as 285.7MHz and 389.1MHz which is well above the loop bandwidth for a common mode
range of 100m 1.1V and stays below the reference input not to respond to input signal.
On the other hand, the noise from the CMFB circuit and unity gain buer circuit is com-
mon mode to the charge pump, so it has little impact on the phase noise of the frequency
synthesizer.
Transistor sizes of the unity gain buer circuit is given in Table 3.2.
M
1
, M
2
18u/60n
M
3
, M
4
25u/60n
M
5
2u/0.2u
M
6
4.2u/0.2u
M
7
, M
8
6u/2u
M
9
, M
10
, M
11
, M
12
, 16u/2u
Table 3.2: UGB transistor sizes
Layout for unity gain buer circuit is given in Figure 3.30(b).
Bias Block
The complete circuit of the bias block used in charge pump design is shown in Figure 3.33.
The circuit consist of wide swing current mirrors and a start up circuit. Transistors M
1
to
M
2
, form the n channel current mirror together with the diode connected bias transistor M
12
.
Transistors M
3
to M
4
simply act as a current mirror. Gate voltages of these transistors are
derived from the diode connected transistor M
12
. The current for the biasing transistor M
12
is produced by the current copy transistors M
13
and M
14
. Similar structure holds for the
PMOS current mirror components. M
11
is used for biasing purposes of gates of M
5
and M
6
and the current into this diode connected transistor is produced via M
9
and M
10
.
This bias loop has two solutions since it is a modied version of general gm bias circuit. There
is a possibility for the current into the transistors to be zero. Once this occurs, the circuit
stays stable in this condition forever thus it does not start up. To ensure this condition does
not happen, a start up circuitry that aects the bias loop only when the currents are zero, is
required. M
15
, M
16
, M
17
and M
18
are included for this purpose. When there is no current
3.2 Charge Pumps 45
Figure 3.32: AC response for dierent input levels of UGB
Figure 3.33: CP-Bias Block
owing in the loop, M
15
is o. M
16
being always on, operates as a high impedance load. It
pulls the gates of M
17
and M
18
high. These transistors, M
17
and M
18
, will then inject current
into the bias loop via M
10
and M
4
. This would start up the circuit. Once the circuit are
biased properly M
15
sinks all the current from M
16
and it pulls down the gates of M
17
and
M
18
to low thus turning them o. Once the circuit starts up, then there is no current owing
through the transistors in start-up circuit.
M
1
, M
9
, M
15
, M
17
, M
18
3u/0.2u
M
2
12u/0.2u
M
3
, M
4
, M
10
3u/0.3u
M
5
, M
6
, M
14
6u/0.3u
M
7
, M
8
, M
13
6u/0.2u
M
11
1.2u/0.3u
M
12
0.6u/0.3u
M
16
0.6u/6u
Table 3.3: Bias Block transistor sizes
Figure 3.34: Layout for CP bias block
Glitch Suppression
High-speed glitch is mainly originated from the charge sharing eect discussed in Section
3.2.4. There are several techniques for charge injection cancellation as given in [22]. In this
work transmission gates are used for charge cancellation.
Charge injection eects can be partially eliminated by making use of complementary switches.
The amount of charge injected to the output node have dierent signs, and with a good
combination of the P
MOS
and N
MOS
devices, injection of charge to output node can be
lowered.
3.2 Charge Pumps 47
Figure 3.35: Transmission gate as a switch
For fully cancellation of charge injection, q
N
and q
P
should be equal to each other.
q
N
= W
N
L
N
C
ox
(V
CK
V
IN1
V
THN
) = W
P
L
P
C
ox
(V
CK
V
IN1
V
THP
) (3.16)
From this result, it can be seen that, cancellation of charge depends on the accuracy in device
sizes, and the threshold voltages of P
MOS
and N
MOS
devices as in Equation 3.17. Thus
totally cancellation is not possible however reduction in charge injection is expected.
W
N
L
N
(V
CK
V
IN1
V
THN
) = W
P
L
P
(V
CK
V
IN1
V
THP
) (3.17)
Charge pump of this work is modied as given in Figure 3.36 in order to have suppressed
the high speed glitches. After adding the modied switches, the high-speed glitches are
almost completely eliminated from the output current since P
MOS
and N
MOS
transistors in
transmission gates are matched. In practical implementation, however, this performance will
be limited by the resistance in the loop lter and any other parasitic resistance like routing
resistance and gate resistance.
Figure 3.36: Modication for Glitch Suppression
However there is an obvious drawback which is the increased complexity as compared with
the standard architectures, as it is now necessary to generate and route both the primary
input signals and their inverses.
Total power consumption under typical operation is 2.05 mW from 1.2V power supply.
Figure 3.37: Charge pump Full Schematic
3.2 Charge Pumps 49
Figure 3.38: Complete Charge pump layout
Chapter 4
VCO & Divider
The VCO is the most challenging part of the PLL design, especially if the PLL reference input
frequency is high. In this case, a high frequency VCO is necessary. Oscillators may seem like
simple devices, until you have to design one into your system. Thats when you may discover
there is much more to these critical timing devices than meets the eye. There are many
requirements for the VCO in a PLL design, which conict with one another. Therefore, a
special care must be taken in the VCO design. Some of the most important VCO requirements
and VCO terms include the following:
Control Voltage : This is the varying voltage, which is applied to the VCO input
terminal causing a change in the output frequency.
Free-Running Frequency : FR is the output frequency of the VCO for a zero control
voltage. It is sometimes referred to as center frequency.
Tuning Range : The range of frequencies over which the VCO can operate as a result
of the applied control voltage.
Frequency Deviation : This is how far the center frequency will change as a function
of the control voltage; usually specied in percentage or ppm. As the deviation is
made larger, other stabilities such as, temperature and aging will usually degrade.
Linearity: The generally accepted denition of linearity is the ratio between frequency
error and total deviation, expressed in percent, where frequency error is the maximum
frequency excursion from the best straight line drawn through a plot of output frequency
versus control voltage.
Response Slope : The slope of the frequency versus the control voltage. This is
generally referred to as the VCO gain, KVCO, or the tuning performance and expressed
in megahertz per volt (MHz/V).
52 VCO & Divider
Transfer Function : This denotes the direction of frequency change versus control
voltage and sometimes referred to as Slope Polarity. A positive transfer function de-
notes an increase in frequency for an increasing positive control voltage. Conversely, if
the frequency decreases with a more positive control voltage, the transfer function is
negative.
Phase Stability : The output spectrum of the VCO should approximate as good as
possible the theoretical Dirac-impulse of a single sine wave. It is mostly referred to as
Spectral Purity and quantied by phase noise, which is expressed in terms of dBc/Hz.
Frequency pushing : It is the dependency of the center frequency on the power supply
voltage expressed in MHz/V. In this work, S
V DD
is used as the sensitivity parameter.
Frequency pulling :It is the dependency of the center frequency on the output load
impedance.
Tuning Speed :This is the time required for the output frequency to settle to within
90% of its nal value with the application of a tuning-voltage step.
Output Amplitude : It is desirable to achieve large output oscillation amplitude,
thus making the waveform less sensitive to noise. The amplitude trades with power
dissipation, supply voltage, and even the tuning range. Also the amplitude may vary
across the tuning range, which is an undesirable eect.
Output Characteristics : This denes the output waveform of the VCO. In PLL
applications, sine or square-waves are used mostly.
Power Dissipation : As with other analog circuits, oscillators suer from trade-os
between speed, power dissipation, and noise.
In literature many types of oscillators can be found [19]. Depending on the application, these
types are benecial or undesirable. In current application, oscillator types are discussed by
their phase noise, i.e jitter, performance and their supply sensitivity. CMOS voltage controlled
oscillators, VCOs, are customary designed either by using ring oscillator architectures or LC
resonant circuits. Although amongst these applications, LC designs has better phase noise
performance, they are undesirable due to the increased complexity and cost by addition of
high quality integrated inductors. In spite of LC oscillators, ring oscillators can be built in
any standard CMOS technology with much less die area. Moreover, they oer multiple output
phases and wide tuning ranges. In this work, main focus is on ring oscillators due to ease in
integration.
4.1 Ring Oscillator VCOs
Ring oscillators are often used in PLL applications due to their simplicity and ease in IC
integration. Basic oscillation principle is based on the ring of inverters in a chain. However,
with single ended structures it is not possible to achieve oscillation with less then three stages
and odd number of inverter stages is required [21]. In a certain technology, total delay of
three inverter stages puts a limit to the maximum achievable frequency.
4.1 Ring Oscillator VCOs 53
4.1.1 Single Loop Ring Oscillator Design
Figure 4.1: Three-stage ring oscillator
Figure 4.1 shows a typical single-stage inverter placed in a unity-gain loop where R and C
are the output equivalent node resistance and capacitance of the inverter stage, respectively.
Under the assumption that all stages are identical, system has three poles located at
p
in
Equation 4.1 which is the 3dB bandwidth of a single stage inverter.
p
=
1
RC
(4.1)
For three stage inverter, total phase shift of the system at
p
equals to 135
o
(each stage
contributes 45
o
) and as = total phase shift becomes 270
o
. Therefore, a certain
frequency exists for the system that total phase shift equals to 180
o
, i.e. each stage has a
phase shift of 60
o
. Each stage also contribute a DC phase shift of 180
o
thus waveform at
each node is 240
o
out of phase with respect to the previous node.
Nevertheless, to meet the Berkhausen criteria, loop gain must be equal to unity at the oscil-
lation frequency. Transfer function of each stage is given as;
G(s) =
A
1 +
s
p
(4.2)
Thus, transfer function for the open loop three stage oscillator is given as;
H(s) =
A
3
(1 +
s
p
)
3
(4.3)
To meet the phase shift criteria of 180
o
in three stage design, single stage should have a phase
shift of 60
o
at oscillation frequency ;
G(s) = arctan

o
p
= 60
o
o
=
3
p
(4.4)
From 4.1 and 4.3 general oscillation frequency can be given as;
O
=
tan
RC
(4.5)
where is the total phase shift of each stage individually.
54 VCO & Divider
To meet the loop gain criteria, magnitude of the loop gain at the oscillation frequency should
be equal to or greater than unity.
[H(
o
)[ =
A
3
_
1 +
_
p
_
2
3
= 1 (4.6)
Applying 4.4 into 4.6 each stage should have a gain of A = 2 for proper oscillation. Closed
loop poles can be examined to see this property clearly.
V
OUT
V
IN
=
1
1 H(s)
(4.7)
One of the three closed loop poles is real and other two are complex conjugate;
s
1
= (A1)
o
(4.8)
s
2,3
=
_
A(1 j
3)
2
1
_
o
(4.9)
Thus the output waveform in time domain can be given as;
V
OUT
(t) = ae
(
A2
2

p
t)
cos
_
A
3
2

p
t
_
(4.10)
According to the Berkhausen criteria;
If A 2, The poles are on left half plane, and output decays exponentially to 0. Thus,
circuit fails to oscillate.
If A=2, then two poles are on j axis, one pole is on real axis. The output is a sinusoid
at the frequency of

3
o
. Thus, steady state oscillation occurs.
If A ~ 2, two complex poles now have a positive real part and hence give rise to a
growing sinusoid. Thus, the oscillation grow in amplitude and goes to innity. However
in most practical cases, due to nonlinearity and eventually saturation of the stages
oscillation amplitude is limited.
In practical conditions oscillation frequency is dened based on the total delay of the inverter
stages;
f
o
=
1
2nt
d
(4.11)
This oscillation frequency, f
o
, is obviously not equal to the frequency obtained from the
small signal analysis since small signal analysis does not include the non linear behavior of
active components as the oscillation amplitude grows. For the current application rail to rail
switching is aimed. Small signal behavior study gives an insight on how the system operates
but it does not a suciently explain dynamics in rail to rail switching.
4.1.2 Multi Loop Ring Oscillator Design
When ring oscillators are implemented in single loop inverter stages, maximum operating
frequency is simply set by the total delay of the inverter stages. For a xed technology,
maximum achievable frequency relays on the minimum delay of a single stage. This restric-
tion reveals a challenging requirement on maximum attainable frequency. There are many
techniques that oer high frequency ring VCOs, available in literature such as sub feedback
loops [16], multi feedback loops [7], dual delay paths [25] or oscillator coupling [1]. General
multi loop architecture which is shown in Figure 4.2 is one of the promising techniques that
operates at higher frequencies and it is the main conguration used in this work. In this
architecture, inverter stages have two dierential inputs P, P+ and S, S+. Main inputs
being P, P+ constitute the strongest path, the auxiliary feed forward inputs, being S, S+,
reduce the delay of the stages by speeding up the transition at output nodes. The frequency
of operation is dened by the number of stages in both loops, and the fastest path sets the
operation frequency.
Figure 4.2: 4 Stage Multi Loop Ring Oscillator
To understand the frequency control mechanism in multi feedback loops, even and odd number
of stages are studied here.
Odd Number of Stages
Figure 4.3: 3-stage ring oscillator with multi loop architecture
In Figure 4.3, a simple conguration of multi loop architecture with three stage inverters is
given. Secondary feed forward loops are obtained by connection of k
th
outputs to n
th
inputs
where N is the number of stages, n equals to [(k +x) modN], and (x 1) is the number of
stages that feed forward loops passover [8].
Under the assumption that each output can be modeled with a single output resistance, R
and capacitance equivalent, C, small signal analysis can be applied to the 1
st
order model
given in Figure 4.4. In this model 1st stage consist of a dierential stage where the main loop
is composed of inverters G
M
and the auxiliary loop is formed by the inverters g
m
.
56 VCO & Divider
Figure 4.4: 3 stage ring oscillator 1
s
t order model
Prior to small signal behavior study, it should be strictly stated that ring oscillators are
highly nonlinear, large signal systems. Their operating parameters greatly deviate from the
ones obtained from small signal analysis. Since rail to rail switching is the main design goal in
order to minimize phase noise requirements, it is likely that transconductance of transistors
decreases with increasing signal swing. However small signal analysis is still essential to attain
an insight about the circuit parameters that control frequency.
In multi loop architectures main loop is intentionally designed to be stronger than the auxiliary
loop, thus phase relation is determined by the main loop.
For a three stage design following condition holds;
V
n+1
= V
n
e
j
(4.12)
V
n+1
= V
k+1
e
j
(4.13)
where the output of a single stage can be given as;
V
n+1
=
R
1 +jRC
(V
n
G
M
V
k+1
g
m
) (4.14)
Output V
k+1
can be rewritten as V
n+1
e
j
. Thus;
V
n+1
=
RG
M
1 +jRC
V
n
+
Rg
m
1 +jRC
V
n+1
e
j
(4.15)
Rearranging the V
n
and V
n+1
terms, transfer function can be written as given in Equation
4.16.
H(j) =
V
n
V
n+1
=
RG
M
1 +jRC Rg
m
e
j
(4.16)
or in other form, the term e
j
can be expressed in terms of its imaginary and real parts;
H(j) =
V
n
V
n+1
=
RG
M
1 g
m
Rcos +j(RC Rg
m
sin)
(4.17)
Phase shift of each stage can be calculated from the phase of its transfer function.
H(j) = tan
1
_
RC Rg
m
sin
1 g
m
Rcos
_
(4.18)
As previously mentioned, phase relation between the stages is determined by the main loop.
Thus, obtained result in Equation 4.18 should be equal to the phase dierence between V
n
and V
n+1
, . Thus phase shift of single stage in terms of circuit parameters can be given as;
tan( ) = tan =
RC g
m
Rsin
1 Rg
m
cos
(4.19)
From Equation 4.19 oscillation frequency can easily be given as;
o
=
tan
RC

g
m
C
[tan cos + sin] (4.20)
For the case g
m
= 0, oscillation frequency equals to the one given for single loop architectures.
It is clearly stated in Equation 4.20 that frequency improvement in multiple pass architecture
should be possible under the condition that tan cos +sin 0 is satised. Since for a xed
number of inverter stages, available phases in loop is determined, connection scheme should
be done to satisfy this condition. For a three stage system, total open loop gain is given as
in Equation 4.21;
G(j) = H(j)
3
=
_
RG
M
1 g
m
Rcos +j(RC Rg
m
sin)
_
3
(4.21)
According to the Berkhausen criteria, the magnitude of the loop gain at the oscillation fre-
quency should be equal to unity. For a three stage ring oscillator, condition in Equation 4.23
should hold.
G(j) = [H(j)[
3
=
RG
M
_
(1 g
m
Rcos )
2
+ (RC Rg
m
sin)
2
3
= 1 (4.22)
For oscillation condition to be satised, condition in Equation 4.23 should hold.
RG
M

_
(1 g
m
Rcos )
2
+ (RC g
m
Rsin)
2
(4.23)
Substituting RC Rg
m
sin term from 4.19 into 4.23 one can easily conclude that required
gain relation of main and auxiliary loop should satisfy the following condition;
RG
M

1 g
m
Rcos
cos
(4.24)
Equation 4.24 is an important result that requires special attention since the gain of the loop
function determines the start up conditions. On the other hand, frequency improvement is
not totally controlled or in other words it is not constant for a given process since absolute
improvement factor depends on process parameters that control output equivalent resistance,
R and capacitance C. Thus parameters obtained from theoretical analysis may not result in
desired frequency improvement.
58 VCO & Divider
Even Number of Stages
Multi loop architecture can also be implemented in even number of stages. However, to satisfy
the Berkhausen oscillation criteria, additional rad phase shift should be introduced to the
loop. In Figure 4.5, an example of a 4 stage multiple pass ring oscillator architecture is given.
For even number of inverter stages, phase relation of the auxiliary loop should be kept same
as the odd number of stages. Model used given in Figure 4.4 is still can be used since internal
conguration of delay stages is assumed to remain same. Additional phase shift is introduced
only with modication of the connection scheme. Phase shift of rads is assumed to be
introduced to loop by reversed inputs of the 1
st
stage.
Figure 4.5: 4 stage multiple pass ring oscillator architecture
Transfer function of each stage can be given as in Equation 4.25.
H(j) =
V
n
V
n+1
=
RG
M
1 g
m
Rcos +j(RC Rg
m
sin)
(4.25)
Phase information around the loop can be obtained by addition of individual phase shifts of
each stages. Thus, Equation 4.26 should be the starting point to examine phase behavior in
even loops.
2k = H
1
(j) +H
2
(j) +H
3
(j) +... +H
N
(j) (4.26)
Phase shift of all stages would be identical except from the 1
st
stage. Thus Equation 4.26 can
be simplied as;
2k = H
1
(j) (N 1) (4.27)
where N is the number of stages in the loop and is the phase shift between the main inputs
and outputs. Since H
1
(j) is designed to have a phase shift of in order to satisfy
Berkhausen oscillation condition, total phase shift can be related to as in Equation 4.28.
=
(2n 1)
N
(4.28)
At the oscillation frequency, phase shift of each stage from the transfer function should be
equal to .
= tan
1
_
RC g
m
Rsin
1 Rg
m
cos
_
(4.29)
4.2 Gain Stages 59
o
=
tan
RC
+
g
m
C
[sin tan cos ] (4.30)
This is an expected result for the operating frequency, which the same as 4.19.
G(j) = H(j)
4
=
_
RG
M
1 g
m
Rcos +j(RC Rg
m
sin)
_
4
(4.31)
Total loop gain of 4 stage ring oscillator, given in 4.31, has a sign inversion compared to the
one given in three number of stages. Minimum gain requirement of each single stage can be
obtained as the same way for odd number of stages.
RG
M

_
(1 g
m
Rcos )
2
+ (RC g
m
Rsin)
2
(4.32)
4.1.3 Loop Architecture Decision
From the discussion in previous sections, it can be easily seen that for multi loop applications,
inputs of the delay cells have to be split either by splitting the NMOS transistors or intro-
ducing additional PMOS inputs. This, in addition to other necessary components such as
frequency tuning and bias current sources, increases the complexity of the oscillator. Simple
mis connection in the delay cell or in the top level loop routings may lead the loop to an
undesired, perfectly stable, latch up condition. However, multiple loop architectures intro-
duce fast transitions at the output nodes thus allowing high frequency operation meanwhile
reducing phase noise.
With single loop architectures, it is not possible to meet high frequency with poor transitions
at the outputs and also phase noise performance is worse compared to multi loop topologies.
As a result, for this work multiple pass architecture is desirable for their superior phase noise
performance and high frequency operation.
4.2 Gain Stages
In previous section loop structure is analyzed by means the parameters that control frequency
improvement in the loop.
Although, frequency range of an oscillator is an essential specication to be met, there are
other exclusive parameters to be taken into account. Constraints such as phase noise or jitter
are also signicant performance parameters, and they are originally depend on the type of
the delay cell used in inverter stages.
When the delay cells are biased in continuous conduction, i.e. switching is not rail to rail,
phase contribution of the active components increases. 1
st
order model given in Figure 4.1
can be used to make the an approximated noise power estimation as [24];
P
NOISE
=
T
T
4kTR
1 + (2f
m
RC)
2
(4.33)
60 VCO & Divider
where T stands for the oscillation period, T is the on time of transistor, f
m
is the oset
from the carrier and RC is the approximated 1
st
order time constant.
For dierential systems power supply rejection ratio is given as the ratio of dierential gain,
A
V
(when the supply is clean), to the power supply gain, A
dd
, when the input is 0;
V
OUT
=
A
V
(V
dd
= 0)
A
dd
(V
in
= 0)
=
A
dd
1 +A
V
V
dd

A
dd
A
V
V
dd
=
1
PSRR
+
V
dd
(4.35)
While it would be still possible to calculate gains A
dd
and A
V
separately, dierential system
can be considered in unity gain conguration, and power supply rejection can be calculated
directly as in Equation 4.34. For the calculation of PSRR in dierent delay cells of this work,
they are all considered in unity gain conguration.
In following sections, a brief study on gain stages is carried out.
4.2.1 CMOS Digital Inverter
An accurate estimate of the gate delay through a simple CMOS inverter gives an insight for
the phase noise analysis of dierent gain stages.
Figure 4.6: Simple Inverter
Throughout the literature, several studies have been performed on noise analyses of single
stage inverters. Here only, results of analyses from [2] is referred in order to make comparisons
with other delay cells.
Propagation delay of a simple CMOS inverter is designated as the time dierence between
the input threshold crossing and output toggle moment [2]. This propagation delay can be
given as 4.37;
inv
=
V
DD
C
I
(4.36)
where C stands for the total output capacitance at output node and I is the current driven
during the switching.
4.2 Gain Stages 61
Phase Noise
Phase noise of a single inverter is given by [19],
S
=
4kT
I
_
1
V
dd
V
t
(
N
+
P
) +
1
V
dd
_
(
f
O
f
)
2
(4.37)
where V
t
is the threshold voltage of inverter.
N
and
P
are the channel noise parameters
of NMOS and PMOS transistors, respectively.
Supply Sensitivity
Simple CMOS digital inverter has a low pass power supply rejection characteristic.
Voltage transfer function from positive supply, V
DD
to output node V
O
has a pole ap-
proximately at
s(C
gs1
+C
gs2
+C
l
)
g
m1
+g
m2
and a zero
C
gs2
g
m2
where the zero is at higher frequencies.
S
V DD
=
V
o
V
dd
g
m2
+sC
gs2
g
m1
+g
m2
+s(C
gs1
+C
gs2
+C
l
)
(4.38)
Within the PLL loop power supply rejection of single inverter is suppressed with the
amount of loop gain. However outside the loop bandwidth, supply noise rejection,
PSRR, remains constant at a certain value.
As a result, digital inverter exhibits extremely poor low-frequency PSRR since any
power-supply noise is amplied by the small-signal gain of the inverter. This is one of
the reasons why digital inverters are not frequently used in VCOs that are intended for
jitter-sensitive applications.
4.2.2 Dierential Pair
In contrast to single ended simple inverter stages, dierential ring oscillators can be imple-
mented with either odd or even number of stages. Dierential ring oscillator buer stage can
be considered as a gain amplier with a control input. This control input can be implemented
as a current sink or current source as given in Figure 4.7.
Figure 4.7: Delay Control in Dierential Gain Stages
The dierential stage given in 4.7(a) exhibit small tuning range because the output capaci-
tance and resistance is not a function of tail current and time constant is not well controlled.
62 VCO & Divider
For the conguration in 4.7(b), load transistors are biased in triode region. Thus their on
resistance is set by the control voltage. As V
CONTROL
drops, time constant at the output
node also drops, and on the other hand small signal gain also decreases. Eventually, this may
result in a large drop of loop gain that circuit may fail to oscillate for lower V
CONTROL
.
For the conguration 4.7(c), small signal impedance of the load transistors are adjusted via
the controlled tail current and since the small signal gain is xed g
m
ratios of the NMOS and
PMOS transistors, gain stage is frequently used in ring oscillator applications.
In general form their oscillation frequency is given as [2];
f
O
=
1
2ln2NRC
=
I
TAIL
2ln2NCV
OUT
(4.39)
where N is the number of stages, R is the equivalent output resistance, C is the equivalent out-
put capacitance, I
TAIL
is the tail current per stage and nally V
OUT
stands for the amplitude
of the output waveform.
Phase Noise
Phase noise of a dierential gain stage can be given as in general form as [2];
S
=
2kT
I
2
TAIL
ln(2)
_
t
g
mt
2
+
d
3g
md
4
+
1
R
__
f
o
f
_
2
(4.40)
where
t
and
d
are the channel noise parameters of tail transistor and dierential pair,
and g
md
is transconductance of dierential pair and g
mt
stands for the transconductance
of the tail current source.
Supply Sensitivity
Supply sensitivity of a dierential pair can be given as in Equation 4.41 [4];
S
V DD
=
V
o
V
dd
1 +sg
m
r
2
ds
C
P
g
2
m
r
2
ds
(C
P
+C
O
)
(4.41)
4.2.3 Delay Cell with push pull inverters (DC
1
) [12]
Another type of delay stage which is suitable for multi loop implementation is presented in
[12] given Figure 4.8. For frequency improvement, secondary inputs are implemented with
a push pull inverter. These inverters basically sharpens both low to high and high to low
transitions.
Primary loop is implemented via transistors M
3
and M
9
, while PMOS transistors M
6
and
M
8
forms the load of the gain stage. In a multi loop conguration, V
S
+ is designed to be
earlier than V
P
+, secondary inverters starts sourcing current to the parasitics at the OUT
output node before the main inputs. In this manner, low to high transition at the output
node speeds up and delay is decreased.
With this conguration, frequency control mechanism is implemented via load transistors
M
6
and M
8
. For an extreme case where the control voltage is too high that these loads
4.2 Gain Stages 63
Figure 4.8: (DC
1
) Delay Cell Proposed by [12]
are turned o, oscillation is maintained by grounded extra loads M
4
and M
10
. Thus output
frequency settles to a constant value for higher values of control voltage. However, since these
extra loads are biased in triode, their noise contribution is continuous during the complete
oscillation period. Moreover they increase the current consumption since they are biased in
continuous conduction.
In addition, cross coupled NMOS latch transistors ensure dierential operation mode, however
they limit output voltage swing.
Phase Noise
Figure 4.9: Phase Noise of DC
1
@ 5.053GHz
64 VCO & Divider
Supply Sensitivity
Model used for PSRR calculation is given in Figure 4.10 and supply sensitivity of a DC
1
can be given as in Equation 4.42;
Figure 4.10: Small signal equivalent model of DC
1
used to calculate PSRR [12]
S
V DD
=
V
o
V
dd
=
g
m4
+g
m6
+sC
gs2
g
m1
+g
m3
+g
m5
+s(C
gs1
+C
gs2
+C
gs3
+C
gs5
+C
o
)
(4.42)
4.2.4 Delay Cell with feedback control (DC
2
) [24]
The circuit proposed in Fig. 4.11 has a dierential structure in order to reduce the power
supply injected noise.
Figure 4.11: (DC
2
) Delay Cell [24]
The tail current source, implemented simply with a MOS transistor, is removed to reduce
noise. PMOS load transistors, M
1
and M
2
form a latch structure, and cross coupled NMOS
M
3
and M
4
control the maximum gate voltage of this latch, thus, they limit the strength
of the added latch. When V
CONTROL
is low, the strength of the latch becomes weak and
the output current increases. When V
CONTROL
is high, the latch becomes stronger resisting
the voltage switching of the dierential cell. Therefore delay time increases. Since, positive
feedback of the latch determines the transition time, output waveform keep performing full
switching, although the delay time changes with control voltage.
Phase Noise
4.2 Gain Stages 65
Since it is dicult to analyze the noise characteristics of the saturated ring oscillator
accurately, the output phase noise of the saturated-type ring oscillator is approximated
by the switching operations on the thermal noise current in the MOS devices. The
generated noise power can be given as in Equation 4.33.
Figure 4.12: Phase noise of DC
2
Supply Sensitivity
Model used for PSRR calculation is given in Figure 4.13 and power supply rejection
of delay cell in Figure 4.11 is given in Equation 4.43. Power supply noise is directly
injected to the delay with transistor M
7
while transistor M
1
is subject to the voltage
division between the C
gs
of the M
1
and output resistance of M
4
.
Figure 4.13: Small Signal Model of DC
2
used to calculate PSRR in [24]
66 VCO & Divider
S
V DD
=
V
o
V
dd
s
2
C
gs1
C
gs7
s
2
C
gs1
(C
gs4
+C
gs5
+C
gs7
+C
o
) +sC
gs1
(g
m4
+g
m5
) +g
m1
g
m4
(4.44)
4.2.5 Delay Cell with common mode noise rejection (DC
3
) [15]
Delay cell proposed by [15] introduces new considerations for low phase noise and common
mode noise rejection. As shown in Figure 4.14(a), each delay cell has complementary inputs
and dierential control terminals.
Output latch is introduced in order to store logic output levels, and meanwhile they assure
rail to rail switching. Input inverters are driven via the inputs. However, strength of these
inverters are controlled by dierentially controlled voltage V + and V via PMOS and NMOS
current sources, thus delay time is determined by the relative strength ratio between input
inverters and latch inverters. As the input inverters made stronger via control voltage, delay
time decreases.
Generally ring oscillators have wide tuning range that it is desirable to limit this range and
pull K
V CO
down to reasonable levels. In order to do so, current sources are biased deep
into triode by biasing gate of M
1
as close as possible to V
DD
. Thus M
1
and M
2
would have
opposite polarities. With proper sizing of these transistors, common mode signals at V
C
+
and V
C
can be canceled. Thus, this type of delay cell oers a good rejection of common
mode noise from supply and ground.
Phase Noise
Single sideband phase noise due to the additive noise can be given as in Equation 4.2.5
[15].
L() =
_
_
16FkTR
2
o
9|/t|
2
max
(

o
)
2
(forV
pp

8V
dd
3
)
64FkTRV
dd
3
o
27|/t|
3
max
(

o
)
2
(forV
pp

8V
dd
3
)
Supply Sensitivity
Although dierential circuits are well known for their improved power supply rejection
at low frequencies, and they are widely used for ring oscillator circuits, there are still
very few designs where the delay cell is controlled dierentially. In most PLL designs,
either a single-ended charge pump and loop lter have to be used, or a dierential-to-
single-ended converter is inserted between the loop lter and the VCO. However, in
both cases, ground and supply noise couples to control voltage. Supply sensitivity for
the delay cell proposed by [15] is given as in Equation 4.45;
4.2 Gain Stages 67
(a) Schematic (b) Block Schematic
Figure 4.14: Schematic of the DC
3
[15]
Figure 4.15: Small signal model of DC
3
for PSRR calculation
68 VCO & Divider
S
V DD
=
V
o
V
dd
=
g
m1
+g
m10
+sC
gs1
g
m1
+g
m3
+s(C
gs1
+C
gs3
+C
o
)
(4.45)
4.3 Delay Cells Performance List
Each delay cell is placed in a 4 stage ring oscillator and they are designed to operate within
the band of interest. Their noise performance is simulated under clean and noisy supply
conditions. The 1
st
column in Table 4.1 shows the phase noise performance under clean
supply and ground condition. In the 2
nd
column, noise performance under noisy supply is
given. For this case, ground is assumed to be clean. In the 3
rd
column, noise performance
under noisy ground is given and also for this case supply is assumed to be clean. And nally
in the 4
th
column, noise performance under noisy ground and noisy supply is given.
Current consumption of the delay cells are also given in Table 4.1.
Clean
@1MHz
Supply
@1MHz
Ground
@1MHz
Supply-
Ground
@1MHz
Total Cur-
rent
Freq(GHz)
DC1 [12] -84.47dBc -63.53dBc -63.53dBc -60.53dBc 22.05mA 5.053
DC2 [24] -83.04dBc -61.27dBc -60.14dBc -57.67dBc 18.54mA 5.933
This Work -83.03dBc -60.95dBc -60.82dBc -57.89dBc 7.72mA 5.503
Table 4.1: Comparison of performance metrics of delay cells
4.4 Ring Oscillator Design
An overview of the phase noise and supply noise contribution for dierent delay cells has been
performed in previous section. In this part, the key parameters on suitable delay cell selection
are discussed and design procedure for the ring oscillator is described.
Main requirements of ring oscillator of the wideband PLL system are its frequency range,
phase noise performance and power supply sensitivity. On the other hand, frequency control
conguration is also important since the charge pump used in this work is a dierential one
and it has dierential control voltage output. There could be two options to combine the
charge pump with VCO;
First conguration could be a system where a single ended controlled VCO is used and
a dierential to single ended converter is inserted in between the charge pump and the
VCO.
Another solution could be a dierentially controlled VCO, where the system has good
noise rejection to both ground and supply.
In this work, second option is chosen in order to avoid dierential to single ended converter
which also introduce poor supply noise rejection.
4.4 Ring Oscillator Design 69
(a) Schematic (b) Block Schematic
Figure 4.16: Schematic and block schematic of the delay cell used in this work
For the conguration given in Figure 4.16(a), frequency span over the central frequency, i.e.
K
vco
is too high. The required tuning range is 1GHz over 5.4GHz and an additional 30%
is required to keep the system perform over process and temperature variations.
Delay cell proposed by Dai [15] is modied for multiple pass loop as given in Figure 4.16(a).
Operation principle is almost similar to the one described in [15] except from the secondary
input inverters, C
1
and C
2
, in Figure ??. These secondary inputs drive a pair of inverters, C
1
and C
2
whose strength is controlled dierentially via the current sources M
13
and M
14
shown
in Figure ??. The delay time is determined by the strength ratio between these controlled
secondary inputs and the latch inverters A
1
and A
2
. The stronger the C
1
and C
2
gets, the
faster the transition at output nodes occurs. This can be roughly explained as; as the C
1
and C
2
gets stronger, the current supplied to output nodes increases and this sharpens the
transition at output. As a result delay time between the cells decreases and the operation
frequency increases. Controlling the strength of these inverters determines the delay time,
thus the frequency.
The current sources M
13
and M
14
are biased in triode region in order to improve linearity of
frequency over control voltage. Thus NMOS current is controlled via V +, the control voltage
that has positive polarity, and PMOS current source is controlled via V in order to serve
for the same concept. Since the V
gs
voltages of these sources are relatively large, variations
on supply is now less eective.
On the other hand, M
13
and M
14
are controlled with signals that have opposite polarities. If
they can be congured with a proper sizing, common mode signals at the control voltage are
canceled out and only the dierential operation controls the frequency. Thus common mode
noise from ground an supply is rejected up to a certain extent.
Phase Noise
70 VCO & Divider
Phase noise of the delay cell is given as in Equation 4.46 [5].
L() =
FkTRV
dd
3
o
[/t[
3
max
(

o
)
2
(4.46)
where L() is the single sideband phase noise, is the empirical constant factor, F
is the excess noise factor according to the Leesons model [5].
Figure 4.17: Phase Noise performance of the delay cell used in this work 5GHz
Supply Sensitivity
Model used for PSRR calculation of DC
3
is given in Figure 4.18 and supply sensitivity
of a DC
3
can be given as in Equation 4.47;
S
V DD
=
V
o
V
dd
=
g
m1
+g
m7
+g
m13
+s(C
gs1
+C
gs7
)
g
m1
+g
m3
+g
m5
+g
m7
+s(C
gs1
+C
gs3
+C
gs5
+C
gs7
+C
o
)
(4.47)
4.4.1 VCO Tuning Range
From the discussion above, it is desirable to limit the K
vco
within reasonable levels. In order
to lower VCO gain and still be able to cover the such a wide required frequency tuning range,
input inverters are divided into 8 switchable inverters connected in parallel. With such a
conguration, 9 dierent bands are obtained.
4.4 Ring Oscillator Design 71
Figure 4.18: Small Signal Equivalent to half circuit for PSRR calculation
Typical Fast-Fast Slow-Slow Fast-Slow Slow-Fast
Min Max Min Max Min Max Min Max Min Max
Band 0 4.010 4.455 4.793 5.332 4.060 4.377 4.026 4.772 4.141 4.755
Band 1 4.326 5.160 5.297 6.121 4.080 4.399 4.442 5.171 4.431 5.158
Band 2 4.831 5.553 5.787 6.595 4.089 4.728 4.845 5.560 4.834 5.551
Band 3 5.223 5.934 6.258 7.054 4.419 5.049 5.234 5.940 5.229 5.932
Band 4 5.605 6.305 6.717 7.500 4.741 5.362 5.612 6.305 5.610 6.305
Band 5 5.976 6.665 7.162 7.934 5.056 5.666 5.977 6.661 5.983 6.667
Band 6 6.337 7.018 7.603 8.355 5.362 5.673 6.334 7.007 6.346 7.021
Band 7 6.690 7.360 8.015 8.766 5.661 6.247 6.678 7.340 6.699 7.365
Band 8 7.034 7.695 8.425 9.165 5.952 6.543 7.014 7.669 7.045 7.704
Table 4.2: VCO Tuning Range
72 VCO & Divider
Figure 4.19: Schematic of VCO delay cell used in this work
4.5 Layout of the VCO 73
4.5 Layout of the VCO
Layout of the complete VCO is given in Figure 4.20. The delay cell is consist of switching
input transistors and the main core. Transistor type used in the design is of importance
from RF perspective since the operating frequency is couple of GHz. One would prefer
the implementations with RF transistors since they oer better modeling for phase noise
and loading eects on VCO by means of their additional substrate network, drain source
diodes and capacitances, gate resistances, gate induced noise eects, etc. However, with RF
transistor, introduced parasitics are relatively greater than that of normal transistors, due
to the long routing and interconnection paths. Since each transistor has its own complete
surrounded ring, interconnections get longer, introducing larger parasitics.
At the very beginning of the layout design, the complete delay cell was drawn with RF
transistors. However, it was not possible to meet the frequency range specication due to
large capacitive loadings at output nodes. Primarily, estimated parasitic node capacitance was
10fF however after layout extraction with RF transistors, equivalent parasitics capacitance
was 25fF which degraded the frequency. Thus, the nal design was implemented with normal
model transistors of IBM 65nm s library.
Power consumption of the VCO cell is 9.2 mW under typical condition operating at 5.5GHz.
VCO Top Level Layout
IBM 65nm process oers a triple well option where a separate p-well can be isolated from the
substrate by a buried n-implant. This buried n-implant is guarded by an n-well ring. Thus,
all the n-wells within the N well ring are shorted that they are all at same potential.
Each delay cell is placed in its separate deep n-well, DNW, and global ground rings are placed
in between each deep n-wells. It is important for the DNW to have a low ohmic connection
to the local supply. From this point, triple contact ring and wide connection metals are used
for local supply and ground connections of DNWs.
There exist a maximum area for DNW in order to keep eectiveness of triple well high. Deep
n-wells of delay cells occupy 31.6X22.145 of area each. Total area of the top level layout
is 151.03X24.54.
For V
dd
and ground connections H-tree routing is used in order to keep the resistive voltage
drop same for each delay cell.
4.6 Divider Performance
High speed frequency dividers are critical parts of frequency synthesizers in wireless systems.
These dividers allow the output frequency from a voltage controlled oscillator to be compared
with a much lower external reference frequency that is commonly used in these synthesizers.
Common trade-os in high frequency dividers are speed of division, power consumption and
occupied area.
74 VCO & Divider
Figure 4.20: VCO delay cell
Figure 4.21: VCO top level layout
4.6 Divider Performance 75
In this work, the most important parameters of the divider are the operating frequency, the
power consumption, and the noise contribution. Since the divider noise is subject to low pass
ltering as explained in Subsection 2.3.2, its in band noise contribution is of importance.
The operating frequency of a digital divider is decided by the propagation delay. For the
divider used in this work, clock is divider by 2 in the 1st stage, and it is followed by a divide-
by-3 circuit as shown in Figure 4.22. In this architecture, the maximum operating frequency
is given in Equation 4.48.
f
max
=
1
2 max(
pLH
,
pHL
)
(4.48)
where
pHL
,
pHL
are the propagation delays of the low-to-high and high-to-low transitions
respectively.
Figure 4.22: Block Schematic of the divider used in this work
Jitter performance of the divider is given in Figure 4.23.
Figure 4.23: Jitter performance of the divider
76 VCO & Divider
Phase noise performance of the divider is given in Figure 4.24. At 1MHz oset from the
carrier, the phase noise is 151.6 dBc/Hz.
Figure 4.24: Divider phase noise performance
Chapter 5
Top Level
The ultimate goal of this research is to complete a 4.9GHz 5.9GHz Wideband PLL fre-
quency synthesizer integrated in IBM 65nm CMOS Digital-Process without any external com-
ponents or processing steps. The division ratio is xed to 6, so the input frequency ranges
from 816MHz 983MHz and the reference signal is supplied from an o chip oscillator.
The required frequency range as being 4.9GHz 5.9GHz in typical conditions and with the
design margins included becomes relatively large. In a wideband ring oscillator PLLs, it is
easy to achieve wide tuning range. However, with wide PLL bandwidth, PLL in band noise
is more important to overall jitter performance. To lower the PLL in band noise, VCO gain,
charge pump, loop lter and divider noise should be reduced. Reducing the VCO gain reveals
a trade of between the wide tuning range and jitter. It gets dicult to cover the required
frequency range within the temperature and process variations. Reducing the charge pump
and loop lter noise requires higher charge pump current, a bigger loop lter capacitance and
a smaller resistance. This trade o leads to a larger die area.
Simulations are veried for various design corners: temperature is swept from 20
o
C to
105
o
C, and all possible device model corners (typical, slow, fast, fastslow) are checked.
5.1 Loop Parameters
The frequency synthesizer block diagram is shown in Figure 5.1. The synthesizer is a 3rd-
order type II charge pump PLL and the design consists of a phase-frequency detector, a
charge-pump loop-lter, a dierential VCO, an output amplier and a frequency divider.
In order to have a stable PLL synthesizer, loop bandwidth should be carefully considered.
The loop-lter shown in Figure 5.2, is a dierential one.
When the loop lter is only consist of C
1
, C
1
introduces a pole to the system and together
with VCO, the loop has two ideal integrators, which makes it a second-order type-two loop.
However, the loop starts with a phase-shift of 180
o
and there is no zero in the loop. Any
high frequency pole introduced by the loop components makes the loop instable. Therefore,
a stabilizing zero is necessary. A resistor R
1
is added in series with the C
1
to introduce a zero
78 Top Level
Figure 5.1: Loop Components
to the loop. The zero should be placed well before the loop bandwidth to achieve sucient
phase-margin. However, the resistor introduces high frequency ripples on the control line,
which are dicult to suppress. As a result, another pole is necessary to suppress these high
frequency components. C
2
introduces a third pole to the system, making the PLL a third-
order type-two loop. This pole should be placed far from the crossover frequency not to
worsen the phase-margin. As a rule of thumb [21], C
2
is chosen to be 1/10th of C
1
. In order
to perform dierential mode operation, C
2
is split into two separate caps and one of them is
placed dierentially between output nodes.
Figure 5.2: Dierential loop lter used in this work
Input frequency is in the range of 816MHz 983MHz. Thus, rst proposal for loop band-
width can be 80MHz in order to keep the ratio between input frequency and loop bandwidth
bigger than 10 for all input frequencies.
Continuous time approximation (s domain analysis) is only valid when the loop bandwidth
is narrow compared to the input frequency. As the loop bandwidth gets comparable with the
input frequency, sampling eects in the loop must be analyzed. As the ratio between the loop
bandwidth and the input frequency is chosen to be bigger than 10, s domain analysis given
in Appendix A is still valid. Thus the relation between the loop bandwidth and cross over
frequency can be given as;
c
= 2
n
2
i
10
(5.1)
The loop lter transfer function is given as;
F(s) =
s
2
+ 1
s
1
(s
3
+ 1)
(5.2)
where
1
= (C
1
+C
2
),
2
= (C
1
R
1
),
3
= (C
1
C
2
R/C
1
+C
2
).
5.1 Loop Parameters 79
The third pole introduced by C
2
is placed far from the crossover frequency, so the loop can
be considered as a 2nd order system, and loop parameters such as damping factor and the
natural frequency can be given as in 2nd order loops;
n
=
_
K
PFD
K
V CO
NC
1
(5.3)
=
1
2
_
K
PFD
K
V CO
R
2
1
C
1
N
(5.4)
The zero frequency introduced by the resistance, R
1
is given as;
z
=

n
2
=
1
R
1
C
1
(5.5)
The location of 3rd pole is;
3
rd =
C
1
+C
2
C
1
C
2
R
1
(5.6)
The loop lter parameter should be chosen in order to satisfy Equation 5.1 within all input
frequency variations, process and temperature variations for K
V CO
and K
PFD
. The worst
case condition, the largest loop bandwidth, is achieved when both NMOS and PMOS devices
operate at fast conditions, and the temperature is 20
o
and the resistor value is maximum
with process variations. In this case, the loop bandwidth is set to 70.528 MHz, In typical
operating conditions loop bandwidth is 54.935MHz.
In Figure 5.3, loop model for frequency domain analyses in Simetrix is given.
Table 5.1: PLL Performance Summary
Technology IBM 65nm
Supply Voltage 1.2V
Reference Frequency Range (MHz) 816 984
Output Frequnecy Range (GHz) 4.01 6.543
PLL Current Consumption VCO 7.72 mA
Divider 2.78 mA
PFD+CP+Additional Circuitry 1.92 mA
PLL Total 12.42 mA
PLL Total Power Consumption 14.904mW
Phase Noise -108dBc @1MHz/-119dBc @5MHz
In Band Noise Floor -121.7dBc/Hz
Settling Time 245ns
Bonding diagram is given in Figure 5.9. Used package is of a Quad Flats No Leads, QFN, type
where the leads do not extend out from the sides of the package. It is placed on board with
Surface Mount Technology, SMT. The package has 24 leads and its body area is 4mm4mm.
80 Top Level
Figure 5.3: Simetrix Model of the Loop
Figure 5.4: Loop AC response in Simetrix
Figure 5.5: Noise Behaviour of the loop in Simetrix
Figure 5.6: Settling Behavior in Fast Corner
82 Top Level
Figure 5.7: Top level Layout - Core Only
Figure 5.8: Top level layout including the pads
84 Top Level
Figure 5.9: bonding diagram
5.2 Wideband PLL Characteristics Validation 85
5.2 Wideband PLL Characteristics Validation
5.2.1 Loop Bandwidth
Loop bandwidth measurement, can be performed using a signal source capable of generating
a frequency modulated signal. This can be directly achieved by feeding a sine a wave, with a
frequency fm, into a VCO. S
V CO
in Figure 5.10 is, then, an FM modulated signal. Obser-
vation of the distortion at the output spectrum includes information of loop bandwidth. As
a result, response of PLL system to this FM modulated signal oers an estimation of loop
bandwidth.
Figure 5.10: Loop bandwidth measurement setup
5.2.2 Phase Noise Measurement and Other Design Metrics
Dierent methods are used to measure phase noise [9]. One involves measuring phase noise L
(fm) directly on a spectrum analyzer. This measurement can be done as long as the analyzer
has better phase noise performance than the measured source.
Other design metrics, such as; Reference Spurs, Frequency stability, can be measured easily
observed with a spectrum analyzer.
Operating frequency Tuning range Due to the time shortage, a voltage buer
for the VCO control voltage could not be implemented. Thus, it is not possible to
perform measurements on control voltage. This is an obstacle that prevents to have an
information on tuning curves thus VCO gain.
Test board of the chip was not yet complete at the time of writing this thesis. Therefore it
has not been shown here.
86 Top Level
Chapter 6
Conclusion and Recommendations
6.1 Conclusions
The goal of this thesis is to review the theory, design and analysis of PLL system compo-
nents and complete a design of 4.9 5.9 GHz CMOS Wideband PLL frequency synthesizer
integrated in IBM 65nm CMOS Digital-Process.
Therefore, to start the investigation noise phenomenon in PLL loops have been analyzed.
Phase noise and jitter performance under noisy power supply conditions have been analyzed.
Noise contributions of each blocks in a PLL system have been studied.
Input reference frequency is in the order of 800MHz that requires a phase frequency detector
which is capable of high frequency operation. A combination of phase frequency detector and
charge pump that operates at high frequencies is implemented.
A number of oscillator types that are congured in multipath loops have been compared
on various performance metrics. A delay cell oering lower phase noise and being suitable
for dierential operation is used in ring VCO design. Since the VCO of the PLL is imple-
mented with a multipath loop ring oscillator; its open loop output noise is undesirably high.
Loop bandwidth,
N
, is set to be 40MHz for the validity of the continuous time (s-domain)
approximation for all process and temperature corners.
Wideband PLL system has been implemented with a xed divide-by-6 divider.
Entire PLL design consumes 14.9 mW under typical conditions. Total area of the PLL core
is 1 mm x 800 um including the pads. Test-chip is being processed.
6.2 Future Work
The future work includes testing the PLL test-chip, and verifying the simulation results,
improving phase noise performance of the PLL design. An LC VCO may be implemented to
improve the phase noise performance, however, rst step is: to verify noise models, and the
measurement techniques.
88 Conclusion and Recommendations
Appendix A
PLL Basics
A.1 PLL Dynamics
A phase-locked loop is a feedback system that operates on the excess phase of nominally
periodic signals. This is in contrast to familiar feedback circuits where voltage and current
amplitudes and their rate of change are of interest. Shown in Figure A.1, a phase-locked loop
contains three basic components;
1. A phase-detector (PD)
2. A loop-lter (LPF)
3. A voltage-controlled oscillator (VCO).
Figure A.1: Basic phase-locked loop block diagram
The phase-detector compares the phase of the input signal, x(t), against the phase of the
VCO output signal, y(t). Output of the phase-detector is a voltage proportional to the phase
dierence between its two inputs. After a certain settling time, the phase remains constant
with time, then the loop is considered to be constant. The dierence voltage at the phase-
detector output is ltered by the loop-lter. Loop-lter is a low pass lter, which suppresses
the high frequency signal components and noise. Output of the loop-lter is applied to the
VCO as the control voltage. This control voltage changes the frequency of the VCO in a
direction that reduces the phase dierence between the input signal and the local oscillator.
90 PLL Basics
A.1.1 Loop Order and Loop Type
In literature, there exist several applications of PLLs where dierent orders and types of
PLLs are used. When the systems loop lter is only consist of a single capacitance, C
1
, C
1
introduces a pole to the system and together with VCO, the loop has two ideal integrators,
which makes it a second-order type-two loop. However, when the loop lter has a stabilization
zero and an additional capacitance in parallel as shown in Figure A.2 then the loop is a 3
rd
order loop.
Figure A.2: Loop lter with stabilization zero
The loop-lter has a pole at = 0 and a zero at
z
= 1/
z
. A zero is necessary for stability
purposes. Using this lter, open-loop transfer function becomes;
G(s) =
K
pfd
K
vco
(s
2
+ 1)
s
2
1
(A.1)
and the loop gain is;
K =
K
pfd
K
vco
1
(A.2)
Closed-loop transfer function is calculated easily as;
out
(s)
in
(s)
=
sK
pfd
K
vco
1
+K
pfd
K
vco
1
1
s
2
+sK
pfd
K
vco
1
+K
pfd
K
vco
1
1
=
sK +
K
2
s
2
+sK +
K
2
(A.4)
However, the third pole introduced by C
2
is placed far from the crossover frequency, so the
loop can be considered as a 2nd order system, and loop parameters such as damping factor
and the natural frequency can be given as in 2nd order loops. The loop lter transfer function
is given as;
A.1 PLL Dynamics 91
F(s) =
s
2
+ 1
s
1
(s
3
+ 1)
(A.5)
where
1
= (C
1
+C
2
),
2
= (C
1
R
1
),
3
= (C
1
C
2
R/C
1
+C
2
).
Natural frequency of the system is given as;
n
=
K
pfd
K
vco
NC
1
(A.6)
Damping ratio of the system is then given by;
=
1
2
_
K
pfd
K
vco
R
2
1
C
1
N
(A.7)
The zero frequency introduced by the resistance, R
1
is given as;
z
=

n
2
=
1
R
1
C
1
(A.8)
The location of 3rd pole is;
3
rd =
C
1
+C
2
C
1
C
2
R
1
(A.9)
A.1.2 Loop response to a step change in phase
This situation occurs due to a phase change in the reference source or due to a sudden change
in the VCO output phase. The magnitude of this change in phase, , occurring at t = 0
can be given in Laplace domain as;
i
(s) =

s
The loop response to such an input can be given as ;
o
(s) = N
2
n
s +
2
n
s(s
2
+ 2
n
s +
2
n
)
(A.10)
Corresponding transient response has dierent settling behavior depending on the of the
system. For the case when equals to 1, response in Equation A.10 can be derived in time
domain as;
o
(s) = N
2
n
s +
2
n
s(s +
n
)
2
= N
_
1
s

1
s +
n
+

n
(s +
n
)
2
_
92 PLL Basics
(A.12)
After the substitution into partial factions, Laplace transform is applied to Equation A.11.
o
(t) = N
_
1 (1
n
t)e
n
t
(A.13)
Thus the phase error
e
(t) can be given as;
e
(t) =

o
(t)
N
= (1
n
t)e
n
t
(A.14)
A.1.3 Loop response to a step change in frequency
In this work, this case occurs when the input reference signal is changed into a dierent band.
Thus the transient changes at loop output and also the maximum allowable frequency step
should be determined. A frequency input step can be considered in Laplace form as;
i
(t) = t
i
(s) =

s
2
Response of a second order system to such a step input is given as;
o
(s) = N
_
1
s
2

1
s(s +
n
)
+

n
s(s +
n
)
2
_
= N
_
1
s
2

1
(s +
n
)
2
_
(A.16)
and with inverse Laplace transform, loop response for a frequency change can be given in
time domain;
o
(t)
N
= t
_
1 e
(
n
t)
_
(A.17)
Transient phase error at the phase detector input, then can be given as;
err
(t) = t

o
(t)
N
= te
n
t
=

n
te
n
t
(A.18)
Peak phase error is then given by the derivative of the curve in Equation A.18 as;
A.1 PLL Dynamics 93
e
(t)
(
n
t)
=

n
_
e
n
t
n
te
n
t
= 0 (A.19)
Equation in A.19 equals to 0 when
n
t = 1, and the peak phase error is given by;
e
(peak) =

e
n
(A.20)
This reveals an important result on maximum operation frequency;
f
o
(max) = 2eNf
n
(A.21)
The phase error expression given in A.19, is dierentiated to obtain a time domain expression
for frequency error;
e
=

err
t
= (1
n
t)e
n
t
(A.22)
In many practical cases the frequency step is much smaller than the one given by Equation
A.22.
94 PLL Basics
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Master of Science Thesis

Wideband PLL System as a Clock

, (nodes are shown in Figure 3.25. The charge injection from

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