1

Kenneth R. Laker, University of Pennsylvania, updated 29Jan08

Three Domain View of VLSI Design Flow at One Level

Verilog
Verilog/Cadence

Extract Parasitic Elements

SPICE (Spectre)

1. Design Rule Check (DRC) 2. Layout Versus Schematic (LVS) Check

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

Cadence (Virtuoso)

(and near neighbor boundaries)

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

(specications) (schematics)
.1. .2. .3. .4. .4. .4. .3. .2. .1. .3. .2. .1.

(layouts)
Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

Hierarchical & Modular 4-bit Adder

c0

add4

b[3:0] a[3:0]

+ + + +
co3 c b a c b a c b a

s[3:0]

add

add

add

add

+
co

carry

carry

carry

sum

carry

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

sum

sum

sum

sum carry

s co

nand
inv

nand

nand

nand

nor

inv

nor

inv

nor

inv

nor

Hierarchical & Modular Layout

c0 b[3:0] a[3:0]

add4 Layout
c0
b[3] (100,400) s[3] (100,300) b[2] a[2] b[1] a[1] b[0] a[0] (0,0)

+ + add4 + +
co3

s[3:0]

a[3]

add[3]

add Cell
(50,100) (0,75) (100,100)

add[2]

s[2] (100,200)

b[i] a[i]

c[i]
(100,50)

add[1] add[0]
co3

s[1] (100,100) s[1] (0,100) (0,25) (0,0)

add[i] s[i]
co[i]
(50,0)

(100,0)

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

Unused die area -> inefcient layout

Structural Hierarchy 1 mapped poorly into Physical Hierarchy.

Better mapping!

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

Miss-mappings between Structural and Physical Hierarchies usually avoided by using automatic layout system.

REGULARITY
DESIGN THE CHIP REUSING AS MANY IDENTICAL MODULES, CIRCUITS, DEVICES AS POSSIBLE. REGULARITY CAN EXIST AT ALL LEVELS OF THE DESIGN HIERARCHY.

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

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LOCALITY (PHYSICAL)
TIME LOCALITY: modules are synchronized by common clock. -> Critical timing paths are kept within module boundaries or within near neighbor boundaries. -> Place modules to minimize large or global inter-module signal routes. -> Care take to realize robust clock generation and distribution. -> Signal routes between modules with large physical separation need sufcient time to traverse route. -> Replicate modules, if necessary, to alleviate delay issues caused by long intermodule signal routes.

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

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Time-to-Market and Design Investment Increasing (for a given application)

Performance Increasing, Die Are Decreasing, Power Dissipation Decreasing (for a given application)

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

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Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

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Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

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Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

Basic FPGA Architecture

I/O Modules

15

Clock Buffer (Configurable Logic Blocks - CLBs) Logic Modules

Segmented Routing Tracks

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

State-of-the-Art FPGA Architecture

Programmable Function Unit (PFU) perform logic, arithmetic, Distributed RAM & ROM functions. Flexible Sys I/O Buffers support LVCMOS, LVDS, etc. Sys Clock PLLs & DLLs for clock management. Embedded 3.125 Gbps SERDES support PCI express, Ethernet.

16

Sys DSP Blocks implement multipliers, adders, subtractors, accumulators. Configuration Port supports SPI, serial and parallel configuration.

http://www.latticesemi.com/products/fpga/ecp2/optimizedfpgaarchitecture.cfm
Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

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Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

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Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

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Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

Package Bonding Techniques

20

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

Package Bonding Techniques

Flip-Chip Bonding

21

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

Summary of Package Types

22

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09

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One System-In-Package Solution

http://www.ansoft.com/leadinginsight/pdf/System%20in%20Package.pdf, slide 15

Kenneth R. Laker, University of Pennsylvania, updated 26Mar09