Beruflich Dokumente
Kultur Dokumente
September 1995
Features
3 Micron Radiation Hardened CMOS SOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) Dose Rate Survivability: >1 x 1012 RAD (Si)/s
Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse Latch-Up Free Under Any Conditions Military Temperature Range: -55oC to +125oC Signicant Power Reduction Compared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels - VIL = 30% of VCC - VIH = 70% of VCC Input Current Levels Ii 5A at VOL, VOH
P3 6 PE 7 GND 8
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW
MR CP P0 P1 P2 P3 PE GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 TE SPE
Description
The Intersil HCS163MS is a Radiation Hardened synchronous presettable binary counter that features lookahead carry logic for use in high speed counting applications. Counting and parallel load, and presetting are all accomplished synchronously with the positive transition of the clock. The HCS163MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS163MS is supplied in a 16 lead Ceramic atpack (K sufx) or a SBDIP Package (D sufx).
Ordering Information
PART NUMBER HCS163DMSR HCS163KMSR HCS163D/Sample HCS163K/Sample HCS163HMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC +25oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample Sample Die PACKAGE 16 Lead SBDIP 16 Lead Ceramic Flatpack 16 Lead SBDIP 16 Lead Ceramic Flatpack Die DB NA
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
220
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7 PE 10 TE 9 SPE 1 MR VCC 2 CP P T0 MR CP D0 Q0 P T1 MR CP D1 Q1 P T2 MR CP D2 Q2 P T3 MR CP D3 Q3 TE TE
14 Q0
13 Q1
12 Q2 Q3
11
15 TC
TRUTH TABLE INPUTS OPERATING MODE Reset (clear) Parallel Load MR l h (Note 3) h (Note 3) Count Inhibit h (Note 3) h (Note 3) h (Note 3) X X CP PE X X X h l (Note 2) X TE X X X h X l (Note 2) SPE X l l h (Note 3) h (Note 3) h (Note 3) PN X l h X X X OUTPUTS QN L L H Count Qn Qn TC L L (Note 1) (Note 1) (Note 1) L
H = HIGH Voltage Level L = LOW Voltage Level h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial q = Lower case letter indicate the state of the referenced output prior to the LOW-to-HIGH clock transition = LOW-to-HIGH clock transition NOTES: 1. The TC output is HIGH when TE is HIGH and the counter is at terminal count (HLLH for 162 and HHHH for 163) 2. The HIGH-to-LOW transition of PE or TE on the 54/74163 and 54/74160 should only occur while CP is high for conventional operation 3. The LOW-to-HIGH transition of SPE or MR on the 54/74163 should only occur while CP is high for conventional operation
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Specications HCS163MS
Absolute Maximum Ratings
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under Absolute Maximum Ratings may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under Electrical Performance Characteristics are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at 4.5 VCC (TR, TF) . . . . . . . .100ns Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2, 3 Output Current (Sink) IOL VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V , (Note 2) VCC = 4.5V, VIH = 4.5V, VOUT = VCC - 0.4V, VIL = 0V, (Note 2) VCC = 4.5V, VIH = 3.15V, IOL = 50A, VIL = 1.35V VCC = 5.5V, VIH = 3.85V, IOL = 50A, VIL = 1.65V Output Voltage High VOH VCC = 4.5V, VIH = 3.15V, IOH = -50A, VIL = 1.35V VCC = 5.5V, VIH = 3.85V, IOH = -50A, VIL = 1.65V Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND 1 2, 3 1 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC, +125oC, -55oC MIN 4.8 4.0 -4.8 -4.0 MAX 40 750 0.1 UNITS A A mA mA mA mA V
SYMBOL ICC
IOH
VOL
1, 2, 3
0.1
1, 2, 3
1, 2, 3
1 2, 3
0.5 5.0 -
A A -
FN
7, 8A, 8B
1. All voltages referenced to device GND. 2. Force/Measure functions may be interchanged. 3. For functional tests, VO 4.0V is recognized as a logic 1, and VO 0.5V is recognized as a logic 0.
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Specications HCS163MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9 10, 11 Propagation Delay CP to TC TPHL, TPLH VCC = 4.5V 9 10, 11 Propagation Delay TE to TC TPHL, TPLH VCC = 4.5V 9 10, 11 NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. LIMITS TEMPERATURE +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN 2 2 2 2 2 2 MAX 26 31 29 34 21 23 UNITS ns ns ns ns ns ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) CONDITIONS VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC = 5.0V, VIH = 5.0V, VIL = 0.0V, f = 1MHz VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V VCC = 4.5V, VIH = 4.5V, VIL = 0.0V LIMITS TEMPERATURE +25oC +125oC, -55oC MIN 16 24 20 30 12 18 10 15 13 20 3 3 0 0 15 22 30 24 MAX 68 83 10 10 UNITS pF pF pF pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
SYMBOL CPD
Input Capacitance
CIN
TW
TW
TSU
TSU
Setup Time MR to CP
TSU
Hold Time Pn to CP
TH
TH
TREM
FMAX
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
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Specications HCS163MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K RAD LIMITS PARAMETER Supply Current Output Current (Sink) SYMBOL ICC IOL (NOTES 1, 2) CONDITIONS VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V VCC = 4.5V, VIN = VCC or GND, VOUT = VCC -0.4V VCC = 4.5V , VIH = 3.15, VIL = 1.35V, IOL = 50A VCC = 5.5V, VIH = 3.85, VIL = 1.65V, IOL = 50A Output Voltage High VOH VCC = 4.5V, VIH = 3.15V, VIL =1.35V, IOH = -50A VCC = 5.5V, VIH = 3.85V, VIL =1.65V, IOH = -50A Input Leakage Current Noise Immunity Functional Test Propagation Delay CP to Qn Propagation Delay CP to TC Propagation Delay TE to TC NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC. 3. For functional tests VO 4.0V is recognized as a logic 1, and VO 0.5V is recognized as a logic 0. IIN FN VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, (Note 3) VCC = 4.5V TEMPERATURE +25oC +25oC MIN 4.0 MAX 0.75 UNITS mA mA
IOH
+25oC
-4.0
mA
VOL
+25oC
0.1
+25oC
0.1
+25oC
+25oC
+25oC +25oC
5 -
A -
+25oC
31
ns
VCC = 4.5V
+25oC
34
ns
VCC = 4.5V
+25oC
23
ns
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP 5 5
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Specications HCS163MS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate group A testing in accordance with method 5005 of MIL-STD-883 may be exercised. TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. METHOD 5005 PRE RAD 1, 7, 9 POST RAD Table 4 READ AND RECORD PRE RAD 1, 9 POST RAD Table 4 (Note 1) METHOD 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 100%/5004 Sample/5005 Sample/5005 Sample/5005 Sample/5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 7, 9 Subgroups 1, 2, 3, 9, 10, 11 ICC, IOL/H, IOZ./H READ AND RECORD ICC, IOL/H, IOZ./H ICC, IOL/H, IOZ./H ICC, IOL/H, IOZ./H
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR OPEN GROUND 1/2 VCC = 3V 0.5V VCC = 6V 0.5V 50kHz 25kHz
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2) NOTES: 1. Each pin except VCC and GND will have a resistor of 10K 5% for static burn-in 2. Each pin except VCC and GND will have a resistor of 1K 5% for dynamic burn-in 4, 6, 8 11 - 15 1, 3, 5, 7, 9, 10, 16 2 -
NOTE: Each pin except VCC and GND will have a resistor of 47K 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
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Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger and Load Circuit
INPUT VIH VS TW
AC VOLTAGE LEVELS PARAMETER VCC VIH VS VIL GND HCS 4.50 4.50 2.25 0 0 UNITS V V V V V PARAMETER VCC VIH VS VIL GND
DUT
TEST POINT CL RL
DUT
TEST POINT CL RL
CL = 50pF RL = 500
CL = 50pF RL = 500
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TC P0
Q0 P1
Q1
P2
Q2 P3
Q3 PE
GND
SPE
TE
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask series for the HCS163 is TA14348A.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certication.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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