EXPERIMENT NO.

AIM:

STUDY OF TANNER TOOLS

THEORY: Tanner Tools Tanner EDA is a suite of tools for the design of integrated circuits. Tanner EDA is mainly used to analyze circuits at switch level & gate level.These are tool used to enter schematics, perform SPICE simulations, do physical design (i.e., chip layout), perform design rule checks (DRC) and layout versus schematic (LVS) checks. Tanner EDA Design Tools S-edit - a schematic capture tool T-SPICE - the SPICE simulation engine integrated with S-edit L-edit - physical design tool W-edit - waveform formatting

S-EDIT S-Edit is a powerful design capture & entry tool that can generate netlists directly usable in T-Spice simulations. It provides an integrated environment for editing circuits, setting up and running simulations and probing the results. It also provides the ability to perform SPICE simulations of the circuit. These circuits that can be driven forward into a physical layout.

L-EDIT L-edit refers to Flexible to do micromachining design, PCB layout, and other CAD work. L-Edit/DRC it indentifies any design faults(widths, spacing, overlaps),Layout EDITor L-Edit/Extract- generates a circuit " which is used for SPICE simulation netlist "

W-EDIT It is not just a waveform viewer but a robust analysis tool Built-in measurements like max, min, average, intersect, rms, over/undershoot, amplitude, error, crossing, delay, frequency, rise/fall time, settling time, duty cycle, slew rate, etc. It has easy measurement methods by selecting traces & applying options.

T-SPICE It is a complete design capture and simulation solution that provides accuracy. The role of T-Spice is to help design and verify a circuit operation. T-Spice simulation results allow circuit designers to verify and fine-tune designs before submitting them for fabrication. It performs fast, accurate simulations for analog and mixed-signal IC designs and fully supports foundry models for reliable and accurate simulations.

TYPES OF ANALYSIS DC Operating Point Analysis DC Transfer Analysis Transient Analysis AC Analysis

DC operating point analysis finds the circuit steady-state condition. DC Transfer Analysis is used to study the voltage or current at a set of points in a circuit as a function of the voltage or current at another set of points. This is done by sweeping the source variables. AC Analysis characterizes the circuit behaviour dependence on small signal input frequency. Transient Analysis provides information on how circuit elements vary with time.

LATEST VERSION Windows: Version 15.22(XP, Vista, Win 7) Linux (RHEL): Version 15.22

EXPERIMENT NO. 2
AIM: TO DESIGN NMOS TRANSISTOR AND TO STUDY ITS I-V CHARACTERISTICS THEORY: The metaloxidesemiconductor field-effect transistor (MOSFET) is a transistor used for amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gate electrode can induce a conducting channel between the two other contacts called source and drain. The channel can be of n-type or p-type, and is accordingly called an nMOSFET or a pMOSFET. Figure shows the schematic diagram of the structure of an nMOS device before and after channel formation.

g. (1a): nMOSFET before channel formation

Fig. (1b): nMOSFET structure after channel form

CODE: *VI Plot NMOS M1 2 1 0 0 NMOS W=1U L=0.18U v1 1 0 1.8v vds 2 0 1.8v .dc vds 0 1.8 0.02 sweep v1 0 1.8 0.3 .include "C:\Documents and Settings\student\Desktop\MODEL_0.18.md"

.print i(M1) .probe .end

CONCLUSION: The characteristics of an NMOS transistor can be explained as follows. Three regions of operation: - Cut-off mode: MOSFET: VGS < VT , VGD < VT with VDS > 0. - Linear or Triode mode: MOSFET: VGS > VT , VGD > VT , with VDS > 0. - Saturation mode: : MOSFET: VGS > VT , VGD < VT (VDS > 0).

EXPERIMENT-3

AIM: TO DESIGN PMOS TRANSISTOR AND TO STUDY ITS I-V CHARACTERISTICS THEORY: The metaloxidesemiconductor field-effect transistor (MOSFET) is a transistor used for amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gate electrode can induce a conducting channel between the two other contacts called source and drain. The channel can be of n-type or p-type, and is accordingly called an nMOSFET or a pMOSFET. Figure shows the schematic symbol of the structure of an pMOS device before and after channel formation.

CODE:
***PMOS** M1 3 2 1 1 PMOS L=0.18U W=1u ps = 20 pd = 4 .include "C:\Documents and Settings\Administrator\Desktop\180nm.md" vgs 2 1 DC -1.8v vds 3 1 DC -1.8v .DC vds 0.0 -1.8v -0.2 sweep vgs 0 -1.8v -0.2 .probe .print dc .end I(M1)

CONCLUSION: The characteristics of a PMOS transistor can be explained as follows. Three regions of operation: -Cut-off-mode: MOSFET: VGS VT , Id=0. -Linear or Triode mode: MOSFET: VGS < VT , VDS > VGS-VT. -Saturation mode: MOSFET: VGS < VT and VDS VGS-VTH

EXPERIMENT NO. 4

AIM: TO DESIGN A CMOS INVERTER AND STUDY ITS DC CHARACTERISTICS THEORY: CMOS is also sometimes referred to as complementary-symmetry metaloxide semiconductor. The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn while the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without pchannel devices.

CODE: M1 3 1 2 2 PMOS L=0.18U W=2u ps = 20 pd = 4 M2 3 1 0 0 NMOS L=0.18U W=4U ps = 20 pd = 4 VDD 2 0 1.8V c1 3 0 0.01nf *V3 3 0 V1 1 0 1.8V **.TRAN 500PS 20PS

.DC V1 0.0 1.8 0.002 .PROBE .PRINT DC v(1) v(3) .PRINT DC I(M2) .PRINT DC P(VDD) **.print dc p(c1) .END

CONCLUSION: Here we have shown the status of both NMOS and PMOS transistor in all the regions of the characteristics. We can also draw the characteristics, starting with the VI characteristics of PMOS and NMOS characteristics.

EXPERIMENT-5: AIM: TO DESIGN CMOS INVERTER USING NMOS AS DRIVER & ENHANCEMENT NMOS TRANSISTOR AS LOAD USING SPICE &COMPARE THE DC TRANSFER CHARACTERSTICS AND POWER DISSIPATION LEVEL OF CMOS INVERTER USING SPICE. THEORY: It consists of two opposite polarity MOSFETs the NMOS and the PMOS with their gates connected together at the input; the applied voltage is denoted by An NMOS-PMOS group with a common gate is called a complementary pair, which gives us the C in CMOS., the complementary pair forms the basis for CMOS logic circuits. The inverter output voltage is taken from the common drain terminals. The transistors are connected in a manner that ensures that only one of the MOSFETs conducts when the input is table at a low or high voltage; this is due to the use of the complementary arrangement.

CODE:
m1 2 2 3 0 nmos L=0.18U W=0.5U ps = 20 pd = 4 m2 3 1 0 0 nmos L=0.18U W=0.5U ps = 20 pd = 4 VDD 2 0 1.8V c1 3 0 0.01nf *V3 3 0 V1 1 0 1.8V .include "C:\Documents and Settings\Administrator\Desktop\180nm.md" .DC V1 .probe .print .PRINT .PRINT .end 0.0 1.8 0.002 DC V(1) V(3) DC I(M2) DC P(VDD)

CONCLUSION:
The DC characteristics of the inverter are portrayed in the voltage transfer characteristic, which is a plot of Vout as a function of Vin. This is obtained by varying the input voltage Vin in the range from 0 to VDD and finding the output voltage Vout. The VTC for the circuit is obtained by starting with an input voltage of Vin =0v and then increasing it up to a value of Vin =VDD. This results in the plot shown in the characteristic graph.

EXPERIMENT NO-6

AIM: TO STUDY THE EFFECT ON DC TRANSFER CHARACTERISTICS OF A CMOS INVERTER BY

CHANGING THE W/L RATIO OF THE TRANSISTORS

THEORY: CMOS is also sometimes referred to as complementary-symmetry metaloxide

semiconductor. The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn while the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without pchannel devices.

CODE:
M1 3 1 2 2 PMOS L=0.18U W=1u ps = 20 pd = 4 M2 3 1 0 0 NMOS L=0.18U W=0.5U ps = 20 pd = 4 VDD 2 0 1.8V c1 3 0 0.01nf *V3 3 0 V1 1 0 1.8V **.TRAN 500PS 20PS .DC V1 0.0 1.8 0.002

.PROBE .PRINT DC v(1) v(3) .PRINT DC I(M2) .PRINT DC P(VDD) **.print dc p(c1) .END

When PMOS L=0.18U W=2.5u

NMOS L=0.18U W=2U

CONCLUSION: By increasing the width of pull-up transistor the dc transfer characteristics are shifted to the right and by increasing the width of the pull down transistor characteristics are shifted to the left.

EXPERIMENT-7 AIM: TO DESIGN NAND GATE IN CMOS TECHNOLOGY AND SIMULATE THE CHARACTERSTICS USING SPICE. THEORY: Nand Gate is the basic gate and it is also referred as Universal Gate. The output is low
whenever both inputs are high and high otherwise. In case of the NAND gates the PMOS were in parallel and the NMOS were in series. The MOSFETs act as switches. When both inputs are high, the n-MOSFETs switch on to connect the output to ground. If either input is low, the path to ground is cut off, and one of the p-MOSFETs switches on to connect the output to +5V. The schematic diagram is shown below:

CODE:
***nand Gate*** mn1 mn2 mn3 mn4 4 4 4 5 2 3 2 3 1 1 5 0 1 1 0 0 pmos pmos nmos nmos w=5u w=5u w=5u w=5u l=0.18u l=0.18u l=0.18u l=0.18u

C1 4 0 0.1p Vdd 1 0 dc 5v va 2 0 PULSE (5 0 0 1n 1n 10n 20n)

vb 3 0 PULSE (5 0 0 1n 1n 15n 30n) .include "C:\Documents and Settings\Administrator\Desktop\180nm.md" .tran 0.1ns 40ns .probe .power vdd .print tran v(2) v(3) .print tran v(4) **.print p(Va) .end

CONCLUSION: The I-V characteristics are also obtained for the four different modes. Transient characteristics of the NAND gate has been successfully verified.

EXPERIMENT-8 AIM: TO DESIGN NOR GATE IN CMOS TECHNOLOGY AND SIMULATE THE CHARACTERSTICS USING SPICE. THEORY: Nor Gate is the basic gate and it is also referred as Universal Gate.
A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. In case of the NOR gates the PMOS are in series and the NMOS in parallel. PMOS will be switched on when Vout is connected to Vcc. PMOS will be switched off when Vout is not connected to Vcc. The schematic diagram is shown below:

CODE:
***nor Gate*** mn1 mn2 mn3 mn4 1 5 4 4 2 3 2 3 5 4 0 0 1 1 0 0 pmos pmos nmos nmos w=5u w=5u w=5u w=5u l=0.18u l=0.18u l=0.18u l=0.18u

C1 4 0 0.1p Vdd 1 0 dc 5v va 2 0 PULSE (5 0 0 1n 1n 10n 20n) vb 3 0 PULSE (5 0 0 1n 1n 14n 30n) .include "C:\Documents and Settings\Administrator\Desktop\180nm.md" .tran 0.1ns 40ns .probe .power vdd .print tran v(2) v(3) .print tran v(4) **.print p(Va) .end

CONCLUSION: Transient characteristics of the NOR gate has been successfully verified.