Network Syncronization

Distinguished Lecturers Program
Synchronization of Digital Telecommunications Networks

Stefano Bregni
Politecnico di Milano Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32, 20133 Milano MI Tel. 02-2399.3503 - Fax 02-2399.3413 E-mail: bregni@elet.polimi.it
Lecture Outline
Synchronization processes in telecommunications A historical perspective on network synchronization Synchronization networks
Introduction 2
Stefano Bregni
Synchronization Processes in Telecommunications
Synchronization Processes in Telecommunications 1
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Carrier Synchronization
coherent demodulation of an amplitude-modulated signal is based on the recovery of the carrier, i.e. on the recovery of a signal with coherent phase and frequency with the original carrier
x ( t ) = s (t ) cos 2 f0 t
x (t ) cos 0 t = s(t ) cos 2 0 t =

phase error
s( t ) 1 + cos 2 0 t 2
s (t ) 2
cos
frequency error
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Symbol Synchronization
Clock Recovery
recovery of the timing signal associated to a received digital signal
channel equalization filter
r(t)
sampler
r(kT)
symbol decision
1011
t=kT
symbol synchronizer (clock recovery)
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Timing Signal and Significant Instants
s (t ) = A(t ) sin (t )
(t ) =
1 d (t ) 2 dt
T = 1/0
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Frame Synchronization
once that the received bits have been identified, it is necessary to determine the beginning and the end of code words or of groups of code words (frames)
bit semantics
frame frame
101011010001010100101011011110101010110010010101110110001011101001101100101
t
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Bit Synchronization
synchronization of an asynchronous bit stream according to a local clock mapping of tributaries into a PDH multiplex signal (with bit justification) mapping of tributaries into SDH VCs (with or without bit justification) synchronization and frame boundary alignment of PCM multiplex signals at inlets of a digital switching exchange (with slip buffering)
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Bit Synchronizer
scheme of principle
any frequency offset between writing and reading yields, sooner or later, to buffer underflow ( bit repetition) or overflow ( bit loss)
input signal to synchronize
circular buffer
output signal synchronized
slip
slips are deadly!
write address
read address
clock recovery fw
write counter
read counter fr equipment clock

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Packet Switching
peculiarities
packet switching can be efficient to integrate real-time and data traffic (e.g., ATM, IP) packets are delivered with random inter-arrival times packets can be even delivered out of sequence at the receiver, it is not 1 2 3 4 5 6 7 8 9 possible to recover exactly the source frequency, based only on the received bit flow 2 3 5 4 6 8 9 7 1
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Packet Synchronization
effective transport of voice and video and circuit emulation are possible by means of equalization of random packet delivery delays (packet jitter) techniques to rebuild the original bit rate from the received packet sequence asynchronous network
nodes are timed by independent clocks roundtrip delay measurement adaptive strategies
synchronous network
nodes are timed by some network synchronization facility Synchronous Residual Time Stamp (SRTS) is standardized for ATM circuit emulation (AAL-1) (ATM is not suited for an asynchronous environment!)
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Network Synchronization
distribution of time and frequency over a network of clocks, spread over an even wide geographical area, by using the communication links among them goal: to make all network elements to operate synchronously possible applications synchronization of transmission and switching networks synchronization of networks based on some form of TDMA array antennas
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network synchronization is ubiquitous
Examples of Synchronization of a Large Number of Oscillators in Nature

synchronous fireflies (W. C. Lindsey, J. Buck and E. Buck) they flash their light organs at regular but individual and independent intervals if they are not close together if many of them are placed in a relatively close proximity, they exhibit a synchronization of their light organs until they flash in unison synchronization of individual fibers in heart muscles to produce the familiar heartbeat
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Synchronization of Real-Time Clocks

a different kind of network synchronization real-time clocks supply the system time within equipment example: date and time in a PC the distribution of the national standard time is to the purposes of network control and management all events reported to the equipment monitoring system (faults, defects, BER threshold overflowing, line alarms, etc.) must be accompanied by their recording time to allow their correlation example: 23 Dec 1998, 01.32.04 AM
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Multimedia Synchronization
integration of heterogeneous elements such as text, images, audio and video in a multimedia communications time-dependency of data sequences may be simply linear, as in the case of an audio file played on a sequence of images (slide presentation with soundtrack), but other modes of data presentation are also viable, including reverse, fast-forward, fast-backward and random access when non-sequential storage, data compression and random communication delays are introduced, the provision of such capabilities can be very difficult
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A Historical Perspective on Network Synchronization
A Historical Perspective on Network Synchronization 1
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Synchronization in Analog FDM Networks

Single-Side-Band demodulation must be coherent carrier synchronization can follow a point-to-point strategy (i.e., limited to each single transmission system) in simple networks AT&T made up the first synchronization network of history for its long-distance FDM analog transmission network in the '70s locally, PLL-based carrier supplies generated all reference frequencies used by multiplexers and demultiplexers at all hierarchical levels carrier supplies were synchronized by distributing pilot frequencies derived from a network master clock free-run frequency accuracy requested to limit distortion in the demodulated signals was in the order of 1e-7
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Advent of Digital Multiplexing

Plesiochronous Digital Hierarchy (PDH)
plesiochrony means synchronization anarchy all clocks are autonomous only the frequency offset tolerance is specified asynchronous digital multiplexing allows multiplexing of asynchronous tributaries with substantial frequency offsets
bit justification
PDH networks do not need synchronization
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Advent of Digital Switching

the advent of digital TDM techniques yielded a progressive integration of transmission and switching the PCM frame allows switching time slots (TS) moving octets from one TS to another is possible only if PCM signals are exactly synchronized with frame starts aligned
equipment clock
bit synchronization at inputs of digital switching exchanges

input asynchronous PCM frames
bit and frame synchronizer switching fabric PCM frames synchronized output PCM frames synchronized and switched
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Impact of Slips on Digital Services

studies reported throughout the '70s and the '80s describe the effects of slips on services of various kind
uncompressed voice (POTS) compressed voice group 3 facsimile data transmitted on POTS channel (voiceband modem) digital video transmission data transport protocols encrypted services only a little percentage of slips leads to occasional audible clicks in the reproduced audio a slip leads an audible click a slip can wipe out several scan lines a slip may cause a drop out lasting from 10 ms to 1.5 s a slip may cause segments of the picture to be distorted or frames to freeze for periods of up to 6 s slips reduce transmission throughput a slip may result in the loss of the encryption key
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PDH systems are transparent to the timing of transported signals
Timing Transfer through a PDH Transmission Chain

PDH transmission chain
8 Mb/s PDH MUX PDH MUX PDH MUX 34 Mb/s 140 Mb/s PDH MUX 34 Mb/s PDH MUX 8 Mb/s PDH MUX
2 Mb/s
2 Mb/s
clock timing transfer asynchronous multiplex signal with timing signal embedded
Fundamental Law of Digital Transmission Chains

ALL BITS THAT GET IN ON ONE SIDE MUST GET OUT FROM THE OTHER
Digital Exchange master clock
other digital signals
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Synchronization of Digital Switching Exchanges across PDH Links

point-to-point timing transfer
2 Mb/s
Digital Exchange
2 Mb/s
Digital Exchange
PDH MUX
PDH MUX
master clock
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Synchronization of Digital Switching Exchanges Served by SASE Clocks across PDH Links
Digital Exchange
2 Mb/s
2 Mb/s
Digital Exchange
PDH MUX
PDH MUX 2 MHz
2 MHz
SASE
master clock
SASE
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Synchronization and SDH/SONET Digital Transmission

SDH networks are usually synchronized to avoid any pointer action pointer adjustments can yield excessive jitter on demapped tributaries some equipment is designed to minimize this issue
enhanced pointer processor enhanced synchronizer/desynchronizer
it is anyhow advisable to synchronize SDH networks to avoid problems in multi-vendor PDH/SDH networks SDH technology allows a more effective timing transfer between offices contrary to PDH, in SDH networks timing should not be carried on signals mapped in STM-N frames
Stefano Bregni
Synchronization of Digital Switching Exchanges Served by SASE Clocks across SDH Links
Digital Exchange
2 Mb/s
SDH transmission chain

SDH MUX STM-N SDH MUX
2 Mb/s
Digital Exchange
2 MHz
2 MHz
SASE
master clock
2 MHz
SASE
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Is ATM Really Asynchronous?

source #1 source #2
popular misunderstanding Asynchronous Transfer Mode refers to how information is transferred, not to the physical network
source #3 source #4 source #5 source #6 source #1 source #2 source #3 source #4 source #5 source #6
Asynchronous Transfer Mode (ATM)
Synchronous Transfer Mode (STM)
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Synchronization in ATM Transport Networks

synchronization plays an essential role in ATM networks in particular in the integration of ATM equipment into existing telecommunications networks ATM equipment requires synchronization to support Constant Bit Rate (CBR) services, based on AAL type 1 (SRTS cell synchronization) to support synchronous physical interfaces
PCM (E1: 2.048 Mb/s, DS1: 1.544 Mb/s) SDH/SONET (155.520 Mb/s and higher)
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Synchronization of ATM Equipment

synchronization of modern ATM equipment is accomplished through dedicated ports (2.048 MHz, ITU-T G.703/13) the most straightforward way of synchronizing an ATM NE is to integrate it into a synchronization network ATM equipment should take the timing from SASE/BITS accuracy of timing no burden of avoiding timing loops (duty of the synchronization network manager) if no synchronization network is available, then line-timing is the only feasible way of synchronizing synchronization is supplied via SDH, E1 or DS1 signals care must be taken to avoid timing loops
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Synchronization of Cellular Mobile Wireless Telephone Networks

wireless networks pose specific synchronization requirements BTS, BSC and MSC need to be synchronized to ensure slip-free interconnection at trunk lines BTS needs to be synchronized to ensure frequency stability on the on-air wireless channels GSM and TDMA (USA) systems frequency synchronization CDMA (IS-95 USA) system also precise time synchronization
to PSTN
MSC
trunk lines
trunk lines
BSC
trunk lines
trunk lines
BTS
air interface
BTS BTS
air interface air interface
BTS
air interface
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Synchronization Requirements of Cellular Networks

CDMA, GSM and TDMA specifications require frequency stability to avoid that centre frequencies of on-air channels drift and thus no co-channel interference no problems at hand-off from one cell to another CDMA (IS-95 USA) specifications require also time stability to keep pilot sequences in all cells well aligned and thus no problems at hand-off from one cell to another new services will require even stricter frequency and time stability locating mobile handsets third generation wireless systems (UMTS) ATM and backhaul radio can be used as transport technology among BTS, BSC and MSC do not feature a good timing transparency
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Synchronization Networks
Synchronization Networks 1
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Network Synchronization Goals

to align the absolute time scales of network nodes time synchronization
nodes are synchronous with same total phase synchronization of real-time clocks for date and time (NTP)
to align the significant instants of timing signals of network nodes aside from a constant phase error frequency synchronization with phase control but with no need to compensate average delays of synchronization signals
nodes are synchronous but with different total phases (PLL) no pointer action no slips
to make equal the frequencies of network nodes frequency synchronization without phase control
nodes are mesochronous (FLL) there may be pointer action and slips (phase random walk)
Stefano Bregni
Synchronization Network
the facility implementing network synchronization nodes autonomous clock
stand-alone device able to generate a timing signal, starting from some periodic physical phenomenon
slave clock
device that generates a timing signal having phase (or much less frequently frequency) locked to a reference timing signal at its input
links communication channels among nodes

digital circuits analog channels connections at higher OSI levels
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Issues of Timing Distribution

tactics of point-to-point timing transfer
how to transfer timing from one node to another the main techniques have been described presenting the historical evolution of network synchronization
strategy of network synchronization

how to organize timing distribution to all the nodes of the network higher-level issue
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Full Plesiochrony
Anarchy
no-synchronization strategy anarchy is the easiest form of government, but it relies on the good behavior of the single elements all network clocks are autonomous the synchronization of processes in different nodes is entrusted to the accuracy of clocks
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Master-Slave Synchronization
Despotism
distribution of the timing reference from one master clock to all the other slave clocks of the network directly or indirectly star topology tree topology despotism is generally considered as unethical, but it is certainly effective in ensuring a tight control on the slaves what happens should the master fail?
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Mutual Synchronization
Democracy
based on the direct, mutual control among clocks meshed topology complexity of the dynamic system control extremely reliable
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Mixed Mutual/Master-Slave Synchronization

Oligarchy
mutual synchronization strategy is adopted for a few network core clocks master-slave strategy is adopted for the peripheral clocks
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Hierarchical Mutual Synchronization

Hierarchical Democracy
w1
generalization of democratic strategy some count more than others do each of N network nodes is given a relative weight wi
w2
w5
0 wi 1,
iN
w3
wi = 1
w4
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Hierarchical Master-Slave Synchronization

Hierarchical Despotism
variant of the pure MS strategy alternate synchronization routes for protection if the master fails, another clock takes its place according to a hierarchical plan static pre-selected protection routing table dynamic protection via Synchronization Status Messages (SSM) the most widely adopted to synchronize modern digital telecommunications networks
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Mixed Plesiochronous/Synchronous Networks

Independent Despotic States
it appears how difficult is to lock all Administrations to a supranational timing reference GPS is not accepted as first-choice primary reference by many national Administrations for political reasons national synchronous HMS networks are plesiochronous in relation to the others
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Synchronization Network Standard Architectures

ITU-T, ETSI, ANSI
all based on the hierarchical master-slave strategy (HMS) at level 0 one (or more, for reliability) network master clock generates the network reference signal, by running in autonomous mode at lower levels 1, 2, etc. network slave clocks
are synchronized by the signals coming from the upper level synchronize the clocks at lower levels
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ITU-T/ETSI Reference Architecture
Clock Types in Synchronization Networks

Primary Reference Clock (PRC) network master clock: autonomous clock or based on GPS/LORAN-C Synchronization Supply Unit (SSU) function represents the building clock (network slave clock) accepts synchronization inputs from external sources filters the timing signal derived from this selected source may use an internal timing source (hold-over) distributes the filtered timing signal to other elements within the node physical implementation: Stand-Alone Synchronization Equipment (SASE) SDH Equipment Clock (SEC)
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Intra-Node Timing Distribution

within nodes containing a SSU/SASE (e.g., PSTN offices)
logical star topology centered on the SSU within the node, all network element clocks are synchronized by the SSU short-distance links ITU-T G.703 signals 2.048 Mb/s 2.048 MHz
node boundary
SEC SEC SEC
SSU
SEC
SEC
SEC
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The BITS/SASE Concept

the clock designated to time all other clocks in the office ITU-T/ETSI: Stand-Alone Synchronization Equipment (SASE) ANSI: Building Integrated Timing Supply (BITS) some operators rely on clocks equipping large switches or DCXs for the BITS/SSU function, but good practice suggests using dedicated equipment BITS/SASE should receive two or more references from other locations intra-node timing distribution dedicated E1/DS1 signals at 2.048/1.544 Mb/s (ITU-T G.703) analog sine-wave 2048 kHz signal (ITU-T G.703) Clock Distribution Unit and Synchronous Clock Insertion Unit (AT&T) other (1544 kHz, 8 kHz, Composite Clock 64 kHz + 8 kHz in USA etc.)
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Inter-Node Timing Distribution

among nodes containing a SSU/SASE
tree topology standard HMS architecture timing is transferred from one node to another along synchronization trails SSU the facilities of PDH/SDH transmission networks can be used synchronization trails may SSU SSU contain SECs
PRC
SSU
SSU
SSU
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Synchronization Network Reference Chain

N SECs PRC SSU 1
transit node
N SECs SSU K-1

transit node
N SECs SSU K
transit or local node
N SECs
up to N=20 SECs cascaded between any two SSUs up to K=10 SSUs in one chain total number of SECs in one chain limited to 60
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ANSI Reference Architecture
Clock Hierarchy Based on Performance Levels: Strata

Primary Reference Source (PRS) (analogous to PRC) frequency accuracy better than 11e-11 GPS or LORAN-C Stratum-1 clock (e.g., Cesium-beam atomic clock) Stratum-2 clock (analogous to transit-node SASE) frequency accuracy better than 1.61e-8 Stratum-3 clock (analogous to local-node SASE) frequency accuracy better than 4.61e-6 Stratum-3E clock (specific for SONET networks with improved short-term stability) Stratum-4 e Stratum-4E clock (specific for customer-premises equipment) frequency accuracy better than 3.21e-5
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Synchronization Network Protection

clocks are duplicated and can recover timing from at least two alternate diversely-routed synchronization trails clocks recover timing only from clocks of upper or equal level a priority scheme must be established to select the reference in case of fault switching criteria: hard failure detection
LOS, AIS, LOF, Ex-BER, LOP
soft failure detection

frequency offset out-of-mask MTIE/TDEV
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Synchronization Status Messages (SSM)

defined by ITU-T, ETSI and ANSI SSMs are quality-markers embedded within digital signals that are used as synchronization sources the originating node declares the quality of the synchronization source to which its signal is traceable SSMs allow clocks to select the best synchronization source (i.e., that one declaring the best quality) among the available references according to a priority scheme their main purpose is to avoid timing loops compatible with most network topologies point-to-point, linear, mesh or ring topologies
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SSM Defined by ITU-T/ETSI
0000 0010 0100 1000 1011 1111
Quality unknown PRC (ITU-T Rec. G.811) SASE transit node clock (ITU-T Rec. G.812) SASE local node clock (ITU-T Rec. G.812) Synchronous Equipment Timing Source (SETS) (ITU-T Rec. G.813) Do not use for synchronization
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Transmission of SSM
on PDH systems transport via E1 signal (2.048 Mb/s) SSMs are inserted in one of TS0 bits 4-8 of odd frames (without alignment word): bit Sa4, Sa5, Sa6, Sa7, Sa8 usually, the bit Sa4 is used over a multiframe of 4 basic frames A1 A1 A1 A2
RSOH
A2 A2 J0 F1 D3 K2 D6 D9 D12
B1 D1
E1 D2
on SDH systems transport via STM-N SSMs are inserted in bits 5-8 of byte S1 within MSOH
AU pointer B2 B2 B2 K1 D4
MSOH
D5 D8 D11
D7 D10
S1 Z1 Z1 Z2 Z2 M1 E2
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Distinguished Lecturers Program

Synchronization of Digital Telecommunications Networks

Distinguished Lecturers Program

Synchronization processes in telecommunications A historical perspective on network synchronization Synchronization networks

Distinguished Lecturers Program

Synchronization Processes in Telecommunications

Synchronization Processes in Telecommunications 1

Distinguished Lecturers Program

x (t ) cos 0 t = s(t ) cos 2 0 t =

Synchronization Processes in Telecommunications 3

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channel equalization filter

Synchronization Processes in Telecommunications 4

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Timing Signal and Significant Instants

Distinguished Lecturers Program

Distinguished Lecturers Program

Synchronization Processes in Telecommunications 8

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input signal to synchronize

output signal synchronized

read counter fr equipment clock

Distinguished Lecturers Program

Distinguished Lecturers Program

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Synchronization Processes in Telecommunications 13

Distinguished Lecturers Program

network synchronization is ubiquitous

Examples of Synchronization of a Large Number of Oscillators in Nature

Synchronization Processes in Telecommunications 14

Distinguished Lecturers Program

Synchronization of Real-Time Clocks

Synchronization Processes in Telecommunications 15

Distinguished Lecturers Program

Synchronization Processes in Telecommunications 17

Distinguished Lecturers Program

A Historical Perspective on Network Synchronization

A Historical Perspective on Network Synchronization 1

Distinguished Lecturers Program

Synchronization in Analog FDM Networks

Distinguished Lecturers Program

Advent of Digital Multiplexing

PDH networks do not need synchronization

A Historical Perspective on Network Synchronization 4

Distinguished Lecturers Program

Advent of Digital Switching

bit synchronization at inputs of digital switching exchanges

A Historical Perspective on Network Synchronization 6

Distinguished Lecturers Program

Impact of Slips on Digital Services

A Historical Perspective on Network Synchronization 7

Distinguished Lecturers Program

PDH systems are transparent to the timing of transported signals

Timing Transfer through a PDH Transmission Chain

Fundamental Law of Digital Transmission Chains

Digital Exchange master clock

other digital signals

A Historical Perspective on Network Synchronization 5

Distinguished Lecturers Program

Synchronization of Digital Switching Exchanges across PDH Links

PDH transmission chain

A Historical Perspective on Network Synchronization 8

Distinguished Lecturers Program

point-to-point timing transfer