PRELAB 3 REPORT EE 271 Group 3

Instructor: Nguyen The Nghia Student: - Doan Thanh Thien - Nguyen Van Trong - Huynh Minh Hai

Problem: we have to design a system which will control the traffic light at a junction where the Highway and Country Road intersect each other. Requirements: we have a sensor in country road which will detect whether the road has cars or not. When the sensor is activated (detect cars in country road) the light in Highway will change from green to yellow then to red and the light in country road will change from red to green. There is some delay time when go from this state to another state and we should can control that delay. In this project we use 5sec delay for Red Red state and 3sec delay for Yellow Red state.

Analysis problem: - According to the requirements above we see that state machine is the most suitable method for solving this problem. - We will divide it into 5 states: State 0(S0): the light in Highway will be green and in Country Road will be Red. State 1(S1): the light in Highway will be changed to yellow and the light in Country Road is still Red State 2 (S2): the light in Highway will be Red and the light in Country Road now is changed to Green. State 3 (S3): the light in Highway is still Red; the light in Country Road now is turned into Yellow. From all above we can build a truth table:

State S0 S1 S2 S3

HwG 1 0 0 0

HwY 0 1 0 0

HwR 0 0 1 1

FwG 0 0 1 0

FwY 0 0 0 1

FwR 1 1 0 0

State S0 S1 S2 S3 State Machine Diagram

Highway Green Yellow Red Red

Country Road Red Red Green Yellow

S0
0

S3
0 1

S1 S2

Algorithm description: Variables description: - We will use : 6 L.E.Ds (HwR, HwG, HwY, FwR, FwG, FwY)to display : + Highway: Red, Green, Yellow + Country Road: Red, Green, Yellow X: active high, use to detect whether have car in country road or not. Count: 3 bit control time delays (counting depends on clock ) State: 3 bit to save the current and next state. Reset: active high, used to reset program. CODE:

1/ Clock Design: module clock_design (clock_in, resetn, clock_out); input clock_in, resetn; output clock_out; wire [31:0] clk; parameter which_clock = 1; clock_divider cdiv (clock_in, reset, clk); assign clock_out = clk[which_clock]; assign reset = ~resetn; endmodule module clock_divider (clock, reset, divided_clocks); input clock, reset; output reg [31:0] divided_clocks = 0; always @(posedge clock, posedge reset) begin if(reset) divided_clocks <= 0; else divided_clocks <= divided_clocks + 1; end endmodule //Testbench module clock_design_tb; reg clk_in_tb; reg resetn_tb; //Initialize value of clock initial begin clk_in_tb = 1; resetn_tb = 0; #10 resetn_tb = 1; #20 resetn_tb = 0; #50 resetn_tb = 1; end //Clock generator always begin: CLOCK_GENERATOR #1 clk_in_tb = ~clk_in_tb; //Toggle clock every 5 ticks end clock_design myClock(clk_in_tb, resetn_tb, clk_out_tb); endmodule

2/ Delay: module signal(Time, Active, resetn, clk,Sig, display); output reg Sig; output reg [13:0] display; input clk, resetn, Active; input [4:0] Time; reg [4:0] count; assign reset = ~resetn; always @(posedge clk, posedge reset) begin if(reset || Active == 0) begin // setting the initial value count = 0; Sig = 0; display = 0; end else begin if(count < Time - 1) begin count = count + 1; Sig = 0; end else begin Sig = 1; count = 0; end display[13:7] = (Time - count) / 10; // This is first digit of 7-seg LED display[6:0] = (Time - count) % 10; // This is second one end end endmodule //Testbench //Included : module Display module delay_tb; wire [0:13] display_tb; wire clk_out_tb; wire Sig_tb; wire [0:6] HEX1_tb, HEX0_tb; reg [4:0] Time_tb; reg Active_tb; reg clk_in_tb; reg resetn_tb; //Initialize value of clock initial begin clk_in_tb = 1; resetn_tb = 0; #5 resetn_tb = 1; Active_tb = 0; Time_tb = 0;

#20 Time_tb = 10; Active_tb = 1; #50 resetn_tb = 0; #50 resetn_tb = 1; #300 Active_tb = 0; #20 Time_tb = 22; Active_tb = 1; end //Clock generator always begin: CLOCK_GENERATOR #5 clk_in_tb = ~clk_in_tb; //Toggle clock every 5 ticks end clock_design myClock(clk_in_tb, resetn_tb, clk_out_tb); delay myDelay(Time_tb, Active_tb, resetn_tb, clk_out_tb, Sig_tb, display_tb); led7segs myLed7segs(display_tb, HEX1_tb, HEX0_tb); endmodule

3/ Led 7 segments module led7segs(decimal, HEX1, HEX0); // This module is to display 2 BCD on 2 7-segment LEDs output reg [0:6] HEX1, HEX0; input [13:0] decimal; //Behavior of led7segs HEX[1] always @(decimal[13:7]) begin case (decimal[13:7]) 4'b0000: HEX1 = 7'b0000001; // 0 4'b0001: HEX1 = 7'b1001111; 4'b0010: HEX1 = 7'b0010010; 4'b0011: HEX1 = 7'b0000110; 4'b0100: HEX1 = 7'b1001100; 4'b0101: HEX1 = 7'b0100100; 4'b0110: HEX1 = 7'b0100000; 4'b0111: HEX1 = 7'b0001111; 4'b1000: HEX1 = 7'b0000000; 4'b1001: HEX1 = 7'b0000100; //default: HEX1 = 7'b1111111; // All led off endcase end //Behavior of led7segs HEX[0] always @(decimal[6:0]) begin case (decimal[6:0]) 4'b0000: HEX0 = 7'b0000001; // 0 4'b0001: HEX0 = 7'b1001111; 4'b0010: HEX0 = 7'b0010010;

// // // // // // // // //

1 2 3 4 5 6 7 8 9

// //

1 2

4'b0011: 4'b0100:

HEX0 = 7'b0000110; HEX0 = 7'b1001100;

// //

3 4

4'b0101: HEX0 = 7'b0100100; 4'b0110: HEX0 = 7'b0100000; 4'b0111: HEX0 = 7'b0001111; 4'b1000: HEX0 = 7'b0000000; 4'b1001: HEX0 = 7'b0000100; //default: HEX0 = 7'b1111111; endcase end endmodule

//

// 5 // 6 // 7 // 8 // 9 All led off

4/ Traffic: module Traffic(clk, X, reset, Sig, out,state, Active, numdelay); input clk, X, reset; output reg [0:5] out; output reg [0:1] state; wire clkin, display; output reg Active; output reg [0:4] numdelay; output Sig; parameter zero=0, one=1, two=2, three=3, delay01 = 7, delay12 = 5, delay23 = 7, delay30 = 5; //clock_design myclk(clkin, reset, clk); //delay mydelay(numdelay, Active, reset, clkout, Sig, display);

always @(state) begin case (state) zero: out = 6'b010100; one: out = 6'b001100; two: out = 6'b100010; three: out = 6'b100001; default: out = 6'b010100; endcase end always @(negedge reset or posedge clk ) begin if (reset==0) begin

state <= zero; {numdelay} = 0; Active = 0; end else case (state) zero: begin if (X==1) begin Active = 1; {numdelay} = delay01; if (Sig == 1) begin state<= one; numdelay = delay12; Active = 0; end end else state <= zero; end one: begin if(Sig == 0) begin Active = 1; {numdelay} = delay12; end else begin state <= two; numdelay = delay23; Active = 0; end end two: if (X==1) state <= two; else begin if (Sig == 0) begin Active = 1; {numdelay} = delay23; end else begin state <= three; Active = 1; numdelay = delay30; end end three: if (Sig == 0) begin Active = 1;

numdelay = delay30; end else begin state <= zero; Active = 0; numdelay = 0; end endcase end endmodule

module Traffic_tb; reg X_in_tb; wire [0:5] out_tb; wire [0:1] state_tb; wire [0:13] display_tb; wire clk_out_tb; wire Sig_tb; wire [0:6] HEX1_tb, HEX0_tb; wire [4:0] Time_tb; wire Active_tb; reg clk_in_tb; reg resetn_tb; //Initialize value of clock initial begin X_in_tb = 1; clk_in_tb = 1; resetn_tb = 0; #5 resetn_tb = 1; #350 X_in_tb = 0; end //Clock generator always begin: CLOCK_GENERATOR #2 clk_in_tb = ~clk_in_tb; //Toggle clock every 2 ticks end clock_design myClock(clk_in_tb, resetn_tb, clk_out_tb); delay myDelay(Time_tb, Active_tb, resetn_tb, clk_out_tb, Sig_tb, display_tb); led7segs myLed7segs(display_tb, HEX1_tb, HEX0_tb); Traffic myTraffic(clk_out_tb, X_in_tb, resetn_tb, Sig_tb, out_tb, state_tb, Active_tb, Time_tb); endmodule