DEPARTMENT OF BIOMEDICAL ENGINEERING MODEL QUESTION PAPER

ANALOG AND DIGITAL ICS

Answer ALL Questions PART A (10 x 2 = 20 Marks) 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. What is differential amplifier? List the important characteristics of an ideal Op - Amp. What are the different types of ADC? Define capture range. Define the following: Minterm and Maxterm. Define switching function. What is PLA? How its differ from ROM? Differentiate decoder and encoder. Draw a logic diagram of counters. List out the various types of flip-flop. PART B (5 x 12 = 60 Marks) 11. a. (i) Draw the circuit of inverting and non inverting amplifiers using Op Amp and derive an expression for their gain. (ii) What is virtual ground? Explain with a neat circuit diagram.

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11.b. (i) With neat diagram explain the working principle of an instrumentation amplifier using Op - amp. (ii) Explain in detail about V to I converter and I to V converter.

12.a . (i) Explain the operation of D/A converter and give some of the Advantages and Disadvantages. (ii) Derive the expression for lock range of PLL.

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12.b. (i) Draw and explain the working principle of op-amp based voltage controlled oscillator circuit. (ii) Explain in detail about successive approximation DAC. 13.a. (i) Convert the following (37)10 to equivalent hexadecimal. (ii) Perform (4)10 - (9)10 using the 2s complement method. (iii) Minimize the Boolean expression: AB + ABC + ABC + ABC (iv) Explain De Morgans theorem and the duality principle with proof.

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13.b. (i) Reduce the following function using Karnaugh map technique. f ( A, B, C , D ) = m(5, 6, 7,12,13) + d (4,9,14,15) (ii) Minimise the following expression in the POS form f ( A, B, C , D) = M (0, 2,3,8,9,12,13,15) (iii) Simplify the Boolean expression Y = AB + A ( B + C ) + B ( B + C ) 14.a. (i) Design of half adder and full adder using gates. (ii) Design the logic circuit for odd parity checker. (iii) Draw and explain the block diagram of PLA.

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14.b. (i) Explain in detail about parallel binary adder with neat block diagram. (ii) Give the comparison between PROM, PLA and PAL . (iii) Design a 3 to 8 Decoder using gates. (iv) Draw the logic diagram of BCD to Excess 3 code converter.

15.a. (i) Distinguish between combinational and sequential logic circuits. (ii) Explain in detail SR & D flip-flop with neat circuit diagram.

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15.b (i) Distinguish between synchronous and asynchronous sequential counter. (ii) Explain in detail JK & T flip-flop with neat circuit diagram (iii) Briefly explain about Ring counter with neat block diagram.