Migration From AT89C51SND1C to AT83C51SDN1C

This application note details the differences between AT89C51SND1C and AT83C51SDN1C products, and gives some tips and tricks to the user when migrating from Flash to ROM product from a hardware and firmware point of view.

MP3 Microcontrollers

Application Note

Rev. 4244AMP305/03

Memory Architecture
AT83C51SDN1C Memory Architecture

The AT83C51SND1C product provides the internal program/code memory in ROM memory while the AT89C51SND1C product provides it in Flash memory. Figure 1. ROM Memory Architecture
FFFFh

64K Bytes User ROM Memory

0000h

As shown in Figure 1 the AT83C51SDN1C ROM memory is composed of only one user space detailed as follows. User Space This space is composed of a 64K Bytes ROM memory programmed during the manufacturing process. It contains the users application code. Figure 2. Flash Memory Architecture
Hardware Security Extra Row
FFFFh FFFFh F000h

AT89C51SND1C Memory Architecture

4K Bytes Flash Memory

Boot

64K Bytes User Flash Memory

0000h

As shown in Figure 2 the AT89C51SND1C Flash memory is composed of four spaces detailed as follows. User Space This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128 Bytes. It contains the users application code. This space can be read or written by both software and hardware modes. Boot Space This space is composed of a 4K Bytes Flash memory. It contains the bootloader for InSystem Programming and the routines for In Application Programming. This space can only be read or written by hardware mode using a parallel programming tool. Hardware Security Space This space is composed of one Byte: the Hardware Security Byte (HSB) divided in 2 separate nibbles. The MSN contains the X2 mode configuration bit and the Bootloader

AT8xC51SND1C Application Note

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AT8xC51SND1C Application Note

Jump Bit and can be written by software while the LSN contains the lock system level to protect the memory content against piracy and can only be written by hardware. Extra Row Space This space is composed of 2 Bytes: The Software Boot Vector (SBV). This Byte is used by the software bootloader to build the boot address. The Software Security Byte (SSB). This Byte is used to lock the execution of some bootloader commands.

User Constraints

Due to its ROM technology, the AT83C51SND1C product does not allow In-System and In-Application Programming and therefore, does not implement any boot space, hardware security space and extra row space. Attempting to enable the boot memory through software or hardware boot condition will result in no effect. Then, jumping to the boot entry address (F000h) will jump in internal user ROM. Software boot condition ENBOOT bit in AUXR1 register (see Table 1) is not implemented in AT83C51SDN1C product.
User must take care not to write to ENBOOT bit. User must take care to leave this pin unconnected.

No Boot Space or Extra Row Space

Note:

ISP pin (see Figure 3) is not implemented in AT83C51SDN1C product.

Note:

Hardware Security Space

Since the HSB register (see Table 3) is not implemented, the AT83C51SND1C product does not provide any programmable hardware security system. Internal ROM content is always secured because there is no way to read it externally. Moreover the AT83C51SND1C product does not implement X2B bit in HSB disallowing to start automatically in X2 mode.
Note: User must take care to always set the X2 bit in CKCON register by firmware in the application start-up routine if needed.

Version Register

The AT83C51SND1C product NVERS register (see Table 2) is set to 0XXX XXXXb (ROM product) while it is set to 1XXX XXXXb in the AT89C51SND1C product.
Note: User must take care of NVERS register usage in its code to avoid any infinite loop that may have been implemented to secure firmware from old product versions usage.

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Pinout

Figure 3. AT8xC51SND1C 80-pin QFP Package

P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 ALE ISP/NC(1) P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PVDD FILT PVSS VSS X2 X1 TST UVDD UVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

AT89C51SND1C-RO (Flash) AT83C51SDN1C-RO (ROM)

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD

Note:

1. ISP for AT89C51SND1C, NC for AT83C51SDN1C. Do not connect this pin when using AT83C51SDN1C.

AT8xC51SND1C Application Note

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D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

AT8xC51SND1C Application Note

Registers
Table 1. AUXR1 Register AUXR1 (S:A2h) Auxiliary Register 1
7 6 Bit Mnemonic 5 ENBOOT 4 3 GF3 2 0 1 0 DPS

Bit Number 7-6

Description Reserved The value read from these bits are indeterminate. Do not set these bits. Enable Boot Flash Set this bit to map the boot Flash in the code space between at addresses F000h to FFFFh. Clear this bit to disable boot Flash. Reserved The value read from this bit is indeterminate. Do not set this bit. General Flag This bit is a general-purpose user flag. Always Zero This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. Reserved for Data Pointer Extension. Data Pointer Select Bit Set to select second data pointer: DPTR1. Clear to select first data pointer: DPTR0.

ENBOOT

(1)

GF3

DPS

Reset Value = XXXX 00X0b

Note: 1. This bit is not implemented in AT83C51SDN1C product. Do not set this bit.

Table 2. NVERS Register (Read Only) NVERS (S:FBh) Version Register

7 V7 Bit Number 7-0 6 V6 5 V5 4 V4 3 V3 2 V2 1 V1 0 V0

Bit Mnemonic Description V0:7 Value of these bits depends on hardware version.

Reset Value = 0XXX XXXXb (AT83C51SDN1C) or 1XXX XXXXb (AT89C51SND1C)

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Table 3. HSB Byte Hardware Security Byte

7 X2B Bit Number 6 BLJB 5 4 3 2 LB2 1 LB1 0 LB0

Bit Mnemonic Description X2B(1) X2 Bit Program this bit to start in X2 mode. Unprogram (erase) this bit to start in standard mode. Bootloader Jump Bit Program this bit to execute the bootloader at address F000h on next reset. Unprogram (erase) this bit to execute users application at address 0000h on next reset. Reserved The value read from these bits is always unprogrammed. Do not program these bits. Reserved The value read from this bit is always unprogrammed. Do not program this bit. LB2:0 Hardware Lock Bits Refer to for bits description.

BLJB

5-4

2-0

Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase.
Notes: 1. On AT89C51SND1C X2B initializes the X2 bit in CKCON during the reset phase. 2. Bits 0 to 3 (MSN) can only be programmed by hardware mode.

AT8xC51SND1C Application Note

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