447551215

8
2
REV
C
1
ECN
0000813234
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
DESCRIPTION OF REVISION
PRODUCTION RELEASED
CK APPD DATE
2009-11-01
K84 MLB SCHEMATIC

PROD OK2FAB 11/01/2009
D
(.csa) Date (.csa) Date (.csa) Date
D
Page
TABLE_TABLEOFCONTENTS_HEAD
Page
Contents
1
Sync
01/19/2009
Page
49
Contents
SMC
50
Sync
04/02/2009 K24_MLB 02/04/2009
TABLE_TABLEOFCONTENTS_ITEM
Contents
101
Sync
04/06/2009 K24_MLB 03/30/2009 K24_MLB 04/06/2009
1
Table of Contents
2
K24_MLB 01/19/2009
36 37
71
102
Memory Constraints MCP Constraints 1

103
2
System Block Diagram

3
K24_MLB
SMC Support
51
K24_MLB 02/15/2009
72 73
01/19/2009
3
Power Block Diagram

4 01/19/2009
38
52 K24_MLB 01/19/2009
LPC+SPI Debug Connector K84 SMBUS CONNECTIONS

53
K24_MLB
MCP Constraints 2
104
K24_MLB 04/06/2009
4
BOM Configuration
5
39 40
01/19/2009
K24_MLB 04/06/2009
74
106
Ethernet Constraints SMC Constraints

107
K24_MLB 04/06/2009 K24_MLB 01/19/2009
5
Revision History
6
K24_MLB
VOLTAGE SENSING
54
K24_MLB 01/27/2009
75 76
02/04/2009
6
Revision History
7
K24_MLB 02/04/2009
41
55
Current Sensing Thermal Sensors

56
K24_MLB
K84 SPECIAL CONSTRAINTS

109
K24_MLB 01/19/2009
7
FUNC TEST
8
K24_MLB 02/04/2009
42 43
02/04/2009
K24_MLB 04/06/2009
77
03/04/2009
K84 RULE DEFINITIONS
K24_MLB
8
Power Aliases
9
K24_MLB
Fan
57
K24_MLB
9
SIGNAL ALIAS
10
K24_MLB 04/06/2009
44
58
WELLSPRING 1 WELLSPRING 2
59
K24_MLB 02/25/2009 K24_MLB 03/04/2009
10
CPU FSB
11
K24_MLB 04/06/2009
45 46
03/30/2009
11
CPU Power & Ground

12
K24_MLB
SMS
60
K24_MLB 02/25/2009
12
CPU Decoupling
13
K24_MLB
47
02/25/2009 61
DEBUG SENSORS AND ADC SPI ROM

62
K19_IMLB 02/15/2009 K24_MLB 06/09/2009
13
eXtended Debug Port(MiniXDP)

14
K24_MLB
48
04/06/2009
14
MCP CPU Interface

15
K24_MLB
49
04/06/2009 63
AUDIO: CODEC/REGULATOR AUDIO: LINE INPUT FILTER

65
AUDIO 06/09/2009 AUDIO 06/09/2009
15
MCP Memory Interface

16
K24_MLB 04/06/2009
50 51
04/06/2009
16
MCP Memory Misc

17
K24_MLB
AUDIO: HEADPHONE FILTER

66
AUDIO 06/09/2009
17
MCP PCIe Interfaces

18
K24_MLB 04/06/2009
52
67
AUDI0: SPEAKER AMP AUDIO: JACK

68
AUDIO 06/09/2009 AUDIO 06/09/2009
18
MCP Ethernet & Graphics

19
K24_MLB 04/06/2009
53 54
04/06/2009
19
MCP PCI & LPC

20
K24_MLB
AUDIO: JACK TRANSLATORS

69
AUDIO 02/05/2009
20
MCP SATA & USB

21
K24_MLB 03/24/2009
55
70
DC-In & Battery Connectors PBUS Supply/Battery Charger

72
K24_MLB 02/05/2009 K24_MLB
21
MCP HDA & MISC

22
K24_MLB 04/06/2009
56 57
04/06/2009
22
MCP Power & Ground

25
K24_MLB
5V/3.3V SUPPLY
73
23
MCP Standard Decoupling

26
K24_MLB 04/06/2009
58
74
1.5V/0.75V DDR3 SUPPLY

03/03/2009
24
MCP Graphics Support

28
K24_MLB 02/15/2009
59
75
IMVP6 CPU VCore Regulator MCP CORE REGULATOR

76
K24_MLB 02/15/2009 K24_MLB 02/04/2009
25
SB Misc
29
K24_MLB 04/06/2009
60 61
02/05/2009
26
FSB/DDR3 Vref Margining

31
K24_MLB
CPU VTT(1.05V) SUPPLY

77
K24_MLB 03/24/2009
27
DDR3 SO-DIMM Connector A

32
K24_MLB 02/05/2009
62
78
MISC POWER SUPPLIES POWER SEQUENCING

79
K24_MLB 02/15/2009 K24_MLB 02/15/2009
28
DDR3 SO-DIMM Connector B

33
K24_MLB 04/06/2009
63 64
01/27/2009
29
DDR3 Support
34
K24_MLB
POWER FETS
90
K24_MLB 02/15/2009
30
X16 WIRELESS CONNECTOR

37
K24_MLB 04/06/2009
65
93
LVDS CONNECTOR DISPLAYPORT SUPPORT

94
K24_MLB 04/06/2009 K24_MLB 04/06/2009
31
Ethernet PHY (RTL8211CL)

38
K24_MLB 04/06/2009
66 67
04/06/2009
32
Ethernet & AirPort Support

39
K24_MLB
DisplayPort Connector
97
K24_MLB 02/09/2009
33
ETHERNET CONNECTOR
45
K24_MLB 01/19/2009
68
98
LCD Backlight Driver (MC34845) LCD Backlight Support

100
VEMURI_K19I 04/06/2009 K24_MLB 04/06/2009
34
SATA Connectors
46
K24_MLB
69
02/05/2009
35
External USB Connectors
K24_MLB
70
CPU/FSB Constraints
K24_MLB
A
DRAWING TITLE
A
SCHEM,MLB,K84
Schematic / PCB #s
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
PART NUMBER
051-7982 820-2567
QTY
1 1
DESCRIPTION
SCHEM,MLB,K84 PCBF,MLB,K84
REFERENCE DES
SCH PCB
CRITICAL
CRITICAL CRITICAL
BOM OPTION
C.0.0
BRANCH PAGE
NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
1 OF 109
SHEET
1 OF 77
6
U1000
5
U1300
3
J6950,J6900
INTEL CPU CORE 2 DUO

2.26 GHZ PENRYN
XDP CONN
PG 13
DC/BATT CONN
PG 55
DC-DC POWER SUPPLIES

PG 56-64
PG 10
FSB
D
PG 14
J5800
64-Bit 1067 MHZ
TRACKPAD
PG 45
U5515,U5535 J3100,J3200
2 SODIMMS MAIN
GPIOs
FSB INTERFACE MEMORY DDR3 1067MHZ
CPU & MCP THERMAL SENSORS
DIMM
PG 15,16 PG 42 PG 27,28
U5920
SUDDEN MOTION SENSOR

PG 46
Misc
CLK
PG 21
U6100
SPI Boot ROM

PG 48
SYNTH
CURRENT & VOLTAGE SENSORS

PG 53,54,60
J5601
J4501
SATA Conn
PG 34
SPI
FAN CONN AND CONTROL

PG 43
PG 21
HD
J4500
NVIDIA
U4900
SATA Conn
PG 34
B,0
BSA
ADC
Fan
Ser
J5100
SATA
PG 20
MCP79 B03
SMC
LPC
Prt
LPC Conn Port80,serial

PG 38
H8S/2117
PG 36,37
C
J9000
ODD
PG 19
U1400
LVDS CONN
LVDS OUT
PWR
CTRL
PG 65
RGB OUT
J3401 J5800 J9000 J4600,4610
DP OUT
J9400
Bluetooth
HDMI OUT
PG 30
TRACKPAD/ CAMERA KEYBOARD
EXTERNAL USB 2.0

Connectors
PG 65 PG 35
MINI DISPLAY PORT CONN
PG 45
DVI OUT (UP TO 12 DEVICES)
PG 67
TMDS OUT
USB
1 UP TO 20 LANES3
PG 18
PG 20
PCI-E
PG 17
B
SMB
PG 21
RGMII
PG 18
PCI
(UP TO FOUR PORTS)
PG 19
HDA
DIMMS
PG 21
MIKEY
SMC
U6201
Audio Codec CIRRUS LOGIC CS4206

PG 49
U6500
HEADPHONE/LINE OUT Amp

U6610,U6620,U6630 U3700 PG 51
LINE-IN
GIGABIT
MIC
Speaker
U6700
SYNC_MASTER=K24_MLB
PAGE TITLE
SYNC_DATE=01/19/2009
10/100/1000M E-NET
RTL8211CL
PG 31
Amps
PG 52
LINE-IN/LINE OUT MUX

PG 53
System Block Diagram

DRAWING NUMBER SIZE
Apple Inc.
J3401 J3900
051-7982
REVISION
MINI PCI-E E-NET AirPort Conn

PG 30 PG 33
C.0.0
BRANCH PAGE
J6700,J6701,J6702,J6703,J6704

Audio Conns
PG 53
2 OF 109
SHEET
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
K84 POWER SYSTEM ARCHITECTURE

PP18V5_DCIN_CONN
D6905
02
PPVIN_G3H_P3V42G3H
ENABLE
D6905
PBUS_VSENSE
3.425V G3HOT LT3470

VOUT
PP3V42_G3H_REG
03
SMC RESET "BUTTON" NCP303LSN
04
D
01
CHGR_EN (S5)
ENABLES
7A FUSE PPVBAT_G3H_CHGR_REG F7000 PPBUS_G3H
U6990
U5000
Q5315
PPCPUVCORE_VTT_ISNS_R
23 02
VIN
0.01 OHM
R5492
PPCPUVCORE_VTT_ISNS
PPVIN_S0_CPUVTTS0
CPUVTTS0_EN (S0)
PPCPUVTT_S0_REG
EN_PSV VOUT
F6905
CPUVTT
(1.05V)
(7.2A MAX CURRENT)
AC ADAPTER IN
6A FUSE DCIN(16.5V)
VIN VOUT
TPS51117 U7600
PGOOD
MCP79
PWRBTN*
06-1
PBUS SUPPLY/ BATTERY CHARGER ISL6258AHRTZ U7000

J6950
IMVP_VR_ON 3S2P Q7050 BATT_POS_F
PPVBAT_G3H_CHGR_OUT
31
CPUVTTS0_PGOOD
PLTRST* RSMRST*
LPC_RESET_L
PPVIN_S5_CPU_IMVP
01 02
V
CPU VCORE
VOUT VIN
SMC_CPU_VSENSE PPVCORE_S0_CPU_REG (44A MAX CURRENT)
MCP_PS_PWRGD
PS_PWRGD
CPU_PWRGD
29 26
U2850
CPUPWRGD(GPIO49)
30
CPU_RESET# FSB_CPURST_L
ISL9504BCRZ U1400
VR_ON PGOOD
28
VR_PWRGOOD_DELAY U7400
(9 TO 12.6V)
25
06
P1V05ENET_EN
1.05V SO
FETS
(Q3841,Q3840)
PP1V05_ENET_FET 22
4.5V AUDIO TPS71745 VIN PP4V5_AUDIO_ANALOG
VOUT
CPU
PWRGOOD
C
RESET*
CHGR_BGATE
PPVIN_S3_5VS3/PPVIN_S5_3V3S5
EN
1.05V (S5)
EN
U6200
06
VIN ISL8009B
PP1V05_S5_REG
VOUT
U1000
MCP79
PM_SLP_S4_L
32
PP5V_S3_REG Q7940 PP5VRT_S0_FET
11
11-1
P3V3S3_EN
RC DELAY
P1V05_S5_EN 02
U7750
08
SMC
15
SLP_S3#
11-3 P16
U4900
04
SMC_PM_G2_EN P60
P5VS3_EN_L
Q7800
VIN
EN1
5V
(RT)
VOUT1
PP5V_S3_REG
(10A MAX CURRENT)
PP5V_S3
17
P5VS0_EN Q7948
U1400
RC DELAY
DDRREG_EN
(S5) PP3V42_G3H_REG
05
VOUT2
PP3V3_S5_REG
EN2
PP3V3_S5 Q7910 PP3V3_S3_FET
P3V3S5_EN_L
3.3V TPS51125
(4A MAX
CURRENT)
07
PP5VLT_S0_FET
PCI_RESET0#
15-1
11-2
PPBUS_S0_LCDBKLT_PWR
02
SMC_PM_G2_EN
VIN EN0
U7200
VREG3
13
P5VS0_EN
RC DELAY
P5VS3_EN_L MC34845 U9700
PGOOD1,2
P3V3S3_EN
P5V3V3_PGOOD
PPVOUT_S0_LCDBKLT VOUT
B
AP_PWR_EN SMC_ADAPTER_EN Q3801,Q3805
OR GATE Q3801,Q3805 NAND GATE
04-1
24 16
Q7930
ALL_SYS_PWRGD
SMC
RSMRST_OUT(P15)
10
PM_RSMRST_L
IMVP_VR_ON
18
PP3V3_S0_FET
PWRGD(P12)
99ms DLY
IMVP_VR_ON(P16)
25
PM_WLAN_EN_L
P3V3S0_EN Q3810 P3V3_ENET_FET
09
RSMRST_PWRGD SMC_ONOFF_L
RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90)
PM_SLP_S3_L
05
P17(BTN_OUT)
PM_PWRBTN_L SMC_RESET_L
15
RST*
P1V05S0_LDO_PGOOD P5V3V3_PGOOD
P3V3ENET_EN_L SLP_S5_L SLP_S5_L(P95) SLP_S4_L SLP_S4_L(P94) SLP_S3_L SLP_S3_L(P93)
MCPCORESO_PGOOD CPUVTTS0_PGOOD
PP3V3_S0_PWRCTL
PPVIN_S5_1V5S30V75S0 02
VIN
S3 TO S0 PP1V5_S0_FET FETS
(Q7901 & Q7971)
PP1V5_S0
21
1.8V LDO
TPS62202
S0PGOOD_PWROK
U4900
PP1V8_S0_REG
19-1
=DDRREG_EN PM_SLP_S3_L
1.5V
S5 S3
VOUT1
PP1V5_S3_REG (13A MAX CURRENT)
U7760
=DDTVTT_EN
0.75V
VOUT2
14
PP3V3_S0
RST*
V1 V2 V3
PP0V75_S0_REG (1A MAX CURRENT)
PP1V5_S0 PP1V05_S0
RC DELAY
P1V8S0_EN
16-4
TPS51116 U7300
LTC2909 U7870
A
PAGE TITLE
20
RC DELAY
MCPDDR_EN
16-2 RC DELAY
P3V3S0_EN
MCP_CORE
16-3
PPMCPCORE_S0_R
VOUT
R7525 PPMCPCORE_S0_REG
Power Block Diagram

DRAWING NUMBER SIZE
MCPCORES0_EN
EN
(13A MAX CURRENT)

R
Apple Inc.
051-7982
REVISION
RC DELAY
CPUVTTS0_EN
16-6
16-1
ISL6263D BRANCH
C.0.0
PAGE
PBUSVSENS_EN U7500 (S0)
PPVIN_S0_MCPCORE
16-1
RC DELAY
MCPCORES0_EN
16-5
P5VS0_EN (S0)
VIN
3 OF 109
SHEET
02
8
BOM Variants
7
BOM NAME
PCBA,MLB,FOX DDR CONN,K84 PCBA,MLB,MLX DDR CONN,K84 K84 MLB DEVELOPMENT BOM PCBA,MLB,FOX DDR CONN,PVT K84 PCBA,MLB,MLX DDR CONN,PVT K84 K84 MLB DEVELOPMENT PVT
6
TABLE_BOMGROUP_HEAD
5
Bar Code Labels / EEE #s
TABLE_BOMGROUP_ITEM
4
PART NUMBER QTY
1 1 1 1
3
REFERENCE DES
[EEE:8CG] [EEE:A36] [EEE:CXR] [EEE:CY1]
2
BOM OPTION
EEE_8CG EEE_A36 EEE_CXR EEE_CY1
BOM NUMBER
639-0035 639-0254 085-0748 639-0554 639-0555 085-1076
BOM OPTIONS
K84_COMMON,CPU_2_0GHZ,FOX_DDR_CONN,EEE_8CG
TABLE_BOMGROUP_ITEM
DESCRIPTION
LBL,P/N LABEL,PCB,28MM X 6 MM
CRITICAL
CRITICAL CRITICAL CRITICAL CRITICAL
K84_COMMON,CPU_2_0GHZ,MLX_DDR_CONN,EEE_A36 826-4393
TABLE_BOMGROUP_ITEM
K84_DEVEL_ENG 826-4393
TABLE_BOMGROUP_ITEM
K84_COMMON_PVT,CPU_2_0GHZ,FOX_DDR_CONN,EEE_CXR 826-4393
TABLE_BOMGROUP_ITEM
K84_COMMON_PVT,CPU_2_0GHZ,MLX_DDR_CONN,EEE_CY1 826-4393
TABLE_BOMGROUP_ITEM
K84_DEVEL_PVT
BOM Groups
TABLE_BOMGROUP_HEAD
D
BOM OPTIONS
TABLE_BOMGROUP_ITEM
BOM GROUP
K84_COMMON K84_COMMON_PVT K84_MCP K84_MISC K84_PROGPARTS K84_DEBUG_ENG K84_DEBUG_PVT K84_DEBUG_PROD K84_DEVEL_ENG K84_DEVEL_PVT
COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_ENG,K84_PROGPARTS
TABLE_BOMGROUP_ITEM
COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_PROD,K84_PROGPARTS
TABLE_BOMGROUP_ITEM
MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC
TABLE_BOMGROUP_ITEM
ONEWIRE_PU,DP_ESD,MIKEY,LDO_NO,MEM_SENSE,1P05_HIGH_SIDE_SENSE,MCP_T_DIODE_SENSOR,MCPSMC_DIGITEMP_YES
TABLE_BOMGROUP_ITEM
BOOTROM_PROG,SMC_PROG,WELLSPRING_PROG
TABLE_BOMGROUP_ITEM
DEVEL_BOM,SMC_DEBUG_YES,XDP
TABLE_BOMGROUP_ITEM
DEVEL_BOM_PVT,SMC_DEBUG_YES,XDP,NO_VREFMRGN
TABLE_BOMGROUP_ITEM
SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN
TABLE_BOMGROUP_ITEM
DEBUG_ADC,XDP_CONN,LPCPLUS,VREFMRGN
TABLE_BOMGROUP_ITEM
XDP_CONN,LPCPLUS
Module Parts
PART NUMBER
337S3769 338S0710 516S0706
QTY
1 1 1 1 1 1 4 1 2 1 1 1 4 3 5 5 3 4 1
DESCRIPTION
PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7550
REFERENCE DES
U1000 U1400 J3200 J3100 J3200 J3100 SCREW1,SCREW2,SCREW3,SCREW4 J3900 J4600,J4610 J9400 J6700 U7870 ZS0900,ZS0901,ZS0902,ZS0903 ZS0908,ZS0909,ZS0911
CRITICAL
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
BOM OPTION
CPU_2_0GHZ MCP_B03 FOX_DDR_CONN FOX_DDR_CONN MLX_DDR_CONN MLX_DDR_CONN
IC,GMCP,MCP79,35X35MM,BGA1437,B03
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA
516-0201 516S0790 516-0213 452-1708 514-0704 514-0705 514-0706 514-0718 353S2718 870-1885 870-1885 870-1886 870-1886 870-1887 104S0033 518S0774
CONN,204P,SODIMM,P=0.6MM
CONN,204P,SODIMM,SOCKET,DDR3,RAM,NON/SC
CONN,204P,SODIMM,P=0.6MM,HF
SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97
CONN,RCPT,RJ45,PLASTIC,HF,K83/K84
CONN,RCPT,USB,4P,PLASTIC,HF,K83/K84
CONN,RCPT,MDP,20P,PLASTIC,HF,K83/K84
K84 BOARD STACK-UP

Top 2 3 4
XDP_CONN
CONN,RCPT,S/PDIF,TX,HF,CFR,K83/K84
IC,ISL88042,4X V MONTR,2.78/2.86V,TDFN8
SIGNAL GROUND SIGNAL(High Speed) SIGNAL(High Speed) GROUND POWER POWER GROUND SIGNAL(High Speed) SIGNAL(High Speed) GROUND SIGNAL
POGO PIN,MED,NOISE-IMPROVED,K84
POGO PIN,MED,NOISE-IMPROVED,K84
POGO PIN,TALL,NOISE-IMPROVED,K84
ZS0904,ZS0905,ZS0906,ZS0907,ZS0910
POGO PIN,TALL,NOISE-IMPROVED,K84
ZS0912,ZS0913,ZS0914,ZS0915,ZS0919
POGO PIN,THIN,NOISE-IMPROVED,K84
ZS0917,ZS0918,ZS0916 R6612,R6617,R6630,R6633 J1300
RES,MF,1/4W,6.8OHM,5%,0805,SMD
CONN,RCPT,60P,P=0.4,STK HT 1.0
5 6 7 8
353S2718 514-0704 514-0705 514-0706 514-0718
IS IS IS IS IS
NEW INTERSIL PART FOR FIXING B4 CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI CLOUD GREY 4/LB3 PLASTIC W/PDNI
DONGLE ISSUE PLATING VERSION PLATING VERSION PLATING VERSION PLATING VERSION
OF OF OF OF
514-0692 514-0689 514-0691 514-0694
PART PART PART PART
FOR FOR FOR FOR
RJ45 CONNECTOR USB CONNECTORS MINI DP CONNECTOR AUDIO CONNECTOR
DEVELOPMENT BOM
PART NUMBER
085-0748 085-1076
QTY
1 1
DESCRIPTION
K84 MLB DEVELOPMENT BOM
REFERENCE DES
DEVEL DEVEL_PVT
CRITICAL
CRITICAL CRITICAL
BOM OPTION
DEVEL_BOM DEVEL_BOM_PVT
9 10 11 BOTTOM
K84 MLB DEVELOPMENT PVT
Programmable Parts
338S0563 341S2485 335S0610 341S2487 337S2983 341S2491 1 1 1 1 1 1
IC,SMC,HS8/2117,9X9MM,TLP,HF
U4900 U4900 U6100 U6100 U5701 U5701
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
SMC_BLANK SMC_PROG BOOTROM_BLANK BOOTROM_PROG WELLSPRING_BLANK WELLSPRING_PROG
IC,SMC,K84
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
IC,PRGRM,EFI BOOTROM,UNLOCK,K84
IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794
IC,WELLSPRING CONTROLLER,K84
LOCKED BOOTROM APN IS 341S2488
Alternate Parts
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR PART NUMBER

152S0778
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
152S0693
ALL
DALE/VISHAY, MAGLAYERS AS ALTERNATE

TABLE_ALT_ITEM
SYNC_MASTER=K24_MLB
PAGE TITLE
152S0796
152S0685
ALL
CYNTEC AS ALTERNATE
TABLE_ALT_ITEM
157S0058
157S0055
ALL
DELTA AS ALTERNATE
TABLE_ALT_ITEM
BOM Configuration
DRAWING NUMBER SIZE
138S0603
138S0602
ALL
MURATA AS ALTERNATE
TABLE_ALT_ITEM
Apple Inc.
R
051-7982
REVISION
128S0093
128S0218
ALL
KEMET AS ALTERNATE
TABLE_ALT_ITEM
C.0.0
BRANCH PAGE
152S0874
152S0516
ALL
MAGLAYERS AS ALTERNATE
TABLE_ALT_ITEM

TABLE_ALT_ITEM
152S0847
152S0586
ALL
MAGLAYERS AS ALTERNATE
104S0018
104S0023
ALL
DALE/VISHAY AS ALTERNATE
4 OF 109
SHEET
8
Revision History
7
NOTE: All page numbers are .csa, not PDF.
6
See page 1 for .csa -> PDF mapping.
1/19/2009:INITIAL RELEASE 0.0.1- ALL PAGES SYNCED FROM K24 - REPLACED K24 REFERENCES WITH K84 3/20/2009: RELEASE 7.1.0 (MAJOR)3/25/2009: RELEASE 7.3.0 (MAJOR)- UPDATED SCHEMATIC AND PCB PART NUMBER INFO - PAGE 31 & 32: PIN SWAPS ON THE DDR3 CONNECTOR PAGES FOR ROUTING PURPOSES (REFER TO RONS EMAIL) - DELETED PAGE 71 (5V S3 LT POWER SUPPLY) AS THERE IS NO NEED OF A SEPARATE 5V S3/S0 SUPPLY 1/21/2009: RELEASE 0.0.2- PAGE 7: DELETED PP5VLT_S3 NETS - DELETED PAGES 41,42,43,48,97,98,105 [FIREWIRE, IR CONTROLLER, BACKLIGHT CKT] ***PAGES SYNCED FROM CASEY HARDYS AUDIO_MLB SINCE LAST RELEASE 7.0.0*** - PAGE 7: RENAMED PP5VRT_S3 TO PP5V_S3 ["LT" & "RT" NOMENCLATURE CLEAN-UP] - UPDATED BOM CONFIGURATIONS - PAGE 8: COMBINED 5V S3 LT AND RT ALIASES INTO ONE =PP5V_S3_REG AND RENAMED NETS - DELETED IR SPECIFIC NETS ON SATA CONNECTOR -PG. 67, DELETED R6726 (LT & RT NOMENCLATURE CLEAN-UP) -PG. 66, CHANGED C6610/11/30/31 TO 0.015UF - PAGE 8: DELETED =PPVIN_S3_5VLTS3, =PP5VLT_S3_V5IN NETS 1/21/2009: RELEASE 0.0.3-PG. 68, ADDED MIKEY MIC LOAD COMPARATOR CKT - PAGE 9: ADDED ALIAS MCP_GPIO_4 FOR MIKEY MIC LOAD DETECT CIRCUIT - CORRECTD BOM CONFIG TABLES -PG. 68, ADDED R6873 - PAGE 21: UNSTUFFED R2143 PU ON MCP_GPIO_4 AS THERE IS ALREADY A 100K PU ON AUDIO PAGE -PG. 68, CORRECTED CODEC OUTPUT SIGNALS TABLE COMMENTS - PAGE 45: ADDED APN TEXT NOTE FOR SIL CONNECTOR 1/21/2009: RELEASE 0.0.4- PAGE 55: ADDED BC846BM NPN TRANSISTOR (APN 372S0129) TO MCP T-DIODE SENSOR CIRCUIT SIMILAR TO - CORRECTED BOM CONFIG TABLE (ADDED BACK BKLT_ENG) THAT IN CPU T-DIODE SENSOR AND STUFFED C5540 - ADDED BACK PAGES 97-98 (LCD BACKLIGHT DRIVER AND SUPPORT CKT) 3/24/2009: RELEASE 7.2.0 (MAJOR)- PAGE 72: RENAMED NETS AND NOTES TO REMOVE REFERENCES TO RT POWER SUPPLY - DELETED KB BACKLIGHT DRIVER/DETECTION CKT - PAGE 72: REPLACED L7260 WITH APN 152S0959 AS PER DAYU - PAGE 4: CHANGE THE CPU TO NEW APNB 337S3704 - PAGE 72: ADDED C7282 APN 128S0218 IN PARALLEL WITH C7280 AS PER DAYU 1/23/2009: RELEASE 0.0.5- PAGE 7: DELETED PPBUS_R_G3H AS NO NEED OF TWO PPBUS BRANCHES - PAGE 73: REPLACED Q7320 AND Q7321 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU - UPDATED PAGES 72-73 : 5V/3.3V & DDR3 POWER SUPPLIES AS PER FLOS RECOMMENDATIONS - PAGE 8: COMBINED TWO SEPARATE PPBUSA/B BRANCHES INTO ONE =PPBUS_G3H - PAGE 74: REPLACED C7433 AND C7431 WITH 0.001UF CAPS APN 132S1035 - SET SOURCE SYNC OF AUDIO PAGES (62-63, 65-68) FROM LENGS AUDIO PAGES - PAGE 9: ADDED LVDS HOLE APN 998-1521 - PAGE 75: REPLACED C7576 WITH 0.022UF APN 132S0102 CAP TO INCREASE THE SLEW RATE - PAGE 75: ADDED A NOTE OCP=14.5A TO R7575 - PAGE 34: CHANGED J3401 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA 1/27/2009: TMLB FIRST RELEASE 0.0.1- PAGE 45: MIRRORED J4500 AND RECONNECTED PINS AS PER NEW PIN OUT DESCRIPTION FROM DIANA - PAGE 75: REPLACED Q7560 AND Q7565 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU - NAME CHANGED TO TMLB. SO CALLING IT RELEASE 0.0.1 - PAGE 45: CHANGED J4501 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA - PAGE 76: CORRECTED MAX OUTPUT NOTE TO REFLECT 7.2A INSTEAD OF 8A - UPDATED SCHEM AND PCBF PART NUMBER INFO - PAGE 50: DELETED SMC_PPBUSA_ISENSE ALIAS AND STUFFED R5055 - PAGE 76: REPLACED Q7620 WITH 2 CSD58858 APN 376S0790 MOSFETS AS PER DAYU - UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_PROD AND BLANK PROGRAMMED PARTS. ALSO, DELETED BMON_ENG BOM OPTION - PAGE 54: DELETED U5470 INA210 CIRCUIT AS THERE IS NO NEED - PAGE 77: ADDED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL VIA A 0 OHM RESISTOR TO PIN 3 (PG) OF THE LDO - PAGE 54: REMOVED BMON CURRENT SENSE CIRCUIT - PAGE 70: REMOVED R7080 SENSE RESISTOR AND RENAMED =PPBUSB_G3H TO =PPBUS_G3H AS NO NEED - PAGE 78: DELETED P5V_LTS3_PGOOD AS THERE IS NO 5V LT POWER SUPPLY ANYMORE - REMOVED ALS SPECIFIC NETS (PAGE 34 & 52) TO HAVE TWO PPBUS BRANCHES - PAGE 78: RENAMED =P5VRTS3_EN_L TO =P5VS3_EN_L - PAGE 70: DELETED R7050 CONNECTION BETWEEN CHGR_AGATE AND CHGR_LOWCURRENT_GATE - PAGE 78: ROUTED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL TO THE WIRED AND CIRCUIT 2/5/2009: RELEASE 0.0.2 AS PER DAYU - COPIED TMLB OVER TO MLB AS K84 WILL BE PENRYN SKU WHILE K83 WILL BE ATOM SKU - PAGE 70: ADDED R7050 (6259_YES) CONNECTION FROM PIN 4 (VREF) TO PM_SLP_S3_L AS PER DAYU - UPDATED THE SCHEMATICS, PCBF AND PCBA PART NUMBER INFO - PAGE 70: AS PER DAYU, ADDED: 3/26/2009: RELEASE 7.4.0 (MAJOR)- REPLACED TEXT TMLB WITH MLB THROUGH OUT THE SCHEMATICS R7051 (6259_YES) CONNECTION BETWEEN CHGR_PIN26 AND CHGR_LOWCURRENT_GATE; - PAGE 4: UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_ENG FOR K84_COMMON BOM GROUP R7052 (6259_NO) CONNECTION BETWEEN CHGR_PIN26 AND GND_CHGR_SGND; - PAGE 4: UPDATED EEE NUMBER - 8CG - PAGE 60: REPLACED DUAL PACKAGE OPA330 OPAMPS WITH SINGLE PACKAGE ONES - APN 353S2179 R7053 (6259_YES) CONNECTION BETWEEN CHGR_PIN6 AND PIN 12 (VHST); - PAGE 4: ADDED 085 DEVELOPMENT BOM VARIANT & K84_DEVEL_ENG, K84_DEVEL_PVT BOM GROUPS R7054 (6259_NO) CONNECTION BETWEEN CHGR_PIN6 AND GND_CHGR_SGND [U6030, U6031, U6040, U6041]. ALSO, ADDED C6031 & C6041 - PAGE 7: DELETED IR_RX_OUT, PP5V_S3_IR_R, KBDLED_ANODE, SMC_KBDLED_PRESENT_L - PAGE 73: RENAMED TEXT NOTE FOR =PP1V5_S3_REG NET TO VOLTAGE=1.5V - PAGE 9: DELETED EXTRA MEDIUM POGO PIN ZS0912 AND SCREW HOLES Z0908, Z0909 - PAGE 8: DELETED FIREWIRE, IR AND BMON SPECIFIC NETS - PAGE 97: STUFF R9716 AS PER KIRANS FEEDBACK - PAGE 9: DELETED R0950 PCIE_FW_PRSNT_L S PD RESISTOR 3/26/2009: RELEASE 7.5.0 (MAJOR)- PAGE 9: ADDED UNUSED FIREWIRE LANE NETS AS TEST POINTS - PAGE 9: CHANGED ALIAS OF FW_PME_L TO TP_FW_PME_L - PAGE 73: ADDED SHORT XW7304 FROM PIN 1 OF C7300 TO POWER GND (PIN 18) - PAGE 9: ADDED SMC_SYS_KBDLED TP ALIAS - PAGE 72: REPLACED C7282 WITH OSCON APN 128S0248 IN PARALLEL WITH C7280 AS PER DAYU - PAGE 55: REPLACED CPU/MCP THERMAL SENSORS U5515 ANDB U5535 WITH THE CHEAPER VERSION APNB 353S2573 - PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 & C7240 WITH 39UF APN 128S0248 AS PER DAYUS RECOMMENDATIONS 3/26/2009: RELEASE 7.6.0 (MAJOR)- PAGE 72: REPLACE Q7220 WITH SIZ700DT - PAGE 73: REPLACE 16V INPUT SIDE CAPS C7331 WITH 39UF APN 128S0248 AS PER DAYUS RECOMMENDATIONS - PAGE 76: REPLACE Q7620 WITH SIZ700DT - ADDED PLACEMENT NOTES TO XW SHORTS AS PER DAYU - ADDED OMIT BOM OPTION TO ALL THE XW SHORTS 2/6/2009: MAJOR RELEASE 0.1.0 - ADDED DIDT=TRUE ATTRIBUTE TO BOOT/VBST SIGNALS OF ALL THE SWITCHING SUPPLIES - NO CHANGES SINCE LAST MINOR RELEASE 0.0.2 - PAGE 8: DELETED =PP3V42_G3H_BATT AS THERE IS NO BIL CONNECTOR - PAGE 8: ADDED =PP3V42_G3H_HALL FOR THE HALL EFFECT CONNECTOR 2/6/2009: WEEKLY RFA BOM RELEASE 1.0.0- PAGE 8: ADDED =PP3V3_S3_AUDIO ALIAS NET FOR CASEYS NEW CHANGES BELOW - NO CHANGES SINCE LAST MAJOR RELEASE 0.1.0 - PAGE 8: DELETED =PP3V42_G3H_PPBUSAISNS AS PPBUS SENSE CIRCUIT HAS BEEN REMOVED - PAGE 8: RENAMED ALIAS =PP5V_S3_P5VS0FET TO =PP5V_S3_P5VLTS0FET AS THIS GOES TO 5V LT S0 FET CIRCUIT 2/15/2009: RELEASE 2.0.0 (WEEKLY RFA)- PAGE 8: ADDED =PP5V_S3_P5VRTS0FET ALIAS, GOING TO 5V RT S0 FET CIRCUIT 1. PAGE 3: POWER BLOCK DIAGRAM - ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR. ALSO, ADDED SENSE RESISTOR ON PPBUS - PAGE 8: ADDED PLACEMENT NOTE TO Q5502 E PAGE 8: ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR, WHILE PPBUSB FEEDS 5V/3.3 V SUPPLY, LCD BKLT & PPBUS VOLTAGE SENS 2.CKT - PAGE 9: ADDED OMIT ATTRIBUTE TO THE LVDS HOLE 3. PAGES 31, 32: REPLACED 0.1UF 0204 TYPE DDR3 DECOUPLING CAPS WITH 0402 TYPE CAPS ( APPLE P/N : 132S1059) - PAGE 69: ADDED HALL EFFECT CONNECTOR CIRCUIT J6955 APN 516S0787 4. PAGE 34: REPLACED AIRPORT CONNECTOR WITH PN 516S0580 AND UPDATED CONNECTIONS ACCORDINGLY - PAGE 79: RENAMED INPUT VOLTAGE NETS OF 5V S0 FET CIRCUITS TO REFLECT RT AND LT 5. PAGE 34: REPLACED SCHMITTS TRIGGER WITH PN 311S0449 (MATCHES UPDATED ALIASES ON PAGE 8) 6. PAGE 45: REPLACED SATA HDD CONNECTOR WITH APPLE PN 516S0350 AND UPDATED CONNECTIONS ACCORDINGLY 7. PAGE 45: ADDED 2 PIN CONNECTOR (APPLE PN 518S0519) FOR SIL 8. PAGE 46: REPLACED ESD DIODES WITH CHEAPER PN 377S0066 ***PAGES SYNCED FROM CASEY HARDYS AUDIO_MLB SINCE LAST RELEASE 7.5.0*** 9. PAGE 54: ADDED BOM OPTION- DEBUG_SENSE- TO CPU 1.05V/CPU VCORE HIGH SIDE CURRENT SENSE AND MCP MEM VDD CURRENT SENSE CIRCUITS FOR DEVELOPMENT BOM -PG. 67, ADDED R6725 10. PAGE 4: ADDED DEBUG_SENSE BOM OPTION TO THE K84_DEVEL_ENG BOM GROUP -PG. 67 ADDED =PP3V3_S3_AUDIO NET 11. PAGE 58: DELETED IPD FLEX CONNECTOR J5800. RENAMED PP18V5_S3, PP3V3_S3_LDO_R, PP3V3_S3_LDO TO PP18V5_S3_LDO, PP3V3_S3_IPD_R AND PP3V3_S3_IPD RESPECTIVELY TO MATCH WITH NEW ADDED PAGE 60 NET NAMES. UPDATED THESE NET NAMES ON PAGE 7 ALSO -PG. 67, DELETED L6706 12. ADDED PAGE 60 AND COPIED OVER ZEPHYR2 SCHEMATICS PAGE FROM M97 IPD_FLEX_WELLSPRING. DELETED THE IPD BOARD CONNECTOR. CALLING IT WELLSPRING 3 -PG. 67, ADDED XW6702 13. PAGE 69: REPLACED BATTERY CONNECTER WITH PN 518S0540 AND BIL CONNECTOR WITH PN 518S0588. UPDATED CONNECTIONS ACCORDINGLY -PG. 66, UPDATED 5V S3 ALIAS NOTES POWER) ALIAS ON PAGE 8 14. PAGE 70: DIVIDED PPBUS INTO TWO BRANCHES - PPBUSA & PPBUSB. ADDED SENSE RESISTOR R7080 (2 MOHMS) ON PPBUSA. ALSO ADDED INA210 AMPLIFIER CKT ACROSS SENSE LINES. ADDED PP3V42_G3H_PPBUSAISNS (IN210 -PG. 67, NO STUFFED R6724 15: PAGE 97: REPLACED BKLT DRIVER CKT WITH THAT OF FREESCALE PART, SIMILAR TO K19I 16. PAGE 69: MOVED THE DECAP C6908 TO CORRECT PART U6901.5 ( SIMILAR TO K24) 17. PAGE 4: REMOVED BKLT_ENG BOM OPTION 3/29/2009: RELEASE 8.0.0 (RFA)***PAGES SYNCED FROM LENG OOIS AUDIO_MLB SINCE LAST RELEASE 1.0.0*** 1. REPLACED MIKEY CD3272 WITH CD3282 - PAGE 7: SCRUBBED THROUGH THE FUNCTIONAL TEST POINTS AGAINST TOMS SPREADSHEET 2. ADAPT JACK INSERT DETECT CIRCUIT TO CD3282 JACK INSERT DETECT FUNCTION. 3/6/2009: RELEASE 6.0.0 (RFA:)- PAGE 7: RENAMED RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR 3. REMOVED JACK EXTRACT CIRCUITRY, FUNCTION IS TAKEN OVER BY CD3282 - PAGE 7: DELETED BATT SIGNAL CONN AND ADDED HALL EFFECT CONNECTOR TEST POINTS 4. REMOVE FM ANTENNA NET. - PAGE 4: ADDED 152S0693 AS ALT FOR 152S0778 FOR SUPPLY REDUNDANCY - PAGE 7: DELETED THERMAL FUNC_TEST SECTION - PAGE 4: ADDED 138S0603 AS ALT FOR 138S0602B FOR SUPPLY REDUNDANCY - PAGE 9: ADDED TP_ ALIASES FOR - CARDREADER_RESET, USB_CARDREADER_N/P, AND ***PAGES SYNCED FROM K24 SINCE LAST RELEASE 1.0.0*** - PAGE 4: ADDED CYNTEC ALTERNATES FOR 107S0074 --> 107S0138 [R7020] AND 107S0075 USB_IR_N/P 1. PAGE 75: MCP VCORE INDUCTOR CHECK FOR PD: CHANGED L7560 TO 152S0966 AND THEN TO 152S0867. BUT NOW IT IS BACK TO 13A PART FOR NOW [R7008] --> 107S0139 - PAGE 9: FIXED BAD_TP_NC NETS - TP_RTL8211_CLK125, TP_PP3V3_ENET_PHY_VDDREG 2. ADDED DIDT TO ALL THE GATE AND PHASE NETS - PAGE 4: ADDED DALE/VISHAY ALTERNATES FOR 104S0023 --> 104S0018 - PAGE 9: DELETED Z0912 MLB MOUNTING HOLE AS NO LONGER NEEDED - PAGE 4: ADDED BOM OPTION 6259_NO TO THE TABLE UNDER K84_MISC BOM GROUP - PAGE 34: RENAMED TITLE: RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR - PAGE 7: DELETED SMC_BIL_BUTTON_L NET FROM BATT SIGNAL CONN GROUP AS BIL IS NO LONGER A POR - PAGE 50: REPLACED R5030 WITH APN: 114S0114,(ITS A 1% TOL, 1/16W, 0402, 84.5OHM RESISTOR) 2/25/09: WEEKLY RFA RELEASE (3.0.0) - PAGE 8: DELETED =PP3V42_G3H_AUDIO AS IT IS NO LONGER USED - PAGE 66: FIXED UNNAMED NETS CONNECTED TO - R6632 - ADDED DIDT ATTRIBUTE - PAGE 8: DELETED =PP3V3_S0_TPAD AS THERE IS NO KEYBOARD BACKLIGHT DRIVER - PAGE 74: FIXED UNNAMED NETS CONNECTED TO - XW7401, XW7402, XW7403 AND XW7404 - PAGE 4: REMOVED SUPERCAP_NO BOM OPTION. ADDED DEBUG_ADC BOM OPTION UNDER K84_DEVEL_ENG - PAGE 8: DELETED =PP3V42_G3H_5V3V3_EN AS IT IS NO LONGER USED - PAGE 78: FIXED BAD_TP_NC NETS - TP_DDRREG_PGOOD (THIS IS FOR NEW SENSOR PAGE 60) - PAGE 9; ADDED 3 ADDITIONAL TALL POGO PINS AS PER NEW MCO AND DELETED ZS0909 SHORT POGO AS IT WAS EXTRA - PAGE 76: REPLACED L7620 WITH ITS REPLACEMENT - APN 152S0518 - PAGE 4: CORRECTED APN FOR PROGRAMMED PARTS - SMC, BOOT ROM, WELLSPRING - PAGE 9: ADDED TP ALIASES TO IMVP6_VR_TT AND IMVP6_NTC - PAGE 69: CHANGE PIN OUTS OF J6955 AS PER CHINMAY - PAGE 4: REMOVED LDO_YES BOM OPTION - PAGE 34: ADDED LC FILTER (L3406 AND C3432) ON PP3V3_S3_BT POWER RAIL AS PER JOHN SCHENS FEEDBACK - PAGE 34: REPLACED THE AIRPORT CONNECTOR WITH 1.8 MM HEIGHT CONNECTOR APN 516S0582 - PAGE 8: DIVIDED PP5V_S0_FET INTO TWO BRANCHES - PP5VRT_S0_FET & PP5VLT_S0_FET (FOR ROUTING PURPOSE, - PAGE 39: REPLACED ETHERNET CONNECTOR WITH THAT OF M97A/K24 PART APN 514-0636 (SYNCED WITH K24) 3/31/2009: RELEASE 9.0.0 (RFA)5V S3 IS DIVIDED INTO RT AND LT POWER SUPPLY AND WILL HAVE CORRESPONDING S0 FETS) - PAGE 8: DIVIDED PP5V_S3_REG INTO TWO BRANCHES - PP5VRT_S3_REG & PP5VLT_S3_REG - PAGE 45: RENAMED =PP5V_S0_HDD_R TO PP5V_S0_HDD_R (AS PER UNALIASED.LST REPORT) - PAGE 8: ADDED PP5V_S3_DEBUG_ADC_AVDD/DVDD & PP5V_S3_DEBUG_ISNS ALIASES FOR NEW SENSOR PAGE 60 - PAGE 50: ADDED UNUSED NET ALIAS FOR SMC_BIL_BUTTON_L (NC_SMC_BIL_BUTTON_L) - PAGE 4: DELETED DEBUG_SENSE BOM OPTION AND ADDED MEM_SENSE AND - PAGE 8: ADDED PP3V3_S3_BT ALIAS FOR BLUETOOTH ON RIGHT CLUTCH CONNECTOR PAGE - PAGE 52: DELETED TERM BIL FROM SMC BATTERY & BIL CONNECTIONS 1P05_HIGH_SIDE_SENSE OPTIONS UNDER K84_COMMON BOM GROUP - PAGE 8: ADDED ALIAS PPVIN_S3_5VLTS3 UNDER PPBUSB - PAGE 57: ADDED PLACEMENT NOTES TO C5702 AND C5704 AS PER JOHN SCHENS FEEDBACK - PAGE 4: ADDED MCP_T_DIODE_SENSOR, MCPSMC_DIGITEMP_NO BOM OPTIONS UNDER - PAGE 8: ADDED ALIAS PP5VLT_S3_V5IN UNDER PP5VRT_S3_REG - PAGE 59: REPLACED SMS PART WITH THE NEW BOSCH BMA141 ANALOG PART. ADDED R5923 10K PU RESISTOR ON K84_COMMON BOM GROUP - PAGE 4: ADDED SHORT POGO PIN 870-1699 AS ALTERNATE FOR THE MEDIUM ONES - PAGE 28: REMOVED RTC POWER SOURCES CIRCUIT AND SUPERCAP_NO BOM OPTION FROM R2820 SEL1 SIGNAL AND REMOVED 10K PD ON ST PIN. REPLACED C5926 WITH 0.01UF CAP AS PER DATA SHEET. AND, - PAGE 34: SINCE X16 AIRPORT CARD SOLUTION IS BEING USED, PP5V_S3_WLAN IS REPLACED BY PP3V3_S3_WLAN REPLACED C5923-C5925 CAPS WITH 0.033 UF VALUES FOR CUT-OFF FREQUENCY OF ~146HZ - PAGE 4: UPDATED DESCRIPTION FOR THE CPU (GOING TO Q3450). ALSO, REPLACED PP5V_WLAN WITH PP3V3_WLAN ON PAGE 6 (FUNCTIONAL TEST POINTS) - PAGE 60: CORRECTED PLACEMENT NOTE ASSOCIATED TO XW6080 TO REFLECT D9710 INSTEAD OF D9701 - PAGE 7: UPDATED TPS AS PER NEW UPDATE FROM TOM (SPREADSHEET ATTACHED TO THE RADAR) - PAGE 34: R3453 IS MODIFIED TO 110K RESISTOR, R3454 IS NOSTUFF AND R3453 IS PULLED UP TO PP3V3_WLAN_F. - PAGE 69: CHANGED L6995 TOB APN 152S1017 FOR COT SAVING AND EFFICIENCY - PAGE 12: REPLACED C1260 WITH APN 128S0267 AS PER DAYU THIS IS TO ENSURE 3.3V LEVEL AT THE INPUT OF U3402 AND MAINTAIN 100MS DELAY SPEC BETWEEN 3.3V POWER - PAGE 69: REMOVED BIL CIRCUIT AS IT NO LONGER A POR [R6960, C6954, D6951, C6953, C6952, J6955, C6951] - PAGE 34: DELETED TEXT NOTE ASSOCIATED WITH J3401 TO THE CARD GETTING STABLE AND AIRPORT GETTING OUT OF RESET - PAGE 70: MOVED C7028 TO PPVBAT_G3H_CHGR_REG AS PER JOHN SCHENS FEEDBACK - PAGE 45: ADDED VOLTAGE, MIN LINE AND NECK WIDTH FOR PP5V_S0_HDD_FLT - PAGE 34: DISCONNECTED PP5V_S3_BTCAMERA_F POWER RAIL FROM THE CONNECTOR AND REPLACED IT WITH PP3V3_S3_BT - PAGE 70: ADDED PLACEMENT NOTE TO C7027 AS PER JOHN SCHENS FEEDBACK - PAGE 52: ADDED 0 OHMS STUFFING OPTION TO CONNECT MIKEY SMBUS CONNECTIONS TO MCP SMBUS 0. (SIMILAR TO M96). CAMERA SIGNALS ARE ROUTED VIA LVDS CONNECTOR. MOVED PP5V_S3_BTCAMERA POWER CIRCUIT - PAGE 70: REPLACED R7080 WITH APN 107S0142 WHICH IS TRUE 4-TERMINAL SENSE RESISTOR WITH SMALLER PACKAGE ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0 OHMS ALONG WITH THE USB CAMERA SIGNALS TO LVDS PAGE. ALSO, RENAMED THIS POWER RAIL TO PP5V_S3_CAMERA ON LVDS (DAYUS RECOMMENDATION) - PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN MIKEY AND MCP SMBUS 1 CONNECTIONS. PAGE - PAGE 70: ADDED BOM OPTION 6259_YES TO R7050 AND 6259_NO TO U7060 AND AMON PULLDOWN LOGIC AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_NO WITH THESE 0 OHMS - PAGE 34: ADDED SENSE RESISTOR R3452 ON PP3V3_WLAN SIGNAL CIRCUIT COMPONENTS. TURNED ON 6259_NO, FOR NOW, ON PAGE 4 TABLE - PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN SMC B SMBUS AND MCP SMBUS 1 - PAGE 34: ADDED CHOKES ON PCIE TX/RX SIGNALS. UPDATED PAGE 6 (FUNCTIONAL TEST POINTS) ACCORDINGLY - PAGE 72: CONNECTED SMC_PM_G2_EN SIGNAL TO EN0 PIN 13 OF U7200 VIA A 100K RESISTOR FOR KEEPING THE POWER SUPPLY CONNECTIONS. AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0 - PAGE 34: REPLACED L3404 WLAN INDUCTOR WITH LOW DCR 0603 PART - APN 155S0367 OFF IN CASE IF SMC TURNS OFF OHMS - PAGE 39: REPLACED ETHERNET CONNECTOR WITH APN 514-0668 (SIMILAR TO K36B) - PAGE 72: ADDED PLACEMENT NOTE TO C7230 AS PER JOHN SCHENS FEEDBACK - PAGE 52: ADDED BOM OPTION MCPSMC_DIGITEMP_NO TO R5230 AND R5231 - PAGE 72: REMOVED NOSTUFFED C7251 AS PER DAYU - PAGE 54: REPLACED DEBUG_SENSE BOM OPTION WITH MEM_SENSE FOR MCP MEMORY VDD - PAGE 45: CHANGED SATA HDD CONNECTOR TO APN 516S0616 - PAGE 73: REPLACED C7307,C7308 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY) CURRENT SENSE CIRCUIT AND WITH 1P05_HIGH_SIDE_SENSE FOR CPU 1.05V AND - PAGE 73: ADDED PLACEMENT NOTE TO C7333 AS PER JOHN SCHENS FEEDBACK - PAGE 45: ADDED SENSE RESISTORS R4598 AND R4599 ON 5V ODD AND 5V HDD RAILS RESPECTIVELY CPU VCORE HIGH SIDE CURRENT SENSE CIRCUIT - PAGE 50: UNSTUFFED R5055 AND USED SMC_NB_MISC_ISENSE SIGNAL PORT (SMC) FOR CONNECTING PPBUSA ISENSE SIGNAL. - PAGE 73: DELETED NOTES AT THE BOTTOM RIGHT AFTER CONSULTING WITH DAYU - PAGE 55: ADDED MCP_T_DIODE_SENSOR BOM OPTION TO THE MCP T-DIODE THERMAL ADDED ALIAS ON THIS PAGE - PAGE 73: MOVED C7344 NEXT TO R7350 AND ADDED PLACEMENT NOTE (JOHN SCHEN WANTED IT TO BE NEXT TO L7320 SENSOR CIRCUIT DAYU PERFERRED IT TO BE AFTER THE SENSE RESISTOR - PAGE 51: REPLACED TWO DEMUX SOLUTION WITH A SINGLE DEMUX 1X2 SOLUTION. APN USED - 353S2220 - PAGE 59: DELETED R5923 FROM THE TEXT NOTE [ONLY CHIP SELECT IS BEING DEMUXED] - PAGE 74: ADDED PLACEMENT NOTES TO C7419,C7422 AND C7423 AS PER JOHN SCHENS FEEDBACK - PAGE 60: MANUALLY UPDATED RESISTORS VALUES (VOLTAGE DIVIDERS,AMPLIFIER GAINS, RC) TO MATCH WITH - PAGE 51: R5156, R5157 AND R5158 ARE NOW 0 OHM ISOLATION RESISTORS PLACED ON SPI BUS NEXT TO THE LOCATION WHERE - PAGE 74: STUFFED C7432 AS PER DAYU K19I UPDATES, EXCEPT VOLTAGE DIVIDER FOR PP3V3_WLAN [K19I USES 5V RAIL]. FOR IT BRANCHES INTO TWO - ONE GOING TO MLB SPI ROM AND THE OTHER GOING TO LPC CONNECTOR. THESE RESISTORS ARE - PAGE 74: REMOVED C7400, C7402, R7451 AND R7452 AS PER DAYU PP3V3_WLAN, R6010 HAS BEEN CHANGED TO 634K TO GET VDIVIDER = ~2V PLACED ON THE LPC CONNECTOR BRANCH. THIS IS TO AVOID STUBS IN PRODUCTION - PAGE 75: ADDED PLACEMENT NOTE TO C7563 AS PER JOHN SCHENS FEEDBACK - PAGE 75: ADDED C7590 (2.2UF) APN 138S0579 IN PARALLEL WITH C7563 AS PER DAYU - PAGE 52: ADDED SENSOR ADC CONNECTION BLOCK UNDER SMC 0 SMBUS CONNECTIONS SECTION - PAGE 74: CHANGE L7400 AND L7401 TO 152S1019 AS PER DAYU FOR COST SAVING. ALSO, UPDATED ASSOCIATED TEXTS - PAGE 102: ADDED CONN_PCIE_MINI_R2D_P/N AND CONN_PCIE_MINI_D2R_P/N NETS IN THE - PAGE 75: MOVED C7569 TO PPMCPCORE_S0_R AS PER JOHN SCHENS FEEDBACK - PAGE 54: MOVED PBUS INA210 CIRCUIT TO THIS CURRENT SENSOR PAGE. RENAMED REF DES AS PER THIS PAGE 54 CONSTRAINT SET - PAGE 55: DELETED J5590 CONNECTOR (CONNECTED TO HEAT-PIPE TEMPERATURE DETECTION RAILS) - PAGE 90: ADDED EMI CAPS (C9017-C9025) ON I2C, LED_RETURNS AND LCD_BKLT POWER RAILS GOING TO LVDS. - PAGE 70: ADDED TP TO PIN 13 - PAGE 55: REPLACED U5515 & U5535 WITH CHEAPER APN 353S2571 ADDED PLACEMENT NOTES TOO - PAGE 4: ADDED MIKEY_LOAD_DET BOM OPTION UNDER K84_MISC BOM GROUP - PAGE 60: REMOVED WELLSPRING 3 PAGE (GOING BACK TO K24 SOLUTION) AND REPLACED IT WITH K19I DEBUG SENSOR PAGE (SCHUTIL SYNC) - PAGE 94: REPLACED C9486 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY) - PAGE 61: RENAMED SPI SIGNALS TO MATCH WITH CHANGES ON PAGE 51 ***PAGES SYNCED FROM DAVIDS AUDIO_MLB SINCE LAST RELEASE 8.0.0*** - PAGE 69: ADDED BOM OPTION NOSTUFF TO D6950 FOR NOW - CHANGED R6211 & R6212 FROM 39 OHMS TO 22 OHMS ***PAGES SYNCED FROM CASEY HARDYS AUDIO_MLB SINCE LAST RELEASE 5.0.0*** - PAGE 69: ADDED D6951 ESD DIODE ON BIL SMBUS SIGNALS (NOSTUFF FOR NOW) -PG. 67, CHANGED U6700 CB INPUT TO BE CONTROLLED BY CS4206 GPIO0. - DELETED NOTE ABOVE U6500 - PAGE 69: REPLACED BATTERY CONNECTOR J6950 WITH APN 518S0540 (M96) CONNECTOR -PG. 62, CHANGED TP_AUD_GPIO_0 TO AUD_GPIO_0. - ADDED BOMOPTION = MIKEY_LOAD_DET ATTRIBUTE TO R6870, R6871, C6870, - PAGE 70: ADDED BYPASS 0 OHM RESISTOR R7050 (NOSTUFF FOR NOW) OPTION FOR NEW CHIP WHICH WONT REQUIRE U7060 SOLUTION -PG.66, REPLACED THE LM48310S (U6610/20/30) WITH LM48311S - UPDATED SIGNAL PATH CHART TO INCLUDE MCP79 GPIO ASSIGNMENTS - PAGE 71: ADDED NEW PAGE FOR PP5V_LT_REG POWER SUPPLY. UPDATED ALL THE REF DES AS PER THE PAGE NUMBER -PG. 67, CONNECTED HP OUTPUTS TO NC OF U6700 AND LINE INPUTS TO NO OF U6700. - ADDED BOMOPTION = MIKEY ATTRIBUTE TO R6860, C6860, Q6802, R6864, R6865, & R6861 - PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 WITH 68UF OSCON CAP (APN 128S0275) & C7240 WITH 39UF (APN 128S0248) -PG. 68, CHANGED AUD_PORTB_DET_L TO AUD_PORTA_DET_L. C6871, U6870, C6872, R6872, & R6873 - PAGE 71: CHANGED C7160 TO 39UF OSCON CAP (APN 128S0248) - REMOVED NOTE RE: ROUTING TO MCP79 GPIO ABOVE U6870 -PG. 68, CHANGED AUD_PORTG_DET_L TO AUD_PORTB_DET_L. - PAGE 72: REPLACE Q7220 WITH SIZ700DT AND L7260 WITH SMALLER 10A PART (APN 152S0778) -PG. 67, SET MIN. LINE AND NECK WIDTHS FOR AUD_CONN_L AND AUD_CONN_R - REMOVED BOMOPTION = NOSTUFF ATTRIBUTE FROM R6724 - PAGE 73: ADDED SENSE RESISTOR R7350 ON 1.5V DDR3 SUPPLY RAIL - ADDED BOMOPTION = NOSTUFF ATTRIBUTE TO R6725 - PAGE 77: REMOVED 1.05V S0 PLL LDO CIRCUIT. AND, REMOVED LDO_NO BOM OPTION FROM R7745 ***PAGES SYNCED FROM K24 SINCE LAST RELEASE 5.0.0*** - PAGE 75: CHANGED C7571 & C7560 TO 68UF OSCON CAPS (APN 128S0275) - PAGE 25: CHANGED C2500,C2501,C2502,C2503,C2515,C2520,C2528,C2540,C2580,C2582,C2584,C2586,C2588, - PAGE 78: RENAMED P5VS3_EN_L TO P5VRTS3_EN_L (RT POWER SUPPLY ENABLE) AND ADDED R7814, C7814 S3 ENABLE CIRCUIT C2595 TO 138S0653 4/1/2009: RELEASE 9.1.0 (MAJOR)FOR GENERATING P5VLTS3_EN ENABLE SIGNAL FOR LT POWER SUPPLY - PAGE 26: CHANGED C2615,C6210 TO 138S0653 - PAGE 78: ADDED P5V_LTS3_PGOOD POWER GOOD SIGNAL (WIRED AND WITH OTHER S0 RAILS PGOOD) CORRESPONDING TO 5V LT - PAGE 77: CHANGED U7740 TO 500MA 1.05V LDO - PAGE 4: CHANGED MCP P/N TO 338S0702 AS PER CHALLEE POWER SUPPLY - PAGE 52: FIXED SENSOR ADC SMBUS CONNECTIONS (BOTH SCL AND SDA WERE WRONGLY CONNECTED - PAGE 78: ADDED 0 OHM ISOLATION RESISTORS ON POWER GOOD SIGNALS (BEFORE WIRED AND) TO SMB_0_S0_DATA NETS - PAGE 79: ADDED 5V LT S0 FET AND UPDATED NET NAMES FOR BOTH RT AND LT S0 FET CIRCUITS ACCORDINGLY 3/17/2009: RELEASE 7.0.0 (RFA)- PAGE 69: REFRESHED HALL EFFECT SENSOR WITH THE NEW SYMBOL - PAGE 90: UPDATED LVDS CONNECTOR CONNECTIONS AS PER STEVES RECOMMENDATION. ADDED CAMERA SIGNALS - ADDED PLACEMENT NOTES (ATTRIBUTE) TO ALL XW SHORTS - PAGE 90:RE-ROUTED LED_RETURN SIGNALS FOR LAYOUT FEASIBILITY(CHIP WAS MOVED TO TOP SIDE) - PAGE 97: ADDED BOM OPTION - NOSTUFF- TO R9702 AS PER K19I - PAGE 4: DELETING ENTRIES FOR 107S0138 AND 107S0139 FROM ALTERNATES PARTS TABLE AS THEY WOULD BE REPLACING - PAGE 90: ADDED C9017 (1000PF) CAP AS PER JOHN SCHEN - PAGE 8: DELETED PP5V_S0_BKL, RENAMED PP1V05_S0_MCP_PLL_UF_R TO PP1V05_S0_MCP_PLL_UF THE 107S0074/75 PARTS - PAGE 97: FIXED THE LCDBKLT_VIN SIGNAL NAME ASSOCIATION TO THE CORRECT NET INSTEAD OF - PAGE 8: DELETED PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_BKL_VDDIO, PP3V3_S0_MCP_PLL_VLDO - PAGE 7: RENAMED PP5V_S3_BTCAMERA_F WITH PP3V3_S3_BT_F R9730 PIN - PAGE 8: RENAMED PPVIN_S5_1V5S3_0V75S0 TO PPVIN_S5_1V5S30V75S0 - PAGE 7: DELETED PP5V_S0, PP5V_S3 AND ADDED PP5VRT_S0,PP5VLT_S0, PP5VRT_S3, PP5VLT_S3 DEBUG - PAGE 97: DISCONNECTED PGND (OF CAPS) FROM XW9700 AND ADDED A SEPARATE XW9701 - PAGE 28: DELETED FW_RESET_L SIGNAL VOLTAGE TEST POINTS SHORT TO ISOLATE NOISY PGND FROM THE SYSTEM GND. NAMED IT - PAGE 58: DELETED KB BKLT CIRCUIT - PAGE 7: ADDED PPBUS_R_G3H DEBUG VOLTAGE TEST POINT GND_LCDBKLT_PGND AND ASSIGNED MIN_LINE/NECK_WIDTH ATTRIBUTES - PAGE 60: UPDATED WLAN DIVIDER CIRCUIT WITH 3V3 POWER RAIL INSTEAD OF 5V - PAGE 8: DELETED ALIAS =PP1V05_S0_SMC_LS AS IT IS NO LONGER NEEDED - PAGE 97: RENAMED GND_LCDBKLT TO GND_LCDBKLT_SGND - PAGE 73: UPDATED 1.5V/0.75V POWER SUPPLY WITH CORRECT NET NAMES REFLECTING 1.5V/0.75V INSTEAD OF 1.8V/0.9V AND - PAGE 9: REMOVING 2 EXTRA TALL POGO PINS (ZS0911, ZS0912) AS PER NEW MCO - PAGE 97:DISCONNECTED PINS 2 AND 5 FROM GND PINS(13,19,21)AND CONNECTED SEPARATELY TO IN SYNC WITH PAGE 8 ALIASES - PAGE 9: REPLACED 5 SHORT POGO PINS WITH MEDIUM ONES AND ADDED THREE EXTRA MEDIUM ONES (TOTAL MEDIUM SYSTEM GND - PAGE 4: REMOVED 152S0778 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE SINCE L7260 AS HAS BEEN REPLACED WITH THIS PART POGO PINS = 8) AS PER NEW MCO - PAGE 97: REPLACED D9710 WITH 40V PART- APN 371S0580 AS PER DEREK - PAGE 97: STUFFED R9726 AND SWAPPED C9705 AND R9705 AS PER FREESCALE FOR COMPENSATION. - PAGE 4: REMOVED 104S0018 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE - PAGE 34: REPLACE Q3450 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 - PAGE 45: REPLACE Q4590 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 ALSO, CHANGED R9705 TO 10K 1% VALUE - APN 114S0315 - PAGE 52: DELETE J6955 REFERENCE AS THERE IS NO BIL CONNECTOR ***PAGES SYNCED FROM K24 SINCE LAST RELEASE 2.0.0*** - PAGE 52: REMOVED REFERENCES TO THE LED BACKLIGHT AS FREESCALE PART DOESNT HAVE I2C BUS ACCESS 4/2/2009: RELEASE 9.2.0 (MAJOR): - PAGE 54: REPLACING R5492 WITH APN 107S0139 PART FOR COST SAVING - PAGE 7: SCRUBBED TPS AS PER UPDATE FROM TOM - PG 50: SWAPPED THE PART NUMBER AND THE ALTERNATE PART NUMBER FOR VR5020. MADE ISL60002 THE ALTERNATE PART - PAGE 59: REMOVING R5923 AND ONLY 1 PU ON SEL LINES IS ENOUGH - PAGE 49: FIXED PLACEMENT NOTE ASSOCIATED WITH C4907 (SHOULD BE: PLACE NEAR PIN E1) - PAGE 70: REPLACING R7020 WITH APN 107S0138 PART FOR COST SAVING - PAGE 49:FIXED PLACEMENT NOTES ASSOCIATED WITH R4999,C4920(SHOULD BE:PLACE NEAR PIN M12) - PAGE 70: REPLACING R7008 WITH APN 107S0139 PART FOR COST SAVING ***PAGES SYNCED FROM LENG OOIS AUDIO_MLB SINCE LAST RELEASE 2.0.0*** - PAGE 51: FIXED PLACEMENT NOTE ASSOCIATED WITH R5146 - PLACE NEAR U5110 INSTEAD OF SMC - CHANGED SPEAKER AMPS TO LM48310, PLACEHOLDERS FOR LM48311. LM48311 IS THE CSP VERSION OF THE LM48310. - PAGE 70: R7080 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER - PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH SMBUS_SMC_B_S0_SCL/SDA - CHANGED LDO TO B LP5900. - PAGE 97: RENAMED SINGLE PIN NET GND_LCDBKLT TO GND_LCDBKLT_PGND - PAGE 73: R7350 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER - REMOVED OPTIONAL STUFFING RESISTORS AROUND THE RE-TASKING JACK ANALOG SWITCH. - PAGE 79: REPLACE Q7940 AND Q7948 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 - PAGE 90: REMOVED EMI CAPS [C9017-C9025] ON LED_RETURN, I2C AND LCD_BKLT POWER NETS 2/26/2009: RELEASE 4.0.0 (RFA RELEASE): - PAGE 90: UPDATED LVDS CONNECTOR PINOUT CONNECTIONS AS PER STEVES NEW SPREADSHEET - PAGE 4: ADDED LDO_NO BOM OPTION - PAGE 97: ADDED DIDIT=TRUE ATTRIBUTE TO THE SWITCHING NODE PINS 3 & 4 - PAGE 8: RENAMED PP1V05_S0_MCP_PLL_UF BACK TO PP1V05_S0_MCP_PLL_UF_R - PAGE 97: CHANGED C9711 FROM 0.1UF TO 1.0UF 0603 TYPE CAP AS PER FREESCALE FEEDBACK - PAGE 8: ADDED BACK - PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_MCP_PLL_VLDO - PAGE 97: CHANGED C9715 AND C9716 TO 50V CAPS FOR COST SAVING AND AS PER FREESCALE FEEDBACK - PAGE 13: REPLACED XDP CONNECTOR WITH MINI XDP CONNECTOR APN 516S0625 - PAGE 97: CHANGED R9717 - R9722 FROM 0.1% TO 1% PARTS FOR COST SAVINGS AND AS PER FREESCALE FEEDBACK - PAGE 34: ADDED NOTE WITH REGARD TO SMBUS CONNECTIONS TO THE AIRPORT CONNECTOR - PAGE 97: NO STUFFED C9721 - C9726 AS PER FREESCALE FEEDBACK - PAGE 34: ADDED NOTE WITH REGARD TO 100 MS DELAY REQUIREMENT BETWEEN 3.3 WLAN - PAGE 97: FOR 25KHZ OPERATION, CHANGE R9726 TO NO STUFF, INTERCHANGE R9705(6.8K) WITH C9705 POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET AS IN K19I - PAGE 54: REMOVED NOTE ON AMON AND BMON - PAGE 97: CHANGED R9710 TO 6.65K APN 114S0298 AND R9716 TO 226K APN 114S0445 PARTS AS PER - PAGE 57: REPLACED KEYBOARD CONNECTOR WITH APN 518S0738 FREESCALE FEEDBACK - PAGE 77: ADDED BACK - 1.05 PLL LDO CIRCUIT - PAGE 107: ADDED CONSTRAINTS FOR FOLLOWING SENSOR NETS: ISNS_HDD_P/ISNS_HDD_N; ISNS_ODD_P/ISNS_ODD_N; - PAGE 90: REFRESHED THE SYMBOL OF U9000, PART NUMBER CHANGED TO 353S2603 ISNS_AIRPORT_P/ISNS_AIRPORT_N; ISNS_1V5_S3_P/ISNS_1V5_S3_N; ISNS_LCDBKLT_P/ ISNS_LCDBKLT_N 3/4/2009: RELEASE 5.0.0 (RFA)- PAGE 107: REMOVED FOLLOWING SENSOR NETS CONSTRAINTS: ISNS_P1V5S0MCP_P/ISNS_P1V5S0MCP_N; - PAGE 34: ADDED A TEXT NOTE THAT J3401 (AIRPORT CONNECTOR) COULD CHANGE TO 1.8MM HEIGHT APN 516S0582 ISNS_PVCORES0MCP_P/ISNS_PVCORES0MCP_N SYNC_MASTER=K24_MLB SYNC_DATE=01/19/2009 - PAGE 57: REPLACED KEYBOARD CONNECTOR WITH THAT OF K24 (APN 518S0637) - SYNCED FROM K24 - PAGE 74: ADDED XW7401-XW7404 SHORTS ACROSS L7400 AND L7401 PAGE TITLE - PAGE 69: REPLACED BATTERY CONNECTOR WITH THAT OF K24 (APN 518-0359) - PAGE 69: DELETED NOTE REGARDING INDUCTOR FILTER REQUIREMENT ON BATT_POS_F (AS PER JOHN SCHEN) ***PAGES SYNCED FROM CASEY HARDYS AUDIO_MLB SINCE LAST RELEASE 6.0.0*** - PAGE 70: CHANGED Q7050 TO 376S0761 AS PER DAYU & K24 DESIGN -PG. 67, DELETED R6725 AND NET =PP3V42G3H_AUDIO -PG. 66, ADDED R6613/14/15/16/17 - PAGE 70: CHANGED Q7000 AND Q7001 CHEAPER TO 376S0667 (HAT1128) AS PER DAYUS RECOMMENDATION - PAGE 71: DISCONNECTING EN_PSV (PIN 34) FROM P5VLTS3_EN SIGNAL AND CONNECTING IT TO -PG. 66, ADDED C6612/13 DRAWING NUMBER SIZE PP5VLT_S3_V5IN (5VRT PS) -PG. 66, ADDED R6631/2/3/4/5 -PG. 66, ADDED C6634/5 - PAGE 72: L7220 CHANGED TO 152S0778 FOR COST SAVING AS PER DAYU - PAGE 73: ADDED ONE MORE OSCON 39UF CAP ON INPUT SIDE -PG. 66, CHANGED C6610/11 TO 0.022UF - PAGE 73: MOVED THE SENSE RESISTOR NEXT TO INDUCTOR -PG. 66, CHANGED C6630/31 TO 0.022UF REVISION - PAGE 74: REMOVED UNUSED NETWORK ON U7400 PIN 5 AND PIN 6 AS PER DAYU [R7406, C7410, R7427, R7426] -PG. 65, DELETED R6521 R - PAGE 74: STUFF R7413 AS PER DAYU -PG. 65, ADDED R6523/4 - PAGE 74: CHANGED Q7400 AND Q7402 TO 376S0772 AS PER DAYU -PG. 62, ADDED PLACEMENT COMMENT ATTR. TO XW6200/1 - PAGE 74: CHANGED Q7401 AND Q7403 TO 376S0771 AS PER DAYU -PG. 67, ADDED PLACEMENT COMMENT ATTR. TO XW6700/1/10/11 NOTICE OF PROPRIETARY PROPERTY: BRANCH - PAGE 75: CHANGED R7525 TO 107S0132 FOR COST SAVING AS PER DAYU -PG. 68, ADDED PLACEMENT COMMENT ATTR. TO XW6851/80 - PAGE 78: DELETING P5VLTS3_EN RC CIRCUIT AS IT IS NO LONGER NEEDED (SEE ABOVE). ALSO UPDATED ASSOCIATED TEXT NOTE -PG. 66, REPLACED U6610/30 WITH LM48556 CKTS THE INFORMATION CONTAINED HEREIN IS THE - PAGE 97: FIXED CONNECTION POINT (DOT) FOR LCDBKLT_VIN -PG. 67, DELETED C6760/1/2/3. PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. - PAGE 97: ADDED 0 OHMS SERIES RESISTOR ON LCD_BKLT_PWM FOR DEBUGGING PURPOSES -PG. 67, CHANGEED J6703 TO TWO PIN CONN. THE POSESSOR AGREES TO THE FOLLOWING: PAGE - PAGE 97: RENAMED LCD_BKLT_PWM TO LVDS_IG_BKL_PWM -PG. 67, ADDED J6704 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE - PAGE 97: CHANGED VOVP VALUE TO 6.9V AS PER FREESCALE FEEDBACK -PG. 62, REPLACED C6225 WITH APN: 128S0216 - PAGE 97: ADDED R9726 (22K) AND SWAPPED C9705 AND R9705 LOCATIONS FOR NOISE REDUCTION AS PER FREESCALE RECOMMENDATION II NOT TO REPRODUCE OR COPY IT - PAGE 97: DELETED C9712 AS IT IS REDUNDANT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET - PAGE 97: ADDED PLACEMENT NOTE ATTRIBUTE TO C9713 AND C9710 FOR PLACING THOSE NEAR L9710
Revision History
Apple Inc.
051-7982 C.0.0
5 OF 109
IV ALL RIGHTS RESERVED
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Revision History
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NOTE: All page numbers are .csa, not PDF.
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See page 1 for .csa -> PDF mapping.
4/2/2009: RELEASE 9.3.0 (MAJOR): - PAGE 4:B ADDED 5.95MM SANYO PART 128S0288 AS ALTERNATE TO 128S0271 - PAGE 4:B ADDED 5.95MM SANYO PART 128S0286 AS ALTERNATE TO 128S0248 - PAGE 4: DELETED 152S0694 ALTERNATE ENTRY FOR 152S0138 AS IT IS NOT USED - PAGE 50: REPLACED DUAL Q5032 FET WITH TWO SINGLE Q5032 & Q5033 (APN 376S0612) N-CH FETS FOR ROUTING PURPOSES (SIL ANODE SIGNAL) - PAGE 54:B CHANGED R5412 TO 118OHM (114S0127) - PAGE 72: ADDED MIN_LINE/NECK_WIDTH ATTRIBUTES TO 5V_S3_DRVL, 3V3S5_VBST, 3V3S5_DRVL (FIXED THE NET NAME- ADDED UNDERSCORE) - PAGE 75: CHANGED L7560 TO APN 152S0526 - 0.68UH, 3.5MOHM,16A - AS PER DAYU - PAGE 75: CHANGED R7569 TO 11.3K APN 114S0319 FOR SETTING THE CORRECT OCSET AS PER DAYU - PAGE 97: CHANGED MIN_NECK_WIDTH ASSOCIATED WITH PPVOUT_S0_LCDBKLT TO 0.24MM AS THATS THE PIN WIDTH - PAGE 97: CHANGED MIN_LINE/NECK_WIDTH ASSOCIATED WITH GND_LCDBKLT_SGND TO 0.6/0.24MM ***PAGES SYNCED FROM DAVIDS AUDIO_MLB SINCE LAST RELEASE 9.2.0*** - REMOVED R6725 AND =PP3V3_S3_AUDIO CONNECTION TO MAX14504 ANALOG SWITCH 4/2/2009: RELEASE: 9.4.0 (MAJOR): - PAGE 97: ADDED A 1000PF CAP (C9727) ON LCDBKLT_VIN NEAR PIN 1 - PAGE 97: REPLACED C9717 WITH 1000PF CAP APN 132S0147 AND ADDED PLACEMENT NOTE AS PER JOHN SCHEN 4/2/2009: RELEASE: 9.5.0 (MAJOR): - PAGE 9: REPLACED Z0906,Z0907,Z0910 AND Z0911 MLB MOUNTING HOLES WITH 2.7 MM DIAMETER PLATED HOLES - APN 998-1584 4/3/2009: RELEASE: 9.6.0 (MAJOR): - PAGE 4: UNDER K84_PROGPARTS BOM GROUP, REPLACED BLANK P/N WITH PROGRAMMED P/N - PAGE 8: ADDED GLOBAL DIGITAL GROUND NET WITH MIN_LINE/NECK_WIDTH AND VOLTAGE ATTRIBUTES - PAGE 9: REPLACED Z0905 AND Z0913 MLB MOUNTING HOLES WITH 2.7 MM DIAMETER PLATED HOLES - APN 998-1584 - PAGE 9: DELETED GND MIN_LINE/NECK_WIDTH AND VOLTAGE ATTRIBUTES FROM FAN STANDOFF **PAGES SYNCED FROM LENGS AUDIO_MLB SINCE LAST RELEASE 9.5.0*** - REMOVED OPTIONAL STUFF-AROUND RESISTORS FOR ANALOG SWITCH - CONNECT AUDIO JACK SHIELD TO DIGITAL GROUND. 4/3/2009: RELEASE: 10.0.0 (RFA): - PAGE 9: ADDED 7 EXTRA TALL POGO PINS FOR EMI - 4 STUFFED AT THE BOTTOM, 3 UNSTUFFED ON THE TOP - PAGE 28: DELETED MAKE_BASE=TRUE ASSOCIATED WITH PCIE_RESET_L - PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH I2C_MIKEY_SCL/SDA_R - PAGE 69: REFRESHED J6955 SYMBOL - APN 516S0787 - PAGE 78: DELETED MAKE_BASE=TRUE ASSOCIATED WITH ALL_SYS_PWRGD - PAGE 78: DELETED SYNONYMS AS THEY ARE NOT NEEDED ANYMORE (DUE TO 0 OHMS) **PAGES SYNCED FROM LENGS AUDIO_MLB SINCE LAST RELEASE 9.6.0*** - ADDED 100PF EMC CAP ON THREE SPEAKER CONNECTORS. - CHANGED MIN_WIDTH OF CODEC HP OUT NETS. 4/5/2009: RELEASE 10.1.0 (MAJOR): - PAGE 4: ADDED CHGR_6258 BOM OPTION UNDER MODULE PARTS TABLE AND TO K84 MISC BOM GROUP. THIS IS TO STUFF ISL6258 PART - PAGE 9: ADDED ONE MORE TALL POGO PIN ON BOTTOM SIDE - PAGE 13: FIXED THE NOTE ON THE XDP PAGE- REPLACING 920-0620 ADAPTER BOARD WITH 920-0782 ADAPTER FLEX - PAGE 34: RENAMED P5VWLAN_SS NET TO P3V3WLAN_SS - PAGE 46: DELETED TEXT NOTE RELATED TO R4691 & R4690 AS IT IS NA TO K84 - PAGE 52: MOVED THE R5251 CONNECTION TO SENSOR ADC TO THE RIGHT SIDE TO SHOW A SEPARATE CONNECTION FOR CLARITY - PAGE 52: DELETED TEXT NOTE ON BATTERY LED DRIVER AS IT IS NA TO K84 - PAGE 69: PUT R6961 BEFORE C6955 TO GET RC FILTER. ALSO, FOR NOW, REPLACED R6961 WITH A 0 OHM RESISTOR AND NOSTUFFED C6955 - PAGE 70: ADDED OMIT BOM OPTION TO U7000 AS THIS PART WILL GET STUFFED WITH EITHER ISL6258 OR ISL6259 DEPENDING UPON PAGE 4 BOM TABLE - PAGE 70: FIXED Q7001 DRAIN-SOURCE ORIENTATION 4/6/2009 - RELEASE 10.1.1 (MINOR): **SCHEMATIC AND BOM CLEAN-UP** - PAGE 4: DELETED CHGR_6258 AND RENAMED 6259_NO TO CHGR_6259_NO. REPLACED CHGR_6258 WITH CHGR_6259_NO IN MODULE PARTS TABLE - PAGE 4: DELETED ENTRIES IN THE ALTERNATE BOM TABLE FOR THE FOLLOWING APN: 516-0213 AND 516S0709 - PAGE 8: DELETED =PP3V3_S3_AUDIO ALIAS AS IT IS NO LONGER APPLICABLE - PAGE 57: DELETED NO_TEST = TRUE ATTRIBUTE FROM Z2_SCLK AND Z2_MOSI AS THEY CONFLICT WITH FUNC_TEST ATTRIBUTE ON PAGE 7 - PAGE 69: RENAMED 6259_NO/YES TO CHGR_6259_NO/YES 4/6/2009 - RELEASE 11.0.0 (OK2FAB): - NO CHANGE SINCE LAST MINOR RELEASE 10.1.1 4/7/2009 - RELEASE 12.0.0 OK2FAB (RFA): - NO CHANGE SINCE LAST RFA RELEASE 11.0.0. ***THIS IS A RESUBMIT AS PREVIOUS RFA DIDNT GO THROUGH*** 4/23/2009 - RELEASE 12.1.0 (MAJOR): - PAGE 4: ADDED METAL PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO ADDED CORRESPONDING NOTES514-0691 ALTERNATE FOR 514-0690; 514-0689 ALTERNATE FOR 514-0688 - PAGE 13: REPLACED J1300 XDP CONNECTOR WITH MORE ROBUST CONNECTOR APN 998-2515 - PAGE 39: REPLACED J3900 ETHERNET CONNECTOR WITH POR PLASTIC CONNECTOR APN 514-0692 - PAGE 46: REPLACED J4600 & J4610 USB CONNECTORS WITH POR PLASTIC CONNECTOR APN 514-0688 - PAGE 75: CHANGE Q7560 AND Q7565 TO SIS426 APN 376S0749 PER RDAR://6812904 - PAGE 75: CHANGE R7565 TO 1OHM APN 113S0023 PER RDAR://6812904 - PAGE 76: CHANGED THE CPU VTT OVER CURRENT TRIP POINT PER RDAR://6792329 BY CHANGING R7604 FROM 8.87KN) TO 6.04KN) - PAGE 94: REPLACED J9400 DP CONNECTOR WITH POR PLASTIC CONNECTOR APN 514-0690 - PAGE 75: CHANGED C7565 AND C7568 TO CASE_B4_SM PACKAGE FROM CASE_B2_SM DUE TO PACKAGING ERROR (SAME APN)
05/08/2009: RELEASE 12.12.0 (MAJOR & WEEKLY ECO): - PAGE 4: DELETED SANYO 6.00MM OSCON CAPS 128S0248 & 128S0271 FROM THE ALTERNATE TABLE (MAKING ALTERNATES AS PRIMARY) - PAGE 4: TURNING ON BOM OPTION MCPSMC_DIGITEMP_YES AS POR IS TO CONNECT MIKEY TO MCP79 SMBUS 0 INSTEAD OF SMBUS 1 AND TO CONNECT SMC B SMBUS TO MCP79 SMBUS 1 - PAGE 4: ADDED A TEXT NOTE STATING THAT ADC CAN ONLY WORK IN S0 STATE AS IT HAS I2C BUS PU TO S0 POWER RAIL - PAGE 37: CHANGED C3714 AND C3715 TO 2.2UF APN 138S0642 TO FIX ETHERNET JITTER ISSUE - PAGE 50: CHANGED R5030 TO 63.4 OHMS APN 114S0102 TO INCREASE THE SIL CURRENT PER RDAR://PROBLEM/6752822 - PAGE 50: CHANGED R5714 TO 0 OHM APN 116S0004 PER RDAR://PROBLEM/6752822 - PAGE 52: CHANGED R5200, R5201, R5260 & R5261 TO 2K APN 116S0073 - PAGE 72: REPLACED C7252, C7291 & C7292 WITH 5.95MM SANYO APN 128S0288 - PAGE 72: REPLACED C7240 & C7282 WITH 5.95MM SANYO APN 128S0286 - PAGE 73: REPLACED C7331 & C7345 WITH 5.95MM SANYO APN 128S0286 - PAGE 77: CHANGED C7771 TO 47UF APN 138S0659 TO FIX ETHERNET JITTER ISSUE 05/10/2009: RELEASE 12.13.0 (MAJOR & WEEKLY ECO - THRU EMAIL): - PAGE 60: CHANGED R6003 AND R6004 TO 10 OHMS 5% RESISTOR VALUES RDAR://PROBLEM/6834630 05/11/2009: RELEASE 12.14.0 (MAJOR & WEEKLY ECO - THRU EMAIL): - PAGE 57 : CHANGED R5714 TO 165 OHMS APN 114S0141 AS PER RDAR://PROBLEM/6875543 - PAGE 72 : CHANGED C7252, C7291 & C7292 BACK TO ORIGINAL APN 128S0271 05/20/2009: AGILE RELEASE PROTO 2 - FINAL PROTO 2 OK2FAB RELEASE - UPDATED PAGE BORDERS TO NEW E4 05/22/2009: AGILE RELEASE PROTO 2 ***RETRY*** - FINAL PROTO 2 OK2FAB RELEASE - UPDATED PAGE BORDERS TO NEW E4 OK2FAB 13.0.0 (FAB): DSIZE STANDARDS OK2FAB 14.0.0 (FAB)DSIZE STANDARDS
08/31/2009: RELEASE 16.1.0 (MAJOR)- PAGE 4: REMOVED 138S0606 FROM THE ALTERNATES TABLE AS IT DOESNT PERTAIN TO K84 - PAGE 4: REPLACED CPU APN 337S3704 WITH 337S3769 IN MODULE PARTS TABLE AND REMOVED 337S3704 FROM THE ALTERNATE PART TABLE AS POR IS 337S3769 (P7550) - PAGE 4: REMOVE 870-1794, 870-1698 & 870-1820 FROM THE ALTERNATES TABLE AS POR IS LOW NOISE POGO PINS - PAGE 4: ADDED LOW NOISE POGO APNS 870-1885 (IN PLACE OF 870-1794), 870-1886 (IN PLACE OF 870-1698) & 870-1887 (IN PLACE OF 870-1820) IN MODULE PARTS TABLE - PAGE 4: ADDED NEW INTERSIL ISL6258A (WITH IMPROVED CHARGE CURRENT ACCURACY LIMITS) APN 353S2811 AS AN ALTERNATE FOR APN 353S1832 - PAGE 4: REMOVED 998S APN FROM THE ALTERNATES TABLE PERTAINING TO I/O CONNECTORS AS THEY ARE NO LONGER POR FOR DVT - PAGE 4: REMOVED 514-0706, 514-0705 AND 514-0718 FROM THE ALTERNATES TABLE AND ADDED TO MODULE PARTS TABLE AS THEY ARE NOW POR I/O CONNECTORS - PAGE 9: ADDED OMIT BOM OPTION ON ALL THE POGO PINS - PAGE 46: ADDED OMIT BOM OPTIONS TO J4600 & J4610 USB CONNECTORS - PAGE 67: ADDED OMIT BOM OPTION TO J6700 AUDIO CONNECTOR - PAGE 94: ADDED OMIT BOM OPTION TO J9400 MINI DP CONNECTOR - PAGE 97: UPDATED SCHEMATIC NOTE RELATED TO TARGET AND ACTUAL ISET & OVP NUMBERS AS PER KIRANS EMAIL 09/16/2009: RELEASE 17.0.0 (FAB)- FINAL DVT OK2FAB RELEASE 09/21/2009: RELEASE A.0.0 (FAB)- FINAL PVT OK2FAB RELEASE - PAGE 4: ADDED APN 104S0033 (6.8 OHMS, 1/4W) RESISTORS IN MODULE PARTS TABLE FOR R6612, R6617, R6630 & R6633 ADDED APN 518S0774 FOR XDP CONNECTOR J1300 (TO REPLACE 998-2515) - PAGE 13: ADDED OMIT TO J1300 - PAGE 50: CHANGED R5030 SIL RESISTOR TO 80.6 OHMS APN 114S0112 AS PER ID - PAGE 53: REPLACED APN 376S0545 WITH 376S0820 @ Q5315 - PER ECO#0000737172 - PAGE 66: ADDED BOMOPTION OMIT TO RESISTORS R6612, R6617, R6630 & R6633 10/12/2009: RELEASE B.0.0 (FAB)- PROD_DEBUG (POST FIRST 5K UNTIL 1 MONTH INTO PRODUCTION) OK2FAB RELEASE - PAGE 4: ADDED 1 NEW POR BOMS 639-0554, 639-0555 AND 1 NEW DEVELOPEMENT BOM 085-1076 FOR INITIAL RAMP - PAGE 4: UPDATED BOM GROUPS TABLE TO REFLECT AFOREMENTIONED CHANGES. NEW DEVELOPMENT BOM ONLY HAS XDP CONNECTOR AND LPCPLUS COMPONENTS - PAGE 4: ADDED 2 NEW EEES TO ATTACH WITH AFOREMENTIONED NEW 639 BOMS - PAGE 4: DELETED 353S2811 ENTRY FROM THE ALTERNATES TABLE - PAGE 70: REPLACED U7000 WITH THE NEW INTERSIL SCREENED PARTS APN 353S2811 11/01/2009: RELEASE C.0.0 (FAB)- PROD (POST 1ST MONTH OF PRODUCTION) OK2FAB RELEASE - PAGE 2: UPDATED SYSTEM BLOCK DIAGRAM - PAGE 3: UPDATED POWER SYSTEM BLOCK DIAGRAM - PAGE 4: UPDATED BOM TABLES TO NOT INCLUDE ANY 085 DEVELOPMENT BOMS. AND, K84_DEBUG_PROD BOM GROUP IS TURNED ON
06/09/2009: RELEASE 14.1.0 (MAJOR)- PAGE 4: REMOVING CHGR_6259_NO BOM OPTION AS ISL 6259 IS NOT POR - PAGE 4: ADDED NEW ISL PART APN 353S2718 AS AN ALTERNATE TO FIX B4 DONGLE ISSUE - PAGE 9: REPLACED ALL MEDIUM POGO PINS WITH APN 870-1794 (2 MM) AND ZS0916-ZS0918 WITH THINBC APN 870-1820 (2 MM) ONES - PAGE 59: ADDED R5922 10 OHMS SERIES R ON VDD SUPPLY TO FIX SMS NOISE ISSUE - PAGE 67: CHANGED J6704 TO A THREE PIN CONNECTOR 518S0520 - PAGE 69: REFRESHED J6955 SYMBOL (HALL EFFECT CONNECTOR) - PAGE 70: REMOVED CHGR_6259_YES/NO BOM ATTRIBUTES AS ISL 6259 IS NOT POR - PAGE 70: DELETED R7051 & R7053 CHGR_6259_YES BOM OPTIONS COMPONENTS - PAGE 70: REPLACING R7052 & R7054 CHGR_6259_NO BOM OPTION COMPONENTS WITH XW SHORTS- XW7052 & XW7054 - PAGE 70: REMOVED R7050 CHGR_6259_YES COMPONENT AS IT IS NOT NEEDED WITH ISL 6258 (PM_SLP_S3_L DIRECTLY CONNECTS TO ISL 6258 PIN) - PAGE 94: STUFFED C9485 AND CHANGED IT TO 22UF (APN 138S0654),CHANGED C9400 & C9481 TO 4.7UF (APN 138S0618) & CHANGED C9480 TO 22UF (APN 138S0654): TO FIX B4 DONGLE ISSUE ***PAGES SYNCED FROM CASEY HARDY?S AUDIO_MLB SINCE LAST RELEASE 14.0.0*** - ADDED R6862 PULL-UP RESISTOR TO PERPH. DETECT CKT. 06/10/2009: RELEASE 14.2.0 (MAJOR)- PAGE 4: ADDED APN 138S0661 LOW NOISE MURATA CAPS AS ALTERNATE FOR C9715 & C9716 TO FIX LCD BKLT AUDIBLE NOISE ISSUE - PAGE 49: ADDED 0.1UF CAPS ON SMS_X_AXIS, SMS_Y_AXIS & SMS_Z_AXIS NETS TO FIX NOISE ISSUE - PAGE 77: CHANGED R7780 TO 25.5K APN 114S0354 & R7781 TO 80.6K APN 114S0402 AS PER DAYU 06/11/2009: RELEASE 14.3.0 (MAJOR)- PAGE 77: ADDED 0 OHMS BOM OPTIONS R7782 BETWEEN PIN 4 OF U7750 (SKIP PIN) AND POWER RAIL AND R7783 BETWEEN PIN 4 AND GND. R7782 WILL BE NOSTUFF FOR NOW. THIS IS AS PER DAYU TO FIX ETHERNET JITTER ISSUE 06/11/2009: RELEASE 14.4.0 (MAJOR)- PAGE 49: REPLACED C4950-C4952 WITH 1UF APN 138S0640 CAPS - PAGE 78: DISCONNECTED P1V05_S5_PGOOD FROM PIN 3 OF U7840 AND CONNECTED IT TO PIN 1 (RSMRST_PWRGD) TO FIX LEAKAGE ISSUE 06/12/2009: RELEASE 14.5.0 (MAJOR)- PAGE 9: ADDED ONE MORE EXTRA TALL POGO PIN AS PER EMC RECOMMENDATION : ZS0920 - PAGE 78: ADDED 0 OHM BOM OPTION R7895 BETWEEN 1V05_S5_PGOOD AND RSMRST_PWRGD FOR DEBUG PURPOSES 06/22/2009: RELEASE 14.6.0 (MAJOR)- PAGE 4: ADDED CPU APN 337S3769 AS ALTERNATE TO 337S3704 - PAGE 9: ADDED NOSTUFF BOM OPTION TO ZS0920 - PAGE 50: CHANGED R5030 TO 48.7 OHMS APN 114S0091 (SIL CURRENT TO 12MA) - PAGE 57: CHANGED R5714 TO 113 OHMS APN 114S0125 (KB LED CURRENT TO 8.5MA) - PAGE 97: ADDED CRITICAL ATTRIBUTE TO C9715 & C9716 - PAGE 97: CHANGED R9710 TO 7.68K APN 114S0304 (LCD BKLT CURRENT TO 20MA) 06/25/2009: RELEASE 14.7.0 (MAJOR)- PAGE 70: DELETED OMIT BOM OPTION FROM U7000 AS ISL6259 HAVE BEEN REMOVED 07/17/2009: AGILE EVT OK2FAB RELEASE 15.0.0 (FAB)- NO CHANGES SINCE LAST MAJOR 14.7.0. THIS IS FINAL EVT FAB RELEASE 07/21/2009: RELEASE 15.1.0 (MAJOR)- PAGE 4: DELETED MIKEY_LOAD_DET BOM OPTION FROM THE TABLE UNDER K84_MISC CATEGORY AS PER CASEY - PAGE 4: UPDATED ALTERNATES FOR MINI DP AND USB CONNECTORS WITH PG2 PLASTIC CONNECTORS- APN 514-0706 (MDP) & 514-0705 (USB). AND, UPDATED NOTE BELOW THE ALTERNATES PARTS TABLE ACCORDINGLY - PAGE 4: ADDED PG2 CONNECTOR APN 514-0704 IN THE MODULE PARTS TABLE FOR RJ45 J3900 CONNECTOR - PAGE 4: DELETED 353S2310 PART FROM THE ALTERNATES BOM TABLE AS ALL PRODUCTION HAS NOW MOVED TO ITS ALTERNATE PART 353S2718 - PAGE 4: ADDED NEW INTERSIL PART APN 353S2718 IN THE MODULE PARTS TABLE FOR U7870 TO FIX B4 DONGLE ISSUE - PAGE 21: DELETED NOSTUFF BOM ATTRIBUTE FROM R2143 AS MIKEY_LOAD_DET CIRCUIT HAS BEEN REMOVED. SO R2143 NEEDS TO BE STUFFED NOW - PAGE 39: ADDED BOMOPTION ATTRIBUTE OMIT TO J3900 AS NEW PG2 CONNECTOR PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE - PAGE 78: ADDED BOMOPTION ATTRIBUTE OMIT TO U7870 AS NEW INTERSIL PART PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE 07/27/2009: RELEASE 15.2.0 (MAJOR)- PAGE 4: DELETED LOW NOISE MURRATA CAP ENTRY FROM THE ALTERNATES TABLE - PAGE 49: CHANGED SMS NOISE FILTERING CAPS C4950-C4952 TO 0.47UF APN 132S0178 TO FIX THE SMART TEST FAILURE - PAGE 70: DISCONNECTED PM_SLP_S3_L FROM PIN 4 (VREF) AS IT WAS INCORRECTLY CONNECTED, THEREBY CAUSING HIGHER SLEEP/SHUTDOWN POWER - PAGE 97: NOSTUFFED C9716 AND CHANGED C9715 TO APN 138S0661 AS POR IS TO HAVE SINGLE CAP LOW NOISE MURRATA CAP SOLUTION AS PER ACOUSTICS ENGINEER 08/05/2009: RELEASE 15.3.0 (MAJOR)- PAGE 4: ADDED APN 138S0606 (TAIYO-YUDEN) AS AN ALTERNATE FOR APN 138S0602 - PAGE 4: ADDED PDNI PLATED AUDIO CONNECTOR W/ CHAMFER APN 514-0718 AS AN ALTERNATE FOR J6700 APN 514-0694 - PAGE 4: ADDED GOLD PLATED AUDIO CONNECTOR W/O CHAMFER APN 998-2622 AS AN ALTERNATE FOR J6700 APN 514-0694 - PAGE 4: ADDED GOLD PLATED RJ45 CONNECTOR APN 998-2621 AS AN ALTERNATE FOR J3900 APN 514-0704 - PAGE 4: ADDED GOLD PLATED MINI DP CONNECTOR APN 998-2626 AS AN ALTERNATE FOR J9400 APN 514-0691 - PAGE 4: ADDED GOLD PLATED USB CONNECTOR APN 998-2624 AS AN ALTERNATE FOR J4600/J4610 APN 514-0689 - PAGE 4: ADDED LOW NOISE POGO PINS 870-1885 (MEDIUM), 870-1886 (TALL), AND 870-1887 (THIN) AS ALTERNATES - PAGE 49: CHANGED C4950, C4951, C4952 TO APN:132S0131 (CAP,0402,0.033UF, 16V,10%) AS THESE WOULD BE USED TO ACHIEVE CUT-OFF FREQUENCY OF ~146HZ FOR SMS (AS PER THE VENDOR) AND FILTER THE NOISE TOO AS SEEN BY SMC CHIP. CAPS ON SMS PAGE WOULD BE UNSTUFFED - PAGE 59: ADDED NOSTUFF BOM OPTION ATTRIBUTE TO C5923-C5925 AS STATED ABOVE. ALSO, EDITED THE NOTE ACCORDINGLY - PAGE 70: CHANGED R7031 FROM 10 OHM TO 2.2 OHM, 5%, APN:116S0010 TO FIX SLOW CHARGING ISSUE, PER DAYU - PAGE 70: CHANGED R7047 FROM 10 OHM TO 0 OHM, 5%, APN:116S0004 TO FIX SLOW CHARGING ISSUE, PER DAYU - PAGE 70: CHANGED C7043 FROM 0.1UF TO 1UF, 10%, APN:138S0640 TO FIX SLOW CHARGING ISSUE, PER DAYU 08/27/2009: AGILE PDFC OK2FAB RELEASE 16.0.0 (FAB)- FINAL PDFC (PRE DVT) RELEASE! - PAGE 97: REFRESHED THE SYMBOL OF C9715 4.7UF APN 138S0661
4/24/2009 - RELEASE 12.2.0 (MAJOR): **PAGES SYNCED FROM CASEYS AUDIO_MLB SINCE LAST RELEASE 12.1.0*** - REPLACED J6700 WITH APN: 514-0694 - ADDED DZ 6702 AND L6706 - CONNECTED R6860 TO AUD_IP_PERPH_DET 4/27/2009 - RELEASE 12.3.0 (MAJOR & WEEKLY ECO): - PAGE 4: ADDED NEW BOM ENTRY 639-0254 FOR MOLEX DDR3 CONNECTOR CONFIG. ALSO, EDITED 639-0035 BOM NAME TO REFLECT FOXCONN DDR3 CONNECTOR. ADDED TWO ENTRIES (J3200 AND J3100) FOR FOXCONN AND TWO FOR MOLEX UNDER MODULE PARTS TABLE . - PAGE 74: CHANGED C7432 TO 0.001UF AS PER RDAR://6792327 - PAGE 74: UNSTUFFED C7434 AS PER RDAR://6792327 - PAGE 74: CHANGED C7428 TO 0.47UF AS PER RDAR://6792327 - PAGE 74: CHANGED R7415 TO 10.5K AS PER RDAR://6792327 - PAGE 97: CHANGED R9716 FROM 226K TO 243K TO CHANGE THE OVP POINT TO 35.3V AS PER KIRAN 4/28/2009: RELEASE 12.4.0 (MAJOR): - PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS FOR EMI PURPOSES - L6707 & L6708
APN 155S0367 ON RIGHT PIEZO SPEAKER
4/28/2009: RELEASE 12.5.0 (MAJOR): - PAGE 67: MOVED L6707 & L6708 TO J6703 (FULL RANGE SPEAKER CONNECTOR) BETWEEN CAPS AND CONNECTOR 4/29/2009: RELEASE 12.6.0 (MAJOR & WEEKLY ECO): - PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER J6704 FOR EMI PURPOSES - L6709 & L6710 - PAGE 97: CHANGED L9710 TO A BIGGER 2525 PACKAGE (LOW DCR) APN 152S0585 FOR BETTER EFFICIENCY 4/29/2009: RELEASE 12.7.0 (MAJOR & WEEKLY ECO): - PAGE 97: CHANGED L9710 BACK TO THE ORIGINAL APN 152S0826 AS 2525 PACKAGE CANT FIT IN 5/01/2009: RELEASE 12.8.0 (MAJOR): - PAGE 4: ADDED A36 EEE NUMBER FOR NEW BOM CONFIGURATION 639-0254 - PAGE 60: ADDED 0 OHMS SERIES RESISTORS R6003 AND R6004 ON AVDD AND DVDD SUPPLY RAILS TO ADC CHIP - PAGE 60: CHANGED R6001 & R6002 TO 33 OHMS RESISTORS TO FIX UNDERSHOOT ON I2C BUS 05/01/2009: RELEASE 12.9.0 (MAJOR): - PAGE 4: UPDATED PLASTIC PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO ADDED CORRESPONDING NOTES514-0690 PLASTIC ALTERNATE FOR 514-0691 METAL; 514-0688 PLASTIC ALTERNATE FOR 514-0689 METAL - PAGE 46: REPLACED PLASTIC USB CONNECTORS WITH METAL APN 514-0689 PARTS - PAGE 94: REPLACED PLASTIC MINI DP CONNECTOR WITH METAL APN 514-0691 PART 05/04/2009: RELEASE 12.10.0 (MAJOR): - PAGE 4: REMOVED SHORT POGO PIN ALTERNATE - PAGE 4: REVERTING MCP TO EARLIER USE APN 338S0710 - PAGE 60: CHANGED U6050 INA 211 PART TO 200X GAIN INA 210 APN 353S2073 05/05/2009: RELEASE 12.11.0 (MAJOR & WEEKLY ECO): - PAGE 4: ADDED 4 QUANTITIES OF DIMM CONNECTOR SCREWS APN 452-1708 - PAGE 46: ADDED NOTE ABOUT USING METAL PARTS SCHEMATIC AND CAD SYMBOLS THOUGH POR IS PLASTIC USB CONNECTOR PART - PAGE 94: ADDED NOTE ABOUT USING METAL PARTS SCHEMATIC AND CAD SYMBOLS THOUGH POR IS PLASTIC MINI DP CONNECTOR PART
SYNC_MASTER=K24_MLB
PAGE TITLE
Revision History
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

6 OF 109
SHEET
Functional Test Points

POWER NETS TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE FUNC_TEST
8 8 8 8 8 8 8 7 8 8 8 7 8 8 8 8 7 8 8 8 8 21 22 25 7 30 7 34 47 7 34 36 37 7 45 7 45 7 65 7 47 65 68 49 36 57 63 21 36 37 63 21 32 36 63 67 7 65
FAN CONNECTORS FUNC_TEST
X16 WIRELESS CONN

7 8 43 43
I303 I301 I302 I300 I299
FUNC_TEST
I287 I285 I284 I280 I281
I12 I15 I16
TRUE TRUE TRUE
PP5VRT_S0 FAN_RT_PWM FAN_RT_TACH

(NEED TO ADD 1 GND TP)
MIC FUNC_TEST
I238 I237 I239
I298 I293
TRUE TRUE TRUE
BI_MIC_LO BI_MIC_HI BI_MIC_SHIELD
53 54
I288
53 54
I292
53 54
I295 I290 I271
I227 I226 I228 I230 I229 I231
SPEAKER FUNC_TEST SPKRAMP_L_N_OUT TRUE SPKRAMP_L_P_OUT TRUE SPKRAMP_R_N_OUT TRUE SPKRAMP_R_P_OUT TRUE SPKRAMP_SUB_N_OUT TRUE SPKRAMP_SUB_P_OUT TRUE
52 53 52 53
I289
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP3V3_S3_BT_F 30 CONN_PCIE_MINI_D2R_P 30 72 CONN_PCIE_MINI_D2R_N 30 72 CONN_PCIE_MINI_R2D_P 30 72 CONN_PCIE_MINI_R2D_N 30 72 PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N PP3V3_WLAN 7 30 (NEED PCIE_WAKE_L 17 30 CONN_USB2_BT_P 30 73 CONN_USB2_BT_N 30 73 MINI_CLKREQ_Q_L 30 MINI_RESET_CONN_L 30
30 72
I282
30 72
I376
2 TP)
I396
I283 I279 I278 I270 I379 I273
52 53
I274
52 53
I275
52 53
I276
52 53
I272 I393
IPD_FLEX_CONN
I375 I374 I372 I370
FUNC_TEST
7 45 7 45
I392 I391 I390 I389
I259 I258
I260 I245 I262 I261 I256 I257 I255 I252 I253 I254 I250 I251 I313 I246 I247 I248 I249 I395
I297 I294
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
LVDS FUNC_TEST PP3V3_LCDVDD_SW_F PP3V3_S0_LCD_F PPVOUT_S0_LCDBKLT LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<2> LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 PP5V_S3_CAMERA_F USB_CAMERA_CONN_P USB_CAMERA_CONN_N
7 65 65
(NEED 2 TP) (NEED 2 TP)
I371 I369 I368 I361 I366 I365 I363 I364 I362 I360 I359 I357 I358 I377 I378
7 47 65 68 18 65 18 65 18 65 72 18 65 72 18 65 72 18 65 72 18 65 72 18 65 72 65 72 65 72 65 68 65 68 65 68 65 68 65 68 65 68 7 65
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP3V3_S3_LDO PP18V5_S3 Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL PSOC_F_CS_L PICKB_L
44 45 44 45 44 45 44 45
I385 I388 I387 I386
44 45 45 44 45 44 45
I380 I383 I382 I381
44 45 44 45 44 45 44 45 44 45 39 75 39 75 44 45 44 45
I312 I304
PPVCORE_S0_CPU PPVCORE_S0_MCP PP0V75_S0 PP1V05_S0 PP1V5_S0 PP1V8_S0 PP5VLT_S0 PP5VRT_S0 PP3V3_S0 PP1V5_S3 PP3V3_S3 PP5V_S3 PP1V1R1V05_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET_PHY PP1V2R1V05_ENET PP3V3_G3_RTC PP3V3_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP3V3_S5_AVREF_SMC PP18V5_S3 PP3V3_S3_LDO PP3V3_LCDVDD_SW_F PPVOUT_S0_LCDBKLT PP4V5_AUDIO_ANALOG SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L PP5V_S3_CAMERA_F
I397
DC POWER CONN TRUE TRUE
FUNC_TEST
(NEED 2 TP) 55
55
PP18V5_DCIN_FUSE ADAPTER_SENSE
KEYBOARD CONN
I354
FUNC_TEST
7 8 7 8 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44 44
65 73 65 73
I355 I344 I345 I346 I347
SATA ODD CONN

I264
FUNC_TEST
(NEED 2 TP)
7 34 47 34 36 34 72 34 72 34 72
I349 I348 I350 I352 I351 I353 I327
I268 I269 I267 I265 I266
TRUE TRUE TRUE TRUE TRUE TRUE
PP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N

34 72
I328 I329
SATA HDD/SIL
I319 I314 I315 I318 I317 I307
FUNC_TEST
(NEED 2 TP)
7 34 34 72 34 72 34 72
I343 I342
TRUE TRUE TRUE TRUE TRUE TRUE
PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SYS_LED_ANODE_R

I341 I339 I340 I338 I336
34 72 34
I337 I333 I335 I334 I332 I330 I331
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD
BATT POWER CONN

I322 I321 I320
FUNC_TEST
39 75 39 75 55 55 56
I305
TRUE TRUE TRUE TRUE
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SYS_DETECT_L BATT_POS_F

(NEED 2 TP)
SYNC_MASTER=K24_MLB
PAGE TITLE
FUNC TEST
HALL EFFECT CONNECTOR
I326 I308
FUNC_TEST
7 8 55
R
DRAWING NUMBER
SIZE
TRUE TRUE
PP3V42_G3H SMC_LID_R
Apple Inc.
051-7982
REVISION
C.0.0
BRANCH PAGE
7 OF 109
SHEET
7
"S0,S0M" RAILS
4
"S3" RAILS
58
2
"G3H" RAILS
7 55
=PP1V5_S3_REG
59
=PPVCORE_S0_CPU_REG
(CPU VCORE PWR)
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=1.25V MAKE_BASE=TRUE
64 7
=PP5VRT_S0_FET
PP5VRT_S0
MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE
PP1V5_S3
MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V MAKE_BASE=TRUE
=PP3V42_G3H_REG
PP3V42_G3H
=PP1V5_S3_P1V5S0FET
61 38 43 59 64
=PPVCORE_S0_CPU =PPVCORE_S0_CPU_VSENSE
=PP5V_S0_CPUVTTS0
11 12 40
64 27 28 29
=PPVIN_S5_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD

=PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PP3V42_G3H_RTC_D =PP3V42_G3H_ONEWIRE =PP3V42_G3H_HALL
37 39 63 56 35 44 36 37 38 25 55 55
=PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_MEMRESET =PP3V3_S3_FET PP3V3_S3

=PP5V_S0_LPCPLUS =PP5V_S0_FAN_RT
D
61
=PP5V_S0_CPU_IMVP
=PPCPUVTT_S0_REG PP1V05_S0
64 7
=PP5VLT_S0_FET
PP5VLT_S0
MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE
=PP5V_S0_DP_AUX_MUX
10 11 12 13 14 22 23
=PP1V05_S0_CPU =PP1V05_S0_MCP_FSB =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_VMON =PP1V05_S0_MCP_PLL_UF_R
66 34 60 63
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_PDCISENS
39 58 39 26 30 21 44 46 55 30
=PP5V_S0_HDD =PP5V_S0_MCPREG =PP5V_S0_VMON
=PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_MCP_GPIO
8 23 23 8 23 64 18 24 63 62
=PP3V3_S0_FET
PP3V3_S0
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE
=PP3V3_S3_TPAD =PP3V3_S3_SMS =PP3V3_S3_BT
=PP18V5_DCIN_CONN
PP18V5_G3H
=PP3V3_S0_XDP =PP3V3_S0_MCP =PP3V3_S0_MCP_DAC_UF =PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_ODD =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0

7
13 21 22 23 24 57 24 34 39 39 39 43 49 53 54 59 65 18 19 21
=PP18V5_G3H_CHGR =PP5V_S3_REG PP5V_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE
7
56
56 35
=PPBUS_G3H
PPBUS_G3H
=PP5V_S3_EXTUSB =PP5V_S3_CAMERA =PP5V_S3_AUDIO_AMP =PP5V_S3_MCPDDRFET =PP5V_S3_1V5S30V75S0 =PP5V_S3_AUDIO =PP5V_S3_P5VLTS0FET =PP5V_S3_VTTCLAMP
60
=PPMCPCORE_S0_REG
(MCP VCORE AFTER SENSE RES)
PPVCORE_S0_MCP
=PP3V3_S0_SMBUS_MCP_0 =PP3V3_S0_FAN_RT =PP3V3_S0_AUDIO

22 23
65 52 64 58 49 51 53 64 64 47 37 45 34 47 47 64
=PPVIN_S0_MCPCORE =PPVIN_S5_1V5S30V75S0 =PPCPUVCORE_VTT_ISNS_R

(BEFORE HIGH SIDE SENSING RES.)
60 58 41
=PPVCORE_S0_MCP =PPVCORE_S0_MCP_VSENSE
40
=PP3V3_S0_IMVP
=PP3V3_S0_LCD =PP3V3_S0_MCP_GPIO
C
58
=PP3V3_S0_MCP_PLL_UF
=PP0V75_S0_REG PP0V75_S0
7
23 21 23
C
=PPBUS_S0_LCDBKLT =PPVIN_S5_3V3S5 =PPVIN_S3_5VS3 =PPBUS_G3HRS5
69 57 57 40
=PP3V3R1V5_S0_MCP_HDA =PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_DPCONN =PPSPD_S0_MEM_A =PPSPD_S0_MEM_B =PP3V3_S0_PWRCTL =PP3V3_S0_VMON =PP3V3_S0_CPUVTTISNS
7
=PP5V_S3_DEBUG_ISNS
37 42 42 67 27 28 63 63 41
=PP5V_S3_SYSLED =PP5V_S3_TPAD =PP5V_S3_ODD =PP5V_S3_DEBUG_ADC_AVDD =PP5V_S3_DEBUG_ADC_DVDD =PP5V_S3_P5VRTS0FET
=PPVTT_S0_VTTCLAMP =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B
64 27 28
64
=PP1V5_S0_FET
PP1V5_S0
=PP3V3_S0_SMBUS_MCP_1 =PP3V3_S0_P1V8S0
11 12 63 16 23 28
39 62 62 41
=PP1V5_S0_CPU =PP1V5_S0_VMON =PP1V8R1V5_S0_MCP_MEM =PP1V5_S0_MEM_MCP =PP1V5_S0_MCP_PLL_VLDO
=PP3V3_S0_MCP_PLL_VLDO =PP3V3_S0_MCPDDRISNS
58 26 62
=PPVTT_S3_DDR_BUF
PPVTT_S3_DDR_BUF
41
=PPCPUVCORE_VTT_ISNS (AFTER HIGH SIDE CPU VCORE
PPBUS_G3H_CPU_ISNS
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE
62
=PP1V8_S0_REG
PP1V8_S0
MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=1.8V MAKE_BASE=TRUE
& CPU VTT SENSING RES.)
=PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP
"S5" RAILS
18 24 49
61 59
=PP3V3R1V8_S0_MCP_IFP_VDD
B
62 23
=PP1V8_S0_AUDIO
"ENET" RAILS
32
62
=PP1V05_S5_REG
PP1V1R1V05_S5
=PP3V3_ENET_FET
PP3V3_ENET_PHY
PP1V05_S0_MCP_PLL_UF
=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET
18 23
22 23 32
=PP3V3_ENET_MCP_RMGT =PP3V3_ENET_PHY
31
DIGITAL GROUND GND

32
=PP1V05_ENET_FET
PP1V2R1V05_ENET
7 57
=PP3V3_S5_REG
PP3V3_S5
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=0V
=PP1V05_ENET_MCP_PLL_MAC =PP1V05_ENET_MCP_RMGT =PP1V05_ENET_PHY
23
=PP3V3_S5_MCP_GPIO
18 23
18 20 38 48 65 22 23 25 63 32 64 64 62 29 32 67
=PP3V3_S5_ROM =PP3V3_S5_LCD =PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD
31
PEX & SATA AVDD/DVDD aliases

=PP1V05_S0_MCP_PEX_AVDD0
23 17
=PP3V3_S5_PWRCTL =PP3V3_S5_P1V05ENETFET =PP3V3_S5_P3V3S3FET =PP3V3_S5_P3V3S0FET

206 mA (A01)
17
PP1V05_S0_MCP_PEX_AVDD
MAKE_BASE=TRUE
=PP3V3_S5_P1V05S5 =PP3V3_S5_MEMRESET =PP3V3_S5_P3V3ENETFET
206 mA (A01)
23 8
=PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_DVDD1
17
=PP1V05_S0_MCP_PEX_DVDD 206 mA (A01)
57 mA (A01)
17
=PP3V3_S5_DP_PORT_PWR
SYNC_MASTER=K24_MLB
=PP1V05_S0_MCP_SATA_AVDD0 =PP1V05_S0_MCP_SATA_AVDD1
20
23
PP1V05_S0_MCP_SATA_AVDD
MAKE_BASE=TRUE
PAGE TITLE
127 mA (A01)
20
127 mA (A01)
23 8
Power Aliases
DRAWING NUMBER SIZE
=PP1V05_S0_MCP_SATA_DVDD 127 mA (A01)
=PP1V05_S0_MCP_SATA_DVDD0 =PP1V05_S0_MCP_SATA_DVDD1
20
43 mA (A01)
20
R
Apple Inc.
051-7982
REVISION
C.0.0
BRANCH PAGE
8 OF 109
SHEET
7
HEATSINK STANDOFFS
Z0902 Z0901
STDOFF-4.5OD.98H-1.1-3.48-TH
1
6
PCI-E ALIASES
UNUSED GPU LANES
17
5
=PEG_D2R_N<15:0> =PEG_D2R_P<15:0> =PEG_R2D_C_N<15:0> =PEG_R2D_C_P<15:0> PEG_PRSNT_L PEG_CLK100M_P PEG_CLK100M_N NC_PEG_D2R_N<15:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
4
DACS ALIASES
UNUSED CRT & TV-OUT INTERFACE
18
3
NC_MCP_TV_DAC_RSET
NO_TEST=TRUE
MAKE_BASE=TRUE
2
SO-DIMM ALIASES
UNUSED ADDRESS PINS
27 28
1
TP_MEM_A_A15 TP_MEM_B_A15
MAKE_BASE=TRUE MAKE_BASE=TRUE
MCP_TV_DAC_RSET MCP_TV_DAC_VREF MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC
17
NC_PEG_D2R_P<15:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
MEM_A_A<15> MEM_B_A<15>
STDOFF-4.5OD.98H-1.1-3.48-TH
1
18
NC_MCP_TV_DAC_VREF
NO_TEST=TRUE
MAKE_BASE=TRUE
17
NC_PEG_R2D_C_N<15:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
18
NC_MCP_CLK27M_XTALIN
NO_TEST=TRUE
MAKE_BASE=TRUE
17
NC_PEG_R2D_C_P<15:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
18
NC_MCP_CLK27M_XTALOUT
NO_TEST=TRUE
MAKE_BASE=TRUE
LEFT OF CPU
ABOVE CPU
17
TP_PEG_PRSNT_L
MAKE_BASE=TRUE
18
NC_CRT_IG_R_C_PR
NO_TEST=TRUE
MAKE_BASE=TRUE
ETHERNET ALIASES
MAKE_BASE=TRUE
17
TP_PEG_CLK100M_P
MAKE_BASE=TRUE
Z0903
Z0904
STDOFF-4.5OD.98H-1.1-3.48-TH
1
17
18
NC_CRT_IG_G_Y_Y
NO_TEST=TRUE
TP_PEG_CLK100M_N
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
1
18
NC_CRT_IG_B_COMP_PB
NO_TEST=TRUE
MAKE_BASE=TRUE
32 32
MAKE_BASE=TRUE
=P3V3ENET_EN =P1V05ENET_EN =PP3V3_ENET_PHY_VDDREG =RTL8211_REGOUT =RTL8211_ENSWREG

31
PM_SLP_RMGT_L
MAKE_BASE=TRUE
21
UNUSED EXPRESS CARD LANE

17
18
NC_CRT_IG_HSYNC
NO_TEST=TRUE
31 31
RTL8211_VDDREG NC_RTL8211_REGOUT
PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_PRSNT_L EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N
TP_PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
18
NC_CRT_IG_VSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
BELOW MCP
BELOW CPU
17
TP_PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE
31
FAN STANDOFF
OMIT
TP_RTL8211_CLK125
RTL8211_CLK125
MAKE_BASE=TRUE
17
TP_PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE
LVDS ALIASES
18
Z0905
3P2R2P7
1
17
TP_PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE
R0931
22
5% 1/16W MF-LF 402
17
TP_PCIE_EXCARD_PRSNT_L
MAKE_BASE=TRUE
LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3> LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P<3:0> LVDS_IG_B_DATA_N<3:0>
NC_LVDS_IG_A_DATA_P3
NO_TEST=TRUE
MAKE_BASE=TRUE
17
TP_EXCARD_CLKREQ_L
MAKE_BASE=TRUE
18
NC_LVDS_IG_A_DATA_N3
NO_TEST=TRUE
MAKE_BASE=TRUE
18 17
NC_LVDS_IG_B_CLK_P
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCIE_CLK100M_EXCARD_P
MAKE_BASE=TRUE
18 17
NC_LVDS_IG_B_CLK_N
NO_TEST=TRUE
MAKE_BASE=TRUE
TP_PCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE
18
NC_LVDS_IG_B_DATA_P<3:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
UNUSED FIREWIRE LANE
MLB MOUNTING (TO C. BRACKET) SCREW HOLES

OMIT OMIT
72 17
PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_PRSNT_L FW_CLKREQ_L

PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N
TP_PCIE_FW_D2R_P
MAKE_BASE=TRUE
18
NC_LVDS_IG_B_DATA_N<3:0>
NO_TEST=TRUE
MAKE_BASE=TRUE
CPU FSB FREQUENCY STRAPS

BSEL<2..0> 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 FSB MHZ 266 133 200 (166) 333 100 (400) (RSVD) CPU_BSEL<0:2> MAKE_BASE=TRUE =MCP_BSEL<0:2>
72 17
TP_PCIE_FW_D2R_N
MAKE_BASE=TRUE
Z0906
3P2R2P7
1
Z0907
3P2R2P7
1
72 17 72 17
TP_PCIE_FW_R2D_C_P
MAKE_BASE=TRUE
70 10
TP_PCIE_FW_R2D_C_N
MAKE_BASE=TRUE
MISC MCP79 ALIASES

14
IN
OUT
14
CPU_PECI_MCP FW_PME_L GMUX_JTAG_TCK_L GMUX_JTAG_TDO GMUX_JTAG_TDI GMUX_JTAG_TMS MCP_GPIO_4 CARDREADER_RESET
TP_CPU_PECI_MCP
MAKE_BASE=TRUE
17
TP_PCIE_FW_PRSNT_L
MAKE_BASE=TRUE
19 17
TP_FW_PME_L
MAKE_BASE=TRUE
17
TP_FW_CLKREQ_L
MAKE_BASE=TRUE
TP_GMUX_JTAG_TCK_L
MAKE_BASE=TRUE
17 17
TP_GMUX_JTAG_TDO
MAKE_BASE=TRUE
TP_PCIE_CLK100M_FW_P
MAKE_BASE=TRUE
C
MLB MOUNTING (TO TOPCASE) SCREW HOLES
OMIT OMIT
19 19
TP_GMUX_JTAG_TDI
MAKE_BASE=TRUE
17
TP_PCIE_CLK100M_FW_N
MAKE_BASE=TRUE
TP_GMUX_JTAG_TMS
MAKE_BASE=TRUE
SMC ALIASES
54 36
C
MAKE_BASE=TRUE
21 17
MIKEY_MIC_LOAD_DET
MAKE_BASE=TRUE
TP_CARDREADER_RESET
MAKE_BASE=TRUE
SMC_SYS_KBDLED
TP_SMC_SYS_KBDLED
Z0911
3P2R2P7
1
Z0910
3P2R2P7
1
20 20 20
USB ALIASES
UNUSED USB PORTS
LAN ALIASES
18
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
USB_EXTD_P USB_EXTD_N USB_EXCARD_P USB_EXCARD_N

USB_MINI_P USB_MINI_N
TP_USB_EXTD_P TP_USB_EXTD_N TP_USB_EXCARD_P TP_USB_EXCARD_N

TP_USB_MINI_P
MAKE_BASE=TRUE
=MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS
MCP_MII_PD
MAKE_BASE=TRUE
18 18
R0930
47K
5% 1/16W MF-LF 402
59
CPU VCORE ALIASES

IMVP6_VR_TT IMVP6_NTC TP_IMVP6_VR_TT
MAKE_BASE=TRUE
LVDS CONNECTOR HOLE

3P2R2P7
1
20 20
Z0913
OMIT
20
TP_USB_MINI_N
MAKE_BASE=TRUE
20 20 73 20 73 20 73 20 73 20
USB_EXTC_P USB_EXTC_N USB_CARDREADER_P USB_CARDREADER_N USB_IR_N USB_IR_P
TP_USB_EXTC_P TP_USB_EXTC_N TP_USB_CARDREADER_P TP_USB_CARDREADER_N TP_USB_IR_N TP_USB_IR_P

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
DP HOTPLUG PULL-DOWN
59
TP_IMVP6_NTC
MAKE_BASE=TRUE
18
=DVI_HPD_GMUX_INT
HPLUG_DET2
MAKE_BASE=TRUE
R0940
20K
5% 1/16W MF-LF 402
EMI IO MEDIUM POGO PINS (870-1794 )

OMIT OMIT OMIT OMIT
ZS0900 2.0DIA-MED-EMI-MLB-K84
SM
1
SM
1
SM
1
SM
1
B
OMIT OMIT OMIT
B
SM
1 1
SM
SM
1
EMI TALL POGO PINS (870-1698 )

OMIT ZS0904
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1 1
OMIT ZS0905
SM
OMIT ZS0906
SM
1
OMIT ZS0907
SM
1
OMIT ZS0910
SM
OMIT ZS0912
SM
OMIT ZS0913
SM
OMIT ZS0914
SM
OMIT ZS0915
SM
OMIT ZS0919
SM
A
EMI THINBC POGO PINS (870-1820 )
OMIT ZS0917
2.0DIA-MLB-THIN-BC-K84
SM
SYNC_MASTER=K24_MLB
PAGE TITLE
SIGNAL ALIAS
DRAWING NUMBER SIZE
Apple Inc.
OMIT ZS0918
SM
051-7982
REVISION
OMIT ZS0916
SM
NOSTUFF
ZS0920
SM
C.0.0
BRANCH PAGE

1 1 1
9 OF 109
SHEET
8
70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14
7
OMIT
6
ADS* BNR* BPRI* DEFER* DRDY* DBSY*
H1 E2 G5
5
14 70 14 70 14 70
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_ADSTB_L<0>
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
70 14 70 14 70 14 70 14 70 14
A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0*
U1000
PENRYN
FCBGA
FSB_ADS_L FSB_BNR_L FSB_BPRI_L
BI BI BI
1 OF 4
=PP1V05_S0_CPU
14 70 14 70 14 70
1
8 11 12 13
H5 F21 E1
FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L
BI BI BI
R1000
54.9
1% 1/16W MF-LF 402
ADDR GROUP0
BR0* CONTROL IERR* INIT* LOCK*
F1
FSB_BREQ0_L
BI
14 70
D20 B3
70 CPU_IERR_L
CPU_INIT_L
D
IN
14 70
H4
FSB_LOCK_L
BI
14 70
70 14 70 14 70 14 70 14 70 14
BI BI BI BI BI
FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>
K3 H2 K2 J3 L1
REQ0* REQ1* REQ2* REQ3* REQ4*
RESET* RS0* RS1* RS2* TRDY*
C1 F3 F4 G3 G2
FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L
IN IN IN IN IN
13 14 70 14 70 14 70 14 70 14 70
70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
70 14 70 14 70 14 70 14 70 14 70 14 70 14
A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1* A20M* FERR* IGNNE*
HIT* HITM* BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR*
G6 E4
FSB_HIT_L FSB_HITM_L
BI BI
14 70
OMIT
14 70 70 14
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L
BI BI BI BI BI
13 70 13 70 13 70 13 70 13 70
70 14 70 14 70 14 70 14
R1001
54.9
1% 1/16W MF-LF 402
70 14
BI IN IN OUT IN IN OUT
10 13 70 10 13 70 10 13 70 10 13 70 10 13 70 13 25
1
13 70
70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14
R1002
68
THERMAL PROCHOT* THERMDA THERMDC THERMTRIP* ICH

CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N
5% 1/16W MF-LF 402
70 14
D21 A24 B25
OUT OUT OUT

42 76 42 76
14 37 70
70 14 70 14
D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0*
U1000
PENRYN
FCBGA
ADDR GROUP1
2 OF 4
D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2*
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70
XDP/ITP SIGNALS
DATA GRP 0
DATA GRP 2
70 14 70 14 70 14
IN OUT IN
CPU_A20M_L CPU_FERR_L CPU_IGNNE_L
A6 A5 C4
C7
PM_THRMTRIP_L
OUT
14 37 70
70 14 70 14
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
70 14 70 14 70 14 70 14
IN IN IN IN
CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L
D5 C6 B4 A3
STPCLK* LINT0 LINT1 SMI* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8
H CLK
70 14 70 14 70 14
BCLK0 BCLK1
A22 A21
FSB_CLK_CPU_P FSB_CLK_CPU_N
IN IN
14 70 14 70
70 14 70 14 70 14
TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2 TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3
M4 N5 T2 V3 B2 F6 D2 D22 D3
70 14 70 14 70 14
RESERVED
70 14 70 14 70 14 70 14
1
70 14
R1005
70 14 70 14 70 14
CPU JTAG Support
1K
1% 1/16W MF-LF 402
B
70 13 10
D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2
D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* COMP0 COMP1 COMP2 COMP3 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70 14 70
DATA GRP 1
DATA GRP 3
R1090
54.9
2
2
XDP_TMS
1 1%
70 26 CPU_GTLREF
AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21
MISC
R26 U26 AA1 Y1
70 CPU_COMP<0> 70 CPU_COMP<1> 70 CPU_COMP<2> 70 CPU_COMP<3>
CPU_TEST1
1
R1091
54.9
70 13 10
1/16W MF-LF 402 2
R1006
2.0K
1% 1/16W MF-LF 402
CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 NO STUFF TP_CPU_TEST5

1
XDP_TDI
1 1% 1/16W MF-LF 402
R1092
54.9
1 1% 1/16W MF-LF 402 2
E5 B5 D24 D6 D7 AE6
CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L
IN IN IN IN IN OUT
14 59 70 14 70 14 70 13 14 70 14 70 59
R1023
54.9
1% 1/16W MF-LF 402
R1021
54.9
1% 1/16W MF-LF 402
70 13 10
XDP_TDO
C1014
NO STUFF
0.1uF
10% 16V X5R 402 2
TP_CPU_TEST6 TP_CPU_TEST7
PLACEMENT_NOTE=Place R1092 near ITP connector (if present)
R1010
0
1
70 9 70 9 70 9
OUT CPU_BSEL<0> OUT CPU_BSEL<1> OUT CPU_BSEL<2>
NO STUFF
5% 1/16W MF-LF 402
NO STUFF
1
R1022
27.4
1% 1/16W MF-LF 402
R1020
27.4
1% 1/16W MF-LF 402
R1093
54.9
70 13 10
R1011
1K
2
R1012
1K
5% 1/16W MF-LF 402
XDP_TCK
PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU. PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU. PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU. PLACEMENT_NOTE (all 4 resistors): Place within 12.7mm of CPU
2
1 1%
R1094
649
70 13 10
1/16W MF-LF 402 2
5% 1/16W MF-LF 402
XDP_TRST_L
1 1% 1/16W MF-LF 402
A
SYNC FROM T18
SYNC_MASTER=K24_MLB
PAGE TITLE
CPU FSB
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
CHANGE CPU FROM SOCKET TO BGA SYMBOL
C.0.0
BRANCH PAGE

10 OF 109
SHEET
A4
P6 P21
(CPU CORE POWER) =PPVCORE_S0_CPU

8 11 12
A8
OMIT
A11 A14 P24
U1000
R2
44 A (SV Design Target) 41 A (SV HFM)
A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11
PENRYN
FCBGA
R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4
4 OF 4
A7 A9 A10 A12
AB20
30.4 A (SV LFM) 23 A (LV Design Target)
OMIT
AB7 AC7 AC9
U1000
PENRYN
FCBGA
A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9
AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18
3 OF 4
VCC
AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14
D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9
VCC
AF15 AF17 AF18
(CPU IO POWER 1.05V)

AF20 E14
VSS
VSS
AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25
=PP1V05_S0_CPU
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21
8 10 12 13
E16 E19
4500 mA (before VCC stable)

E21
2500 mA (after VCC stable)

E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23
VCCP
(CPU INTERNAL PLL POWER 1.5V)

W21 G26
(BR1#)
B26
=PP1V5_S0_CPU 130 mA
C26
8 12
H3 H6 H21 H24
AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCCA VID0 VID1 VID2 VID3 VID4 VID5 VID6
AD6 AF5 AE5 AF4 AE3 AF3 AE2
CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>
OUT OUT OUT OUT OUT OUT OUT
59 70 59 70 59 70
J2 J5 J22
=PPVCORE_S0_CPU
59 70 59 70 59 70 59 70
1
8 11 12
J25 K1
R1100
100
1% 1/16W MF-LF 402
K4 K23 K26 L3
VCCSENSE
AF7
CPU_VCCSENSE_P
OUT
59 70
L6 L21
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs. PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.
L24 M2 M5
VSSSENSE
AE7
CPU_VCCSENSE_N
OUT
1
59 70
R1101
100
1% 1/16W MF-LF 402
M22 M25 N1 N4 N23 N26 P3 B1
(Socket-P KEY)
AF25
A
SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL
SYNC_MASTER=K24_MLB
PAGE TITLE
CPU Power & Ground

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

11 OF 109
SHEET
Current numbers from Merom for Santa Rosa EMTS, doc #20905.
CPU VCore HF and Bulk Decoupling

4X 330UF. 20X 22UF 0805
PLACEMENT_NOTE (C1200-C1219):
11 8 =PPVCORE_S0_CPU
Place inside socket cavity on secondary side.
D
1 2
CRITICAL
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
C1200
22UF
20% 6.3V CERM-X5R 805
C1201
22UF
20% 6.3V CERM-X5R 805
C1202
22UF
20% 6.3V CERM-X5R 805
C1203
22UF
20% 6.3V CERM-X5R 805
C1204
22UF
20% 6.3V CERM-X5R 805
C1205
22UF
20% 6.3V CERM-X5R 805
C1206
22UF
20% 6.3V CERM-X5R 805
C1207
22UF
20% 6.3V CERM-X5R 805
C1208
22UF
20% 6.3V CERM-X5R 805
C1209
22UF
20% 6.3V CERM-X5R 805
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
CRITICAL
1
C1210
22UF
20% 6.3V CERM-X5R 805
C1211
22UF
20% 6.3V CERM-X5R 805
C1212
22UF
20% 6.3V CERM-X5R 805
C1213
22UF
20% 6.3V CERM-X5R 805
C1214
22UF
20% 6.3V CERM-X5R 805
C1215
22UF
20% 6.3V CERM-X5R 805
C1216
22UF
20% 6.3V CERM-X5R 805
C1217
22UF
20% 6.3V CERM-X5R 805
C1218
22UF
20% 6.3V CERM-X5R 805
C1219
22UF
20% 6.3V CERM-X5R 805
C
PLACEMENT_NOTE (C1240-C1243): Place on secondary side. CRITICAL
1
C
Place on secondary side. CRITICAL
1
NOSTUFF
CRITICAL
1
CRITICAL
1
C1240
470UF-4MOHM
20% 2.0V POLY-TANT D2T-SM 3
C1241
470UF-4MOHM
C1242
470UF-4MOHM
C1243
470UF-4MOHM
20% 2.0V POLY-TANT D2T-SM
Place on secondary side.
Place on secondary side.
VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF
11 8 =PP1V5_S0_CPU
PLACEMENT_NOTE=Place C1281 near CPU pin B26.
C1250
10uF
20% 6.3V X5R 603
C1251
0.01UF
10% 16V CERM 402
B
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
13 11 10 8 =PP1V05_S0_CPU
1 CRITICAL 330UF 2
C1260
20% 2.5V TANT CASE-B2-SM
C1261
0.1UF
20% 10V CERM 402
C1262
0.1UF
20% 10V CERM 402
C1263
0.1UF
20% 10V CERM 402
C1264
0.1UF
20% 10V CERM 402
C1265
0.1UF
20% 10V CERM 402
C1266
0.1UF
20% 10V CERM 402
SYNC_MASTER=K24_MLB
PAGE TITLE
CPU Decoupling
DRAWING NUMBER SIZE
SYNC FROM T18 REMOVE NO STUFF CAPS C1220 TO C1231 REMOVE C1244 & C1245 CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

12 OF 109
SHEET
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
USE WITH 920-0782 ADAPTER FLEX TO SUPPORT CPU, MCP DEBUGGING.
MCP79-specific pinout
=PP3V3_S0_XDP =PP1V05_S0_CPU
8 12 11 10 8
XDP
R1315
54.9
1% 1/16W MF-LF 402
OMIT CRITICAL
J1300
DF40C-60DS-0.4V
F-ST-SM
2
1
70 10 70 10
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7
70 XDP_CPURST_L
1
BI BI
XDP_BPM_L<5> XDP_BPM_L<4>
OBSFN_A0 OBSFN_A1
3 5 7
OBSFN_C0 OBSFN_C1
JTAG_MCP_TDO JTAG_MCP_TRST_L
IN OUT
21 21
70 10 70 10
BI IN
OBSDATA_A0 OBSDATA_A1
9 11 13
OBSDATA_C0 OBSDATA_C1
MCP_DEBUG<0> MCP_DEBUG<1>
BI BI
19 73 19 73
70 10 70 10
IN IN
OBSDATA_A2 OBSDATA_A3
15 17 19
OBSDATA_C2 OBSDATA_C3
BI BI
19 73 19 73
TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1
OBSFN_B0 OBSFN_B1
21 23 25
OBSFN_D0 OBSFN_D1
JTAG_MCP_TDI JTAG_MCP_TMS
OUT OUT
21 21
TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1
OBSDATA_B0 OBSDATA_B1
27 29 31
OBSDATA_D0 OBSDATA_D1
BI BI
19 73 19 73
TP_XDP_OBSDATA_B2 XDP TP_XDP_OBSDATA_B3
OBSDATA_B2 OBSDATA_B3
33 35 37
OBSDATA_D2 OBSDATA_D3
BI BI
19 73 19 73
R1399
1K
70 14 10
IN
CPU_PWRGD
1 5% 1/16W MF-LF 402
XDP_PWRGD XDP_OBS20
PWRGD/HOOK0 HOOK1 VCC_OBS_AB
39 41 43 45 47 49
FSB_CLK_ITP_P FSB_CLK_ITP_N
IN IN
14 70
XDP
14 70
R1303
1K
2 5% 1/16W MF-LF 402
19 21
IN OUT
PM_LATRIGGER_L JTAG_MCP_TCK
HOOK2 HOOK3
FSB_CPURST_L
IN
10 14 70
XDP_DBRESET_L
OUT
10 25
PLACEMENT_NOTE=Place close to CPU to minimize stub.
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. TDO TRSTn TDI TMS XDP_PRESENT# XDP XDP_TDO XDP_TRST_L XDP_TDI XDP_TMS
73 39 21 73 39 21
BI BI
SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK
SDA SCL TCK1
51 53
IN OUT OUT OUT
10 70 10 70 10 70 10 70
NC
55 57 59
70 10
OUT
XDP_TCK
TCK0
XDP
C1300
0.1uF
10% 16V X5R 402
C1301
0.1uF
10% 16V
X5R 402
(998-2515) 518S0774
Direction of XDP module

Please avoid any obstructions ON ODD-NUMBERED SIDE OF J1300
SYNC_MASTER=K24_MLB
PAGE TITLE
eXtended Debug Port(MiniXDP)

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

13 OF 109
SHEET
5
OMIT
4
U1400
MCP79-TOPO-B
BGA (1 OF 11)
70 10 70 10 70 10
BI BI BI BI BI BI BI BI BI BI BI BI
FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_DINV_L<0> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_DINV_L<1> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> FSB_DINV_L<2> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> FSB_DINV_L<3>
T40 U40 V41
CPU_DSTBP0# CPU_DSTBN0# CPU_DBI0# CPU_DSTBP1# CPU_DSTBN1# CPU_DBI1# CPU_DSTBP2# CPU_DSTBN2# CPU_DBI2# CPU_DSTBP3# CPU_DSTBN3# CPU_DBI3# CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32# CPU_A33# CPU_A34# CPU_A35# CPU_ADSTB0# CPU_ADSTB1# CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4# CPU_ADS# CPU_BNR# CPU_BR0# CPU_BR1# CPU_DBSY# CPU_DRDY# CPU_HIT# CPU_HITM# CPU_LOCK# CPU_TRDY# CPU_PECI CPU_PROCHOT# CPU_THERMTRIP# CPU_FERR# CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_RS0# CPU_RS1# CPU_RS2#
70 10 70 10 70 10
W39 W37 V35
70 10 70 10 70 10
N37 L36 N35
70 10 70 10 70 10
M39 M41 J41
70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<0> FSB_ADSTB_L<1>
AC34 AE38 AE34 AC37 AE37 AE35 AB35 AF35 AG35 AG39 AE33 AG37 AG38 AG34 AN38 AL39 AG33 AL33 AJ33 AN36 AJ35 AJ37 AJ36 AJ38 AL37 AL34 AN37 AJ34 AL38 AL35 AN34 AR39 AN35
70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10
70 10 70 10
AE36 AK35
70 10
BI BI BI BI BI
FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>
AC38 AA33 AC39 AC33 AC35
23 22 14 8
=PP1V05_S0_MCP_FSB
70 10 70 10 70 10
1 1 1
70 10
R1410
54.9
1% 1/16W MF-LF 402
R1415
62
5% 1/16W MF-LF 402
R1416
62
5% 1/16W MF-LF 402
70 10 70 10 70 10
BI BI BI
FSB_ADS_L FSB_BNR_L FSB_BREQ0_L

70 FSB_BREQ1_L
AD42 AD43 AE40 AL32 AD39 AD41 AB42 AD40 AC43 AE41
70 37 10 70 10
IN IN
PM_THRMTRIP_L CPU_FERR_L
70 10 70 10 70 10 70 10 70 10 70 10
BI BI BI BI IN OUT
FSB_DBSY_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_TRDY_L
CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63# CPU_BPRI# CPU_DEFER#
Y43 W42 Y40 W41 Y39 V42 Y41 Y42 P42 U41 R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34 AA36 AA34 AA38 AA35 U38 U36 U35 U33 U34 W38 R33 U37 N34 N33 R34 R35 P35 R39 R37 R38 L37 L39 L38 N36 N38 J39 J38 J37 L42 M42 P41 N41 N40 M40 H40 K42 H41 L41 H43 H42 K41 J40 H39 M43
FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70 10 70
FSB
AA41 AA40
FSB_BPRI_L FSB_DEFER_L
OUT OUT
10 70 10 70
NO STUFF
NO STUFF
1
NO STUFF
1 1
OUT OUT
CPU_PECI_MCP CPU_PROCHOT_L
E41 AJ41 AG43 AH40
R1420
1K
5% 1/16W MF-LF 402
R1421
1K
5% 1/16W MF-LF 402
R1422
1K
5% 1/16W MF-LF 402
70 37 10
BCLK_OUT_CPU_P BCLK_OUT_CPU_N BCLK_OUT_ITP_P BCLK_OUT_ITP_N BCLK_OUT_NB_P BCLK_OUT_NB_N
G42 G41
FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N

70 FSB_CLK_MCP_P 70 FSB_CLK_MCP_N
OUT OUT OUT OUT
10 70 10 70
AL43 AL42
13 70 13 70
9 9 9
IN IN IN
=MCP_BSEL<2> =MCP_BSEL<1> =MCP_BSEL<0>
(MCP_BSEL<2>) (MCP_BSEL<1>) (MCP_BSEL<0>)
F42 D42 F41
AL41 AK42
Loop-back clock for delay matching.

70 10 70 10 70 10
1 1
OUT OUT OUT

23
FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> PP1V05_S0_MCP_PLL_FSB 206 mA 20 mA 29 mA 15 mA
AC41 AB41 AC42
BCLK_IN_N BCLK_IN_P
AK41 AJ40
R1430
49.9
1% 1/16W MF-LF 402
R1435
49.9
1% 1/16W MF-LF 402
270 mA (A01)
AG27 AH27 AG28 AH28
+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU BCLK_VML_COMP_VDD BCLK_VML_COMP_GND CPU_COMP_VCC CPU_COMP_GND
A
R1431
49.9
1% 1/16W MF-LF 402 1 1
CPU_A20M# CPU_IGNNE# CPU_INIT# CPU_INTR CPU_NMI CPU_SMI# CPU_PWRGD CPU_RESET# CPU_SLP# CPU_DPSLP# CPU_DPWR# CPU_STPCLK# CPU_DPRSTP#
AF41 AH39 AH42 AF42 AG41 AH41
CPU_A20M_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_SMI_L CPU_PWRGD FSB_CPURST_L FSB_CPUSLP_L CPU_DPSLP_L FSB_DPWR_L CPU_STPCLK_L CPU_DPRSTP_L
OUT OUT OUT OUT OUT OUT
10 70 10 70 10 70 10 70 10 70 10 70
2 1
=PP1V05_S0_MCP_FSB NO STUFF
8 14 22 23
R1440
150
5% 1/16W MF-LF 402
70 MCP_BCLK_VML_COMP_VDD 70 MCP_BCLK_VML_COMP_GND
AM39 AM40
AH43 H38
SYNC_MASTER=K24_MLB
OUT OUT OUT OUT OUT OUT OUT
10 13 70 10 13 70
PAGE TITLE
MCP CPU Interface

DRAWING NUMBER SIZE
70 MCP_CPU_COMP_VCC 70 MCP_CPU_COMP_GND
AM43 AM42
AM33 AN33 AM32 AG42 AN32
10 70 10 70 10 70
R
R1436
49.9
1% 1/16W MF-LF 402
Apple Inc.
051-7982
REVISION
10 70 10 59 70
C.0.0
BRANCH PAGE
14 OF 109
SHEET
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
7
OMIT
3
OMIT
U1400
MCP79-TOPO-B
BGA (2 OF 11)
U1400
MCP79-TOPO-B
BGA (3 OF 11) AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39
71 27 71 27 71 27 71 27
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT
MEM_A_DQ<63> MEM_A_DQ<62> MEM_A_DQ<61> MEM_A_DQ<60> MEM_A_DQ<59> MEM_A_DQ<58> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<48> MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<41> MEM_A_DQ<40> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<31> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<1> MEM_A_DQ<0> MEM_A_DM<7> MEM_A_DM<6> MEM_A_DM<5> MEM_A_DM<4> MEM_A_DM<3> MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>
AL8 AL9 AP9 AN9 AL6 AL7 AN6 AN7 AR6 AR7 AV6 AW5 AN10 AR5 AU6 AV5 AU7 AU8 AW9 AP11 AW6 AY5 AU9 AV9 AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25 AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31 AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31 AT37 AU37 AW39 AV39 AR37 AR38 AV38 AW38 AR35 AP35
71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27
71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27
71 27 71 27 71 27 71 27 71 27 71 27 71 27
MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0 MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0
MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N
MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<0> MEM_A_DQS_N<0>
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27 71
71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT
MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<31> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<16> MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9> MEM_B_DQ<8> MEM_B_DQ<7> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<4> MEM_B_DQ<3> MEM_B_DQ<2> MEM_B_DQ<1> MEM_B_DQ<0> MEM_B_DM<7> MEM_B_DM<6> MEM_B_DM<5> MEM_B_DM<4> MEM_B_DM<3> MEM_B_DM<2> MEM_B_DM<1> MEM_B_DM<0>
AT4 AT3 AV2 AV3 AR4 AR3 AU2 AU3 AY4 AY3 BB3 BC3 AW4 AW3 BA3 BB2 BB5 BA5 BA8 BC8 BB4 BC4 BA7 AY8 BA9 BB10 BB12 AW12 BB8 BB9 AY12 BA12 BC32 AW32 BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40 BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40 AW42 AW41 AT40 AT41 AP41 AN40 AU40 AU41 AR41 AP42
MEMORY PARTITION 0
71 28 71 28 71 28
MRAS0# MCAS0# MWE0#
MEMORY PARTITION 1
71 28
AV17 AP17 AR17
MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L
OUT OUT OUT
27 71 27 71 27 71
71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28
MBA0_2 MBA0_1 MBA0_0
AP23 AP19 AW17
MEM_A_BA<2> MEM_A_BA<1> MEM_A_BA<0>
OUT OUT OUT
27 71 27 71 27 71
71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28
MA0_14 MA0_13 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0
AR23 AU15 AN23 AW21 AN19 AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19 AT19 AR19
MEM_A_A<14> MEM_A_A<13> MEM_A_A<12> MEM_A_A<11> MEM_A_A<10> MEM_A_A<9> MEM_A_A<8> MEM_A_A<7> MEM_A_A<6> MEM_A_A<5> MEM_A_A<4> MEM_A_A<3> MEM_A_A<2> MEM_A_A<1> MEM_A_A<0>
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 27 71 71 28 71 28
MEMORY CONTROL 0A
MCLK0A_2_P MCLK0A_2_N MCLK0A_1_P MCLK0A_1_N MCLK0A_0_P MCLK0A_0_N MCS0A_1# MCS0A_0# MODT0A_1 MODT0A_0 MCKE0A_1 MCKE0A_0
AW33 AV33
71 28 71 28 71 28 71 28
TP_MEM_A_CLK2P
71 28
TP_MEM_A_CLK2N
71 28
BA24 AY24
MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_CLK_P<0> MEM_A_CLK_N<0>
OUT OUT OUT OUT
27 71 27 71
71 28 71 28 71 28
BB20 BC20
27 71 71 28 27 71 71 28
MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0 MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0
MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N
AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43
MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0>
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71
MRAS1# MCAS1# MWE1#
AW16 BA15 BA16
MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L
OUT OUT OUT
28 71 28 71 28 71
MBA1_2 MBA1_1 MBA1_0
BB29 BB18 BB17
MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0>
OUT OUT OUT
28 71 28 71 28 71
MA1_14 MA1_13 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0
BA29 BA14 AW28 BC28 BA17 BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25 BB25 BA18
MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71 28 71
MEMORY CONTROL 1A
MCLK1A_2_P MCLK1A_2_N MCLK1A_1_P MCLK1A_1_N MCLK1A_0_P MCLK1A_0_N MCS1A_1# MCS1A_0# MODT1A_1 MODT1A_0 MCKE1A_1 MCKE1A_0
BA42 BB42
TP_MEM_B_CLK2P TP_MEM_B_CLK2N MEM_B_CLK_P<1> MEM_B_CLK_N<1> MEM_B_CLK_P<0> MEM_B_CLK_N<0>

28 71 28 71
B
OUT OUT OUT OUT
28 71 28 71
BB22 BA22
BA19 AY19
71 27 71 27 71 27 71 27 71 27 71 27 71 27 71 27
AN5 AU5 AR10 AN13 AN27 AW29 AV35 AR34
AT15 AR18
MEM_A_CS_L<1> MEM_A_CS_L<0>
OUT OUT
27 71 27 71
71 28 71 28 71 28
AT5 BA2 AY7 BA11 BB34 BB38 AY43 AR42
BB14 BB16
MEM_B_CS_L<1> MEM_B_CS_L<0>
OUT OUT
28 71 28 71
AP15 AV15
MEM_A_ODT<1> MEM_A_ODT<0>
OUT OUT
27 71 27 71
71 28 71 28 71 28
BB13 AY15
MEM_B_ODT<1> MEM_B_ODT<0>
OUT OUT
28 71 28 71
AU23 AT23
MEM_A_CKE<1> MEM_A_CKE<0>
OUT OUT
27 71 27 71
71 28 71 28
AY31 BB30
MEM_B_CKE<1> MEM_B_CKE<0>
OUT OUT
28 71 28 71
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP Memory Interface

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

15 OF 109
SHEET
OMIT
U1400
MCP79-TOPO-B
BGA (4 OF 11)
TP_MEM_A_CLK5P
AU33 AU34
MEMORY CONTROL 0B
MEMORY CONTROL 1B
TP_MEM_A_CLK5N TP_MEM_A_CLK4P TP_MEM_A_CLK4N TP_MEM_A_CLK3P TP_MEM_A_CLK3N
MCLK0B_2_P MCLK0B_2_N MCLK0B_1_P MCLK0B_1_N MCLK0B_0_P MCLK0B_0_N MCS0B_0# MCS0B_1# MODT0B_0 MODT0B_1 MCKE0B_0 MCKE0B_1
MCLK1B_2_P MCLK1B_2_N MCLK1B_1_P MCLK1B_1_N MCLK1B_0_P MCLK1B_0_N MCS1B_0# MCS1B_1# MODT1B_0 MODT1B_1 MCKE1B_0 MCKE1B_1
BA41 BB41
TP_MEM_B_CLK5P TP_MEM_B_CLK5N TP_MEM_B_CLK4P TP_MEM_B_CLK4N TP_MEM_B_CLK3P TP_MEM_B_CLK3N
BB24 BC24
AY23 BA23
BA21 BB21
BA20 AY20
TP_MEM_A_CS_L<2> TP_MEM_A_CS_L<3>
AU17 AR15
BC16 BA13
TP_MEM_B_CS_L<2> TP_MEM_B_CS_L<3>
TP_MEM_A_ODT<2> TP_MEM_A_ODT<3>
AN17 AN15
AY16 BC13
TP_MEM_B_ODT<2> TP_MEM_B_ODT<3>
TP_MEM_A_CKE<2> TP_MEM_A_CKE<3>
AV23 AN25
BA30 BA31
TP_MEM_B_CKE<2> TP_MEM_B_CKE<3>
23 23 16 8
PP1V05_S0_MCP_PLL_CORE 17 mA 12 mA 19 mA 39 mA
T27 U28 U27 T28
=PP1V8R1V5_S0_MCP_MEM 87 mA (A01)
R1610
40.2
1% 1/16W MF-LF 402
+V_PLL_XREF_XS +V_PLL_DP +V_PLL_CORE +V_VPLL
MRESET0#
AY32
MCP_MEM_RESET_L TP or NC for DDR2.
OUT
29
71 MCP_MEM_COMP_VDD 71 MCP_MEM_COMP_GND
1
AN41 AM41
MEM_COMP_VDD MEM_COMP_GND +VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8 +VDD_MEM9 +VDD_MEM10 +VDD_MEM11 +VDD_MEM12 +VDD_MEM13 +VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20 +VDD_MEM21 +VDD_MEM22 +VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26 +VDD_MEM27 +VDD_MEM28 +VDD_MEM29 +VDD_MEM30 +VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34 +VDD_MEM35 +VDD_MEM36 +VDD_MEM37 +VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41 +VDD_MEM42 +VDD_MEM43 +VDD_MEM44 +VDD_MEM45 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64
AM17 AM19 AM21 AM23 AM25 AM27 AM29 AN16 BC29 AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29 AV24 AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AY26 AW19 AW24 BC25 AL30 AM31
=PP1V8R1V5_S0_MCP_MEM 4771 mA (A01, DDR3)
8 16 23
R1611
40.2
1% 1/16W MF-LF 402
AA22 AP12
2
G30 P10 T10 T6 V10 V34 W5 AA39 AB22 AB7 AD22 AE20 AF24 AG24 AH35 AK7 AM28 AT25 AP30 AR36 AU10 F28 BC21 AY9
BC9 D34 F24 G32 H31 K7 M38 M5 M6 M7 M9 N39 N8 P33 P34 P37 P4 P40 P7 R36 R40 R43 R5 T18 T20 AK11
T24 T26
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54
T33 T34 T35 T37 T38 T7 T9 U18 U20
SYNC_MASTER=K24_MLB
U22
PAGE TITLE
MCP Memory Misc

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

16 OF 109
SHEET
5
OMIT
4
U1400
MCP79-TOPO-B
BGA (5 OF 11)
9 9 9 9 9 9 9
IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
=PEG_D2R_P<0> =PEG_D2R_N<0> =PEG_D2R_P<1> =PEG_D2R_N<1> =PEG_D2R_P<2> =PEG_D2R_N<2> =PEG_D2R_P<3> =PEG_D2R_N<3> =PEG_D2R_P<4> =PEG_D2R_N<4> =PEG_D2R_P<5> =PEG_D2R_N<5> =PEG_D2R_P<6> =PEG_D2R_N<6> =PEG_D2R_P<7> =PEG_D2R_N<7> =PEG_D2R_P<8> =PEG_D2R_N<8> =PEG_D2R_P<9> =PEG_D2R_N<9> =PEG_D2R_P<10> =PEG_D2R_N<10> =PEG_D2R_P<11> =PEG_D2R_N<11> =PEG_D2R_P<12> =PEG_D2R_N<12> =PEG_D2R_P<13> =PEG_D2R_N<13> =PEG_D2R_P<14> =PEG_D2R_N<14> =PEG_D2R_P<15> =PEG_D2R_N<15>
F7 E7 D7 C7 E6 F6 E5 F5 E4 E3 C3 D3 G5 H5 J7 J6 J5 J4 L11 L10 L9 L8 L7 L6 N11 N10 N9 P9 N7 N6 N5 N4
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
PCI EXPRESS
PE0_RX0_P PE0_RX0_N PE0_RX1_P PE0_RX1_N PE0_RX2_P PE0_RX2_N PE0_RX3_P PE0_RX3_N PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE0_RX6_P PE0_RX6_N PE0_RX7_P PE0_RX7_N PE0_RX8_P PE0_RX8_N PE0_RX9_P PE0_RX9_N PE0_RX10_P PE0_RX10_N PE0_RX11_P PE0_RX11_N PE0_RX12_P PE0_RX12_N PE0_RX13_P PE0_RX13_N PE0_RX14_P PE0_RX14_N PE0_RX15_P PE0_RX15_N
PE0_TX0_P PE0_TX0_N PE0_TX1_P PE0_TX1_N PE0_TX2_P PE0_TX2_N PE0_TX3_P PE0_TX3_N PE0_TX4_P PE0_TX4_N PE0_TX5_P PE0_TX5_N PE0_TX6_P PE0_TX6_N PE0_TX7_P PE0_TX7_N PE0_TX8_P PE0_TX8_N PE0_TX9_P PE0_TX9_N PE0_TX10_P PE0_TX10_N PE0_TX11_P PE0_TX11_N PE0_TX12_P PE0_TX12_N PE0_TX13_P PE0_TX13_N PE0_TX14_P PE0_TX14_N PE0_TX15_P PE0_TX15_N PE0_REFCLK_P PE0_REFCLK_N PE1_REFCLK_P PE1_REFCLK_N PE2_REFCLK_P PE2_REFCLK_N PE3_REFCLK_P PE3_REFCLK_N PE4_REFCLK_P PE4_REFCLK_N PE5_REFCLK_P PE5_REFCLK_N PE6_REFCLK_P PE6_REFCLK_N PEX_RST0# PE1_TX0_P PE1_TX0_N PE1_TX1_P PE1_TX1_N PE1_TX2_P PE1_TX2_N PE1_TX3_P PE1_TX3_N
C5 D4 C4 B4 A4 A3 B3 B2 C1 D1 D2 E1 E2 F2 F3 F4 G3 H4 H3 H2 H1 J1 J2 J3 K2 K3 L4 L3 M4 M3 M2 M1
=PEG_R2D_C_P<0> =PEG_R2D_C_N<0> =PEG_R2D_C_P<1> =PEG_R2D_C_N<1> =PEG_R2D_C_P<2> =PEG_R2D_C_N<2> =PEG_R2D_C_P<3> =PEG_R2D_C_N<3> =PEG_R2D_C_P<4> =PEG_R2D_C_N<4> =PEG_R2D_C_P<5> =PEG_R2D_C_N<5> =PEG_R2D_C_P<6> =PEG_R2D_C_N<6> =PEG_R2D_C_P<7> =PEG_R2D_C_N<7> =PEG_R2D_C_P<8> =PEG_R2D_C_N<8> =PEG_R2D_C_P<9> =PEG_R2D_C_N<9> =PEG_R2D_C_P<10> =PEG_R2D_C_N<10> =PEG_R2D_C_P<11> =PEG_R2D_C_N<11> =PEG_R2D_C_P<12> =PEG_R2D_C_N<12> =PEG_R2D_C_P<13> =PEG_R2D_C_N<13> =PEG_R2D_C_P<14> =PEG_R2D_C_N<14> =PEG_R2D_C_P<15> =PEG_R2D_C_N<15>
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
E11 D11
PEG_CLK100M_P PEG_CLK100M_N
IN
PEG_PRSNT_L
C9
PE0_PRSNT_16#
PEB_CLKREQ#/GPIO_49
Int PU
Int PU
OUT OUT
9 9
30 30
IN IN
MINI_CLKREQ_L PCIE_MINI_PRSNT_L
D5 D9
G11 F11
PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N
OUT OUT
30 72 30 72
PEB_PRSNT#
Int PU
Int PU
9 9
IN IN
FW_CLKREQ_L PCIE_FW_PRSNT_L
E8 C10
PEC_CLKREQ#/GPIO_50
J11 J10
PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N
OUT OUT
9 9
PEC_PRSNT#
Int PU
Int PU
9 9
IN IN
EXCARD_CLKREQ_L PCIE_EXCARD_PRSNT_L
M15 B10
PED_CLKREQ#/GPIO_51
G13 F13
PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N
OUT OUT
9 9
PED_PRSNT#
Int PU
Int PU
TP_PE4_CLKREQ_L TP_PE4_PRSNT_L
L16 L18
PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46
Int PU
J13 H13
TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N
54 9
AUD_IP_PERIPHERAL_DET GMUX_JTAG_TCK_L
M16 M18
OUT
PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47
Int PU Int PU
Int PU
L14 K14
9 9
OUT IN
CARDREADER_RESET GMUX_JTAG_TDO
M17 M19
PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48
Int PU
N14 M14
30 7
IN
PCIE_WAKE_L
F17
PE_WAKE# Int PE1_RX0_P PE1_RX0_N PE1_RX1_P PE1_RX1_N PE1_RX2_P PE1_RX2_N PE1_RX3_P PE1_RX3_N
PU (S5)
K11
PCIE_RESET_L
OUT
25
72 30 72 30
IN IN IN IN IN IN
PCIE_MINI_D2R_P PCIE_MINI_D2R_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN
K9 J9
D8 C8
PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN
30 72 30 72
72 9
H9 G9
B8 A8
9 72 9 72
72 9
9 9
F9 E9
A7 B7
9 9
H7 G7
B6 C6
=PP1V05_S0_MCP_PEX_DVDD0 57 mA (A01, DVDD0 & 1)

T17 W19 U17 V19 W16 W17 W18 U16
+DVDD0_PEX1 +DVDD0_PEX2 +DVDD0_PEX3 +DVDD0_PEX4 +DVDD0_PEX5 +DVDD0_PEX6 +DVDD0_PEX7 +DVDD0_PEX8 +DVDD1_PEX1 +DVDD1_PEX2
=PP1V05_S0_MCP_PEX_DVDD1
T19 U19
+AVDD0_PEX1 +AVDD0_PEX2 +AVDD0_PEX3 +AVDD0_PEX4 +AVDD0_PEX5 +AVDD0_PEX6 +AVDD0_PEX7 +AVDD0_PEX8 +AVDD0_PEX9 +AVDD0_PEX10 +AVDD0_PEX11 +AVDD0_PEX12 +AVDD0_PEX13 +AVDD1_PEX1 +AVDD1_PEX2 +AVDD1_PEX3
Y12 AA12 AB12 M12 P12 R12 N12 T12 U12 AC12 AD12 V12 W12
206 mA (A01, AVDD0 & 1)
23
PP1V05_S0_MCP_PLL_PEX 84 mA (A01)
T16
+V_PLL_PEX
M13 N13 P13
72 MCP_PEX_CLK_COMP
A11
PEX_CLK_COMP
NO STUFF
1
R1710
2.37K
1% 1/16W MF-LF
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX. If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP PCIe Interfaces

DRAWING NUMBER SIZE
402
PLACEMENT_NOTE=Place within 12.7mm of U1400
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

17 OF 109
SHEET
OMIT
U1400
MCP79-TOPO-B
BGA (6 OF 11)
=PP3V3_ENET_MCP_RMGT
8 18 23
+3.3V_DUAL_RMGT1
J24 K24
83 mA (A01)
D
74 31 74 31 74 31 74 31
LAN
+3.3V_DUAL_RMGT2
8 23
D
Network Interface Select
23
+V_DUAL_RMGT1 +V_DUAL_RMGT2 MII_VREF RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3

RGMII_TXC/MII_TXCLK RGMII_TXCTL/MII_TXEN
U23 V23
131 mA (A01)
IN IN IN IN IN IN IN IN IN
ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3> ENET_CLK125M_RXCLK ENET_RX_CTRL =MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS TP_ENET_INTR_L
C23 B23 E24 A24
RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3

RGMII_RXC/MII_RXCLK RGMII_RXCTL/MII_RXDV
E28
MCP_MII_VREF ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3> ENET_CLK125M_TXCLK ENET_TX_CTRL ENET_MDC ENET_MDIO TP_ENET_PWRDWN_L
IN OUT OUT OUT OUT OUT OUT OUT BI
B24 C24 C25 D25
Interface
31 74 31 74 31 74 31 74
ENET_TXD<0> 1 0
RGMII MII
74 31 74 31
A23 C22
9 9 23 18 8
F23 B26 B22
9
1
MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK

RGMII_INTR/GPIO_35
D24 C26
31 74 31 74
NOTE: All Apple products set strap to MII, RGMII products will enable
R1810
49.9
1% 1/16W MF-LF 402 2
J22
RGMII_MDC RGMII_MDIO
RGMII_PWRDWN/GPIO_37
D21 C21
31 74
feature via software.

31 74
This
avoids a leakage issue since MCP79 requires a S5 pull-up.
23
PP1V05_ENET_MCP_PLL_MAC 5 mA (A01)
T23
G23
+V_DUAL_MACPLL BUF_25MHZ
E23
MCP_CLK25M_BUF0_R
OUT
32 74
=PP3V3_S0_MCP_GPIO
8 19 21
74 MCP_MII_COMP_VDD 74 MCP_MII_COMP_GND
C27 B27
MII_COMP_VDD MII_COMP_GND
MII_RESET#
J23
ENET_RESET_L PP3V3_S0_MCP_DAC
OUT
24
31 74
R1860
100K
5% 1/16W MF-LF 402
R1861
100K
5% 1/16W MF-LF
R1811
49.9
1% 1/16W MF-LF 402
TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF
2
C39 B38
RGB_DAC_RSET RGB_DAC_VREF
+V_RGB_DAC +V_TV_DAC DDC_CLK0 DDC_DATA0 RGB_DAC_RED RGB_DAC_GREEN RGB_DAC_BLUE RGB_DAC_HSYNC RGB_DAC_VSYNC TV_DAC_RED TV_DAC_GREEN TV_DAC_BLUE
J32 K32
103 mA 103 mA
206 mA (A01)
402
B31 A31
MCP_DDC_CLK0 MCP_DDC_DATA0 RGB DAC Disable: Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.
DACS
C
9 9
B39 A39 B40
TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE TP_MCP_RGB_HSYNC TP_MCP_RGB_VSYNC
OUT OUT
MCP_TV_DAC_RSET MCP_TV_DAC_VREF
E36 A35
RGB ONLY
TV_DAC_RSET TV_DAC_VREF
A40 A41
TV
20 8
/ Component / Pr / Y
A36 B36 C36
=PP3V3_S5_MCP_GPIO
9 9
CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC
TV DAC Disable:
OUT OUT OUT OUT OUT
9 9 9
R1820
47K
5% 1/16W MF-LF 402
IN OUT
MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT
C38 D38
XTALIN_TV XTALOUT_TV
Okay to float all TV_DAC signals. Okay to float XTALIN_TV and XTALOUT_TV. DDC_CLK0/DDC_DATA0 pull-ups still required.
Comp / Pb
TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45
2
D36 C37
9 9
38
BI
66
LPCPLUS_GPIO
E16 B15
IN
DP_IG_CA_DET (See below)
GPIO_6/FERR*/IGPU_GPIO_6 GPIO_7/NFERR*/IGPU_GPIO_7
IFPA_TXC_P IFPA_TXC_N IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N
B35 C35
LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<2> LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3>
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
65 72 65 72
B32 A32 D32 C32 D33 C33 B34 C34
69 68
OUT OUT OUT
LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR
G39 E37 F40
Interface Mode MCP Signal =MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N<0> =MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2> =MCP_HDMI_DDC_CLK TMDS/HDMI TMDS_IG_TXC_P/N TMDS_IG_TXD_P/N<0> TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2> TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA TMDS_IG_HPD TP_DP_IG_AUX_CHP/N DisplayPort DP_IG_ML_P/N<3> DP_IG_ML_P/N<2> DP_IG_ML_P/N<1>
69 65
FLAT PANEL
LCD_BKL_CTL/GPIO_57 LCD_BKL_ON/GPIO_59 LCD_PANEL_PWR/GPIO_58 HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N DP_AUX_CH0_P DP_AUX_CH0_N HPLUG_DET2/GPIO_22 HPLUG_DET3
7 65 72 7 65 72 7 65 72 7 65 72 7 65 72 7 65 72 9 9
66 66
OUT OUT OUT OUT OUT OUT OUT OUT
=MCP_HDMI_TXC_P =MCP_HDMI_TXC_N =MCP_HDMI_TXD_P<0> =MCP_HDMI_TXD_N<0> =MCP_HDMI_TXD_P<1> =MCP_HDMI_TXD_N<1> =MCP_HDMI_TXD_P<2> =MCP_HDMI_TXD_N<2>
D35 E35
66
G35 F35 F33 G33 J33 H33
DP_IG_ML_P/N<0>
66
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
DP_IG_DDC_CLK
66
=MCP_HDMI_DDC_DATA =MCP_HDMI_HPD DP_IG_AUX_CH_P/N
DP_IG_DDC_DATA
66
DP_IG_HPD
66
IFPB_TXC_P IFPB_TXC_N IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N
L31 K31
LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0> LVDS_IG_B_DATA_P<1> LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_P<2> LVDS_IG_B_DATA_N<2> LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3>
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
9 9
DP_IG_AUX_CH_P/N
66
J29 H29 L29 K29 L30 K30 N30 M30
9 9 9 9 9 9 9 9
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. NOTE: 20K pull-down required on DP_HPD_DET. NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used. NOTE: HDMI port requires level-shifting. IFP interface can
9 72 66 72 66
OUT OUT
DP_IG_AUX_CH_P DP_IG_AUX_CH_N (See below)
D43 C43
be used to provide HDMI or dual-channel TMDS without

66
IN IN
24 8
=DVI_HPD_GMUX_INT =MCP_HDMI_HPD =PP3V3R1V8_S0_MCP_IFP_VDD 190 mA (A01, 1.8V)
C31 F31
level-shifters. LVDS: Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V

24
M27 M26
PP3V3_S0_MCP_VPLL 16 mA (A01) 8 mA 8 mA
M28 M29
+VDD_IFPA +VDD_IFPB +V_PLL_IFPAB +V_PLL_HDMI +VDD_HDMI HDMI_RSET HDMI_VPROBE
DDC_CLK2/GPIO_23 DDC_DATA2/GPIO_24 DDC_CLK3 DDC_DATA3 IFPAB_RSET IFPAB_VPROBE
C30 B30
LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA
OUT BI
7 65 7 65
D31 E31
=MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA
OUT BI
66 66
24 8
=PP1V05_S0_MCP_HDMI_VDD 95 mA (A01)
T25
72 24 72 24
OUT OUT
MCP_HDMI_RSET MCP_HDMI_VPROBE
J31 J30
E32 G31
MCP_IFPAB_RSET MCP_IFPAB_VPROBE
OUT OUT
24 72 24 72
R1850
10K
GPIOs 57-59 (if LCD panel is used): In MCP79 these pins have undocumented internal
5% 1/16W MF-LF 2 402
pull-ups (~10K to 3.3V S0).
To ensure pins are low
by default, pull-downs (1K or stronger) must be used.
SYNC_MASTER=K24_MLB
PAGE TITLE
=DVI_HPD_GMUX_INT: Alias to DVI_HPD for systems using IFP for DVI. Alias to GMUX_INT for systems with GMUX.
MCP Ethernet & Graphics

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.
C.0.0
BRANCH PAGE

18 OF 109
SHEET
6
OMIT
1
=PP3V3_S0_MCP_GPIO
U1400
MCP79-TOPO-B
BGA (7 OF 11)
21 18 8
19
R3 U10 R4 U11 P3
MCP_RS232_SOUT_L
R1989 R1990 R1991 R1992 R1994
8.2K
2 5% 1/16W MF-LF 402
73 19 73 19 19 54 19
PCI_REQ0_L PCI_REQ1_L FW_PWR_EN AUD_IPHS_SWITCH_EN MCP_RS232_SIN_L
T2 V9 T3 U9 T4
OUT OUT IN
PCI_REQ0# PCI_REQ1#/FANRPM2 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ# PCI_TRDY# PCI_CLKRUN#/GPIO_42 LPC_DRQ1#/GPIO_19 LPC_DRQ0# Int PU LPC_SERIRQ Int PU
Int PU
PCI_GNT0# PCI_GNT1#/FANCTL2 PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS# PCI_GNT4#/GPIO_53/RS232_SOUT# PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_PAR PCI_PERR#/GPIO_43/RS232_DCD# PCI_SERR# PCI_STOP#
TP_PCI_GNT0_L TP_PCI_GNT1_L GMUX_JTAG_TMS GMUX_JTAG_TDI MCP_RS232_SOUT_L

73 19 73 19
PCI_REQ0_L PCI_REQ1_L FW_PWR_EN MCP_RS232_SIN_L
8.2K 8.2K 8.2K 8.2K
1 1 1 1
2 5% 2 5% 2 5% 2 5% 1/16W MF-LF 402 1/16W MF-LF 402 1/16W MF-LF 402 1/16W MF-LF 402
OUT OUT OUT
9 19 9 19 19
73 13 73 13 73 13 73 13 73 13 73 13 73 13 73 13
BI BI BI BI BI BI BI BI
MCP_DEBUG<0> MCP_DEBUG<1> MCP_DEBUG<2> MCP_DEBUG<3> MCP_DEBUG<4> MCP_DEBUG<5> MCP_DEBUG<6> MCP_DEBUG<7> TP_PCI_AD<8> TP_PCI_AD<9> TP_PCI_AD<10> TP_PCI_AD<11> TP_PCI_AD<12> TP_PCI_AD<13> TP_PCI_AD<14> TP_PCI_AD<15> TP_PCI_AD<16> TP_PCI_AD<17> TP_PCI_AD<18> TP_PCI_AD<19> TP_PCI_AD<20> TP_PCI_AD<21> TP_PCI_AD<22> TP_PCI_AD<23> TP_PCI_AD<24> TP_PCI_AD<25>
AC3 AE10 AC4 AE11 AB3 AC6 AB2 AC7 AC8 AA2 AC9 AC10 AC11 AA1 AA5 Y5 W3 W6 W4 W7 V3 W8 V2 W9 U3 W11 U2 U5 U1 U6 T5 U7
AA3 AA6 AA11 W10
TP_PCI_C_BE_L<0> TP_PCI_C_BE_L<1> TP_PCI_C_BE_L<2> TP_PCI_C_BE_L<3>
AA9 Y4 AA10 Y1 AB9 AA7 Y2
TP_PCI_DEVSEL_L TP_PCI_FRAME_L TP_PCI_IRDY_L TP_PCI_PAR TP_PCI_PERR_L TP_PCI_SERR_L TP_PCI_STOP_L PM_LATRIGGER_L

13
PCI
PCI_PME#/GPIO_30
Int PU (S5)
T1
OUT
PCI_RESET0# PCI_RESET1#
R10 R11
MEM_VTT_EN_R TP_PCI_RESET1_L
OUT
25
PCI_CLK0 PCI_CLK1 PCI_CLK2
R6 R7 R8
TP_PCI_CLK0 TP_PCI_CLK1
73 PCI_CLK33M_MCP_R
R1910
22
5% 1/16W MF-LF 402
TP_PCI_AD<26> TP_PCI_AD<27> TP_PCI_AD<28> TP_PCI_AD<29> TP_PCI_AD<30> TP_PCI_AD<31>
PLACEMENT_NOTE=Place close to pin R8
PCI_CLKIN
R9
73 PCI_CLK33M_MCP
TP_PCI_INTW_L TP_PCI_INTX_L TP_PCI_INTY_L TP_PCI_INTZ_L
P2 N3 N2 N1
LPC_FRAME# LPC_PWRDWN#/GPIO_54/EXT_NMI#
AD4 AE12
LPC_FRAME_R_L LPC_PWRDWN_L LPC_RESET_L
R1960
22
2 5% 1/16W MF-LF 402
LPC_FRAME_L
OUT OUT OUT
36 38 73 36 38
TP_PCI_TRDY_L
Y3
LPC
LPC_RESET0# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_CLK0
AE5
25 73
AD3 AD2 AD1 AD5
LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>
38 36
IN
PM_CLKRUN_L
AD11
R1950 R1951 R1952 R1953
22 22 22 22
1 1 1 1
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>
BI BI BI BI
36 38 73 36 38 73 36 38 73 36 38 73
IN
FW_PME_L TP_LPC_DRQ0_L
AE2 AE1 AE6
38 36
BI
LPC_SERIRQ
AE9
LPC_CLK33M_SMC_R
OUT
25 73
U24 U26 U39 U4 U8
V16 V17 V18 V20 V22 V24 V26 V27 V28 V33 V37 V4 V40 V7 W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22
Y24 Y25
GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 GND81 GND82 GND83 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97
GND98 GND99 GND100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND111 GND112 GND113 GND114 GND115 GND116 GND117 GND118 GND119 GND120 GND121 GND122 GND123 GND124 GND125 GND126 GND127 GND128 GND129 GND130
Y26 Y27 AB18 H34 AB20 AB21 AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4 AB40 AC22 AC36 AC40 AB33 AC5 AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27 AD28 AD33 AD34
2
R1961
10K
5% 1/16W MF-LF 402
Strap for Boot ROM Selection (See HDA_SDOUT)
GND
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP PCI & LPC

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

19 OF 109
SHEET
5
OMIT
4
U1400
MCP79-TOPO-B
BGA (8 OF 11)
External A
72 34 72 34
OUT OUT
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N
AJ7 AJ6
SATA_A0_TX_P SATA_A0_TX_N SATA_A0_RX_N SATA_A0_RX_P
USB0_P USB0_N USB1_P USB1_N USB2_P USB2_N
C29 D29
USB_EXTA_P USB_EXTA_N AirPort (PCIe Mini-Card)
BI BI
35 73 35 73
72 34 72 34
IN IN
SATA_HDD_D2R_N SATA_HDD_D2R_P
AJ5 AJ4
C28 D28
USB_MINI_P USB_MINI_N External D
BI BI
9 9
D
72 34 72 34
A28 B28
USB_EXTD_P USB_EXTD_N Camera
BI BI
9 9
OUT OUT
SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N
AJ11 AJ10
SATA_A1_TX_P SATA_A1_TX_N SATA_A1_RX_N SATA_A1_RX_P
USB3_P USB3_N USB4_P USB4_N USB5_P USB5_N USB6_P USB6_N
F29 G29
USB_CAMERA_P USB_CAMERA_N IR
BI BI
65 73 65 73
72 34 72 34
IN IN
SATA_ODD_D2R_N SATA_ODD_D2R_P
AJ9 AK9
K27 L27
USB_IR_P USB_IR_N Geyser Trackpad/Keyboard
BI BI
9 73 9 73
J26 J27
USB_TPAD_P USB_TPAD_N Bluetooth
BI BI
44 73 44 73
TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN
AK2 AJ3
SATA_B0_TX_P SATA_B0_TX_N SATA_B0_RX_N SATA_B0_RX_P
F27 G27
USB_BT_P USB_BT_N External B
BI BI
30 73 30 73
TP_SATA_C_D2RN TP_SATA_C_D2RP
AJ2 AJ1
SATA USB
USB7_P USB7_N USB8_P USB8_N USB9_P USB9_N USB10_P USB10_N
D27 E27
USB_EXTB_P USB_EXTB_N ExpressCard
BI BI
35 73 35 73
TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN
AM4 AL3
SATA_B1_TX_P SATA_B1_TX_N SATA_B1_RX_N SATA_B1_RX_P
K25 L25
USB_EXCARD_P USB_EXCARD_N External C
BI BI
9 9
=PP3V3_S5_MCP_GPIO
8 18
TP_SATA_D_D2RN TP_SATA_D_D2RP
AL4 AK3
H25 J25
USB_EXTC_P USB_EXTC_N
BI BI
9 9
R2051
8.2K
5% 1/16W MF-LF 402
R2053
8.2K
5% 1/16W MF-LF 402
F25 G25
TP_USB_10P
2
TP_USB_10N
1 1
TP_SATA_E_R2D_CP TP_SATA_E_R2D_CN
AN1 AM1
SATA_C0_TX_P SATA_C0_TX_N SATA_C0_RX_N SATA_C0_RX_P
USB11_P USB11_N
K23 L23
USB_CARDREADER_P USB_CARDREADER_N
BI BI
9 73 9 73
R2050
8.2K
5% 1/16W MF-LF 402
R2052
8.2K
5% 1/16W MF-LF
C
USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L EXCARD_OC_L
TP_SATA_E_D2RN TP_SATA_E_D2RP
AM2 AM3
402
TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN
AP3 AP2
SATA_C1_TX_P SATA_C1_TX_N SATA_C1_RX_N SATA_C1_RX_P
USB_OC0#/GPIO_25 USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO
L21 K21 J21 H21
IN IN IN IN
35 35
37
TP_SATA_F_D2RN TP_SATA_F_D2RP
AN3 AN2
+V_PLL_USB
L28
PP3V3_S0_MCP_PLL_USB 19 mA (A01)
23
USB_RBIAS_GND
A27
73 MCP_USB_RBIAS_GND
R2060
TP_MCP_SATALED_L
E12
SATA_LED#
23
PP1V05_S0_MCP_PLL_SATA 84 mA (A01)
AE16
+V_PLL_SATA
=PP1V05_S0_MCP_SATA_DVDD0 43 mA (A01, DVDD0 & 1)

AF19 AG16 AG17 AG19
+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4 +DVDD1_SATA1 +DVDD1_SATA2
=PP1V05_S0_MCP_SATA_DVDD1
AH17 AH19
B
8
=PP1V05_S0_MCP_SATA_AVDD0 127 mA (A01, AVDD0 & 1)

AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13
+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9 +AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4 SATA_TERMP
=PP1V05_S0_MCP_SATA_AVDD1
AN14 AL14 AM13 AM14
72 MCP_SATA_TERMP
AE3
GND131 GND132 GND133 GND134 GND135 GND136 GND137 GND138 GND139 GND140 GND141 GND142 GND143 GND144 GND145 GND146 GND147 GND148 GND149 GND150 GND151 GND152 GND153 GND154 GND155 GND156 GND157 GND158 GND159 GND160
AD35 AD37 AD38 AE22 AE24 AE39 AE4 AD6 AF16 AF17 AF18 AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24
806
1% 1/16W MF-LF 402 2
R2010
2.49K
1% 1/16W MF-LF 402
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA. If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP SATA & USB

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

20 OF 109
SHEET
OMIT
U1400
MCP79-TOPO-B
BGA (9 OF 11)
=PP3V3R1V5_S0_MCP_HDA
8 21 23
7 mA (A01)
+V_DUAL_HDA1 +V_DUAL_HDA2
J16 K16
R2160
8.2K
5% 1/16W MF-LF 402
D
73 49
HDA
R2170
22
1 5% 1/16W MF-LF 402 2 5% 1/16W MF-LF 402 2
D
HDA_SDOUT
IN
HDA_SDIN0
G15
HDA_SDATA_IN0
Int PD
HDA_SDATA_OUT
F15
73 21 HDA_SDOUT_R
OUT
49 73
BIOS Boot Select

HDA_BIT_CLK
R2171
22
TP_MLB_RAM_SIZE
J14
HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK
Int PD
HDA_BITCLK
E15
73 21 HDA_BIT_CLK_R
OUT
49 73
I/F LPC
HDA_SDOUT 0 0 1 1
LPC_FRAME# 0 1 0 1
R2172
22
1 5% 1/16W 2
TP_MLB_RAM_VENDOR
23 21 8
J15
=PP3V3R1V5_S0_MCP_HDA (MXM_OK for MXM systems)

1
HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA
Int PD
HDA_RESET*
K15
73 21 HDA_RST_R_L
HDA_RST_L
OUT
49 73
PCI SPI0
R2110
49.9
1% 1/16W MF-LF 2 402
R2173
22
MF-LF 402 2
HDA_SYNC
L15
73 21 HDA_SYNC_R
1 5% 1/16W MF-LF 402
HDA_SYNC
OUT
49 73
SPI1
73 MCP_HDA_PULLDN_COMP
A15
HDA_PULLDN_COMP
HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA SLP_S3* SLP_RMGT* SLP_S5*
K17 L17
MCP_GPIO_4 AUD_I2C_INT_L
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

9 21
IN
21 54
R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls
23
PP1V05_S0_MCP_PLL_NV 37 mA (A01) 20 mA 17 mA
AE18 AE17
+V_PLL_NV_H +V_PLL_SP_SPREF
G17 J17 H17
PM_SLP_S3_L PM_SLP_RMGT_L PM_SLP_S4_L
OUT OUT OUT
7 32 36 63 67 9
LPC_FRAME# high for SPI1 ROM override. NOTE: MCP79 does not support FWH, only
7 36 37 63
LPC ROMs.
So Apple designs will
25 22 7
PP3V3_G3_RTC
38 37 36 32
1 1
OUT IN
=SPI_CS1_R_L_USE_MLB SMC_ADAPTER_EN
L24 L26
GPIO_1/PWRDN_OK/SPI_CS1
GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L
Int PU A20GATE KBRDRSTIN* Int PU SIO_PME* Int PU (S5) EXT_SMI/GPIO_32* Int
not use LPC for BootROM override.
THERM_DIODE_P THERM_DIODE_N
B11 C11
MCP_THMDIODE_P MCP_THMDIODE_N
OUT OUT
42 76
NOTE: MCP79 rev A01 does not support

42 76
=PP3V3_S0_MCP BOOT_MODE_SAFE
8 22 23
SPI1 option.
Rev B01 will.
R2120
R2121
49.9K
1% 1/16W MF-LF 402
TP_SB_A20GATE TP_MCP_KBDRSTIN_L
36 36
K13 L13 C19 C18
49.9K
1% 1/16W MF-LF 402
IN IN
SMC_WAKE_SCI_L SMC_RUNTIME_SCI_L
PU (S5)
MCP_VID0/GPIO_13 MCP_VID1/GPIO_14 MCP_VID2/GPIO_15
L20 M20 M21
MCP_VID<0> MCP_VID<1> MCP_VID<2>
OUT OUT OUT
21 60 21 60 21 60
R2180
10K
5% 1/16W MF-LF
C
BUF_SIO_CLK Frequency
Frequency HDA_SYNC 24 MHz 14.31818 MHz 1 0
402
SM_INTRUDER_L
B20
INTRUDER* LID* LLB*

Int PU (S5) Int PU (S5)
SPKR
C13
MCP_SPKR
OUT
1
37
TP_MCP_LID_L
36
BOOT_MODE_USER
M25 M24
IN
PM_BATLOW_L
MISC
70 59
IN
PM_DPRSLPVR
M22
CPU_DPRSLPVR PWRBTN* RSTBTN* RTC_RST* PWRGD_SB PS_PWRGD CPU_VLD JTAG_TDI Int JTAG_TDO JTAG_TMS Int JTAG_TRST* JTAG_TCK XTALIN XTALOUT XTALIN_RTC XTALOUT_RTC
PU Int PU (S5) Int PU
36 25
IN IN
PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L
C16 D16
SMB_CLK0 SMB_DATA0 SMB_CLK1/MSMB_CLK SMB_DATA1/MSMB_DATA SMB_ALERT*/GPIO_64
L19 K19 G21 F21 M23
SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN
OUT BI OUT BI OUT
13 39 73 13 39 73 39 73 39 73 21 30 32
2
R2181
10K
5% 1/16W MF-LF 402
USER mode: Normal SAFE mode: For ROMSIP recovery
SPI Frequency Select

Connects to SMC for automatic recovery.
RTC_RST_L
(MGPIO2)
C20
36 25
IN IN
PM_RSMRST_L MCP_PS_PWRGD
(MGPIO3)
D20 E20
FANRPM0/GPIO_60 FANCTL0/GPIO_61 FANRPM1/GPIO_63 FANCTL1/GPIO_62
B12 A12 D12 C12
MEM_EVENT_L ODD_PWR_EN_L SMC_IG_THROTTLE_L ARB_DETECT

21
Frequency 31 MHz
SPI_DO 0 0 1 1
SPI_CLK 0 1 0 1
IN OUT IN
21 27 28 36 34 21 37
42 MHz
25
25
IN
MCP_CPU_VLD
C17
CPUVDD_EN
D17
MCP_CPUVDD_EN
OUT
25 MHz 1 MHz
13 13 13 13 13
IN OUT IN IN IN
JTAG_MCP_TDI JTAG_MCP_TDO JTAG_MCP_TMS JTAG_MCP_TRST_L JTAG_MCP_TCK
E19 F19 J19 J18 G19
PU
SPI_CS0/GPIO_10 SPI_CLK/GPIO_11 SPI_DI/GPIO_8 SPI_DO/GPIO_9
C14 D13 C15 B14
SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R
OUT OUT IN OUT
38 73 38 48 73
NOTE: Straps not provided on this page.

38 48 73 38 48 73
25 25
IN OUT
MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT
A16 B16
SUS_CLK/GPIO_34 BUF_SIO_CLK TEST_MODE_EN PKG_TEST
B18 AE7
PM_CLK32K_SUSCLK_R TP_MCP_BUF_SIO_CLK
B
OUT
25 73
25 25
IN OUT
RTC_CLK32K_XTALIN RTC_CLK32K_XTALOUT
A19 B19
K22 L22
1
MCP_TEST_MODE_EN
R2163
10K
5% 1/16W MF-LF 402
R2190
1K
1% 1/16W MF-LF 402
R2150
10K
5% 1/16W MF-LF 402
R2151
100K
5% 1/16W MF-LF 402 2
=PP3V3_S0_MCP_GPIO
8 18 19
=PP3V3_S3_MCP_GPIO
HDA Output Caps

1
For EMI Reduction on HDA interface
R2140
10K
5% 1/16W MF-LF
R2141
10K
5% 1/16W MF-LF 402
R2142
10K
5% 1/16W MF-LF 402
R2143
10K
5% 1/16W MF-LF 402
R2154
100K
5% 1/16W MF-LF 402
HDA_SDOUT_R HDA_BIT_CLK_R HDA_RST_R_L HDA_SYNC_R
21 73 21 73
402
MCP_GPIO_4
21 73 21 73
9 21 21 54 21 27 28 36 21 37
AP_PWR_EN
21 30 32
AUD_I2C_INT_L MEM_EVENT_L SMC_IG_THROTTLE_L
MCP_VID<0> MCP_VID<1>
21 60 21 60 21 60
C2170
10PF
5% 50V CERM 402
C2172
10PF
5% 50V CERM 402
ARB_DETECT
2 1
21
MCP_VID<2>
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP HDA & MISC

R2157
22K
5% 1/16W MF-LF
R2147
100K
1
R2155
22K
5% 1/16W MF-LF 2 402 2
R2156
22K
5% 1/16W MF-LF 402 2
DRAWING NUMBER
SIZE
C2171
10PF
5% 50V CERM 402
5%
C2173
10PF
5% 50V CERM 402 2
1/16W MF-LF 402
Apple Inc.
R
051-7982
REVISION
402
C.0.0
BRANCH PAGE

21 OF 109
SHEET
8
OMIT
7
U1400
MCP79-TOPO-B
BGA (11 OF 11) AH26 AH33 AH34 AH37 AH38 AJ39
5
OMIT
4
U1400
MCP79-TOPO-B
BGA
23 8
=PPVCORE_S0_MCP
AA25 AC23 U25 AH12 AG10 AG5 Y21 Y23 AA16 AA26 AA27 AA28 AC16 AC17 AC18 AC19 AC20 AC21 AA17 AC24 AC25 AC26 AC27 AC28 AD21 AD23 W27 V25 AA18 AE19 AE21 AE23 AE25 AE26 AE27 AE28 AF10 AF11 AA19 AF2 AF21 AF23 AF25 AF3 AF4 AF7 AH23 AF9 AA20 AG11 AG12 AG21 AG23 AG25 AG3 AG4 AA21 AG6 AG7 AG8 AG9 AH1 AH10 AH11 W26 AH2 AA23 W28 AH25 AH21 AH3 AH4 AH5 AH6 AH7 AH9 AA24 W21 W23 W25 AF12
(10 OF 11)
=PP1V05_S0_MCP_FSB
8 14 23
AJ8 AK10 AK33 AK34 AK37 AK4 AK40 AL36 AL40 AL5 AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38 AM5 AM6 AM7 AM9
AP26 AN28 AN30 AN39 AN4 Y7 AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37 AP4 AP40 AP7 AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29
AT33 AT6 AT7 AT9 AY21 AY22 L12 AU12 AU28 AP33 AU32 AR30 AU36 AU38 AU4 G28 F20 AV28 AV32 AV36 AV4 AV7 AW11 G20 AR43 AW43
AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41
GND161 GND162 GND163 GND164 GND165 GND166 GND167 GND168 GND169 GND170 GND171 GND172 GND173 GND174 GND175 GND176 GND177 GND178 GND179 GND180 GND181 GND182 GND183 GND184 GND185 GND186 GND187 GND188 GND189 GND190 GND191 GND192 GND193 GND194 GND195 GND196 GND197 GND198 GND199 GND200 GND201 GND202 GND203 GND204 GND205 GND206 GND207 GND208 GND209 GND210 GND211 GND212 GND213 GND214 GND215 GND216 GND217 GND218 GND219 GND220 GND221 GND222 GND223 GND224 GND225 GND226 GND227 GND228 GND229 GND230 GND231 GND232 GND233 GND234 GND235 GND236 GND237 GND238 GND239 GND240 GND241 GND242 GND243 GND244 GND245 GND246 GND247 GND248 GND249 GND250 GND251 GND252
GND253 GND254 GND255 GND256 GND257 GND258 GND259 GND260 GND261 GND262 GND263 GND264 GND265 GND266 GND267 GND268 GND269 GND270 GND271 GND272 GND273 GND274 GND275 GND276 GND277 GND278 GND279 GND280 GND281 GND282 GND283 GND284 GND285 GND286 GND287 GND288 GND289 GND290 GND291 GND292 GND293 GND294 GND295 GND296 GND297 GND298 GND299 GND300 GND301 GND302 GND303 GND304 GND305 GND306 GND307 GND308 GND309 GND310 GND311 GND312 GND313 GND314 GND315 GND316 GND317 GND318 GND319 GND320 GND321 GND322 GND323 GND324 GND325 GND326 GND327 GND328 GND329 GND330 GND331 GND332 GND333 GND334 GND335 GND336 GND337 GND338 GND339 GND340 GND341 GND342 GND343
AV40 BA1 BA4 AW31 AY6 L35 BC33 BC37 BC41 AY14 BC5 C2 D10 D14 D15 D18 D19 D22 D23 D26 D30 D37 D6 E13 E17 E21 E25 E29 E33 F12 F16 F32 F8 G10 G12 G14 G16 BC12 G22 G24 AW20 G34 G4 G43 G6 G8 H11 H15 AW35 H23 AN8 G40 J12 J8 K10 K12 K18 K26 K37 K4 K40 K8 AU1 L40 L43 L5 M10 M34 M35 M37 Y28 Y33 Y34 Y35 Y37 Y38 AB17 AB16 AN26 AD7 M11 AA4 AB19 AY13 P11 Y6 T11 V11 Y11 AH16 T22
23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6 +VDD_CORE7 +VDD_CORE8 +VDD_CORE9 +VDD_CORE10 +VDD_CORE11 +VDD_CORE12 +VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19 +VDD_CORE20 +VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30 +VDD_CORE31 +VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37 +VDD_CORE38 +VDD_CORE39 +VDD_CORE40 +VDD_CORE41 +VDD_CORE42 +VDD_CORE43 +VDD_CORE44 +VDD_CORE45 +VDD_CORE46 +VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54 +VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81
+VTT_CPU1 +VTT_CPU2 +VTT_CPU3 +VTT_CPU4 +VTT_CPU5 +VTT_CPU6 +VTT_CPU7 +VTT_CPU8 +VTT_CPU9 +VTT_CPU10 +VTT_CPU11 +VTT_CPU12 +VTT_CPU13 +VTT_CPU14 +VTT_CPU15 +VTT_CPU16 +VTT_CPU17 +VTT_CPU18 +VTT_CPU19 +VTT_CPU20 +VTT_CPU21 +VTT_CPU22 +VTT_CPU23 +VTT_CPU24 +VTT_CPU25 +VTT_CPU26 +VTT_CPU27 +VTT_CPU28 +VTT_CPU29 +VTT_CPU30 +VTT_CPU31 +VTT_CPU32 +VTT_CPU33 +VTT_CPU34 +VTT_CPU35 +VTT_CPU36 +VTT_CPU37 +VTT_CPU38 +VTT_CPU39 +VTT_CPU40 +VTT_CPU41 +VTT_CPU42 +VTT_CPU43 +VTT_CPU44 +VTT_CPU45 +VTT_CPU46 +VTT_CPU47 +VTT_CPU48 +VTT_CPU49 +VTT_CPU50 +VTT_CPU51 +VTT_CPU52 +VTT_CPUCLK
R32 AC32 E40 J36 N32 T32 U32 V32 W32 P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32 B41 B42 C40 C41 C42 D39 D40 D41 E38 E39 F37 F38 F39 G36 G37 G38 H35 H37 J34 J35 K33 K34 K35 L32 L33 L34 M31 M32 M33 N31 P32 Y32 AA32
1139 mA
1182 mA (A01)
POWER
GND
AG32
43 mA
=PP3V3_S0_MCP
8 21 23
+3.3V_1 +3.3V_2 +3.3V_3 +3.3V_4 +3.3V_5 +3.3V_6 +3.3V_7 +3.3V_8
AD10 AE8 AB10 AD9 Y10 AB11 AA8 Y9
450 mA (A01)
=PP3V3_S5_MCP
8 23
+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4 +3.3V_DUAL_USB1 +3.3V_DUAL_USB2 +3.3V_DUAL_USB3 +3.3V_DUAL_USB4
G18 H19 J20 K20
16 mA
266 mA (A01)
G26 H27 J28 K28
250 mA
=PP1V05_S5_MCP_VDD_AUXC
8 23
25 21 7
PP3V3_G3_RTC 10 uA (G3)
A20
+VBAT
+VDD_AUXC1 +VDD_AUXC2 +VDD_AUXC3
T21 U21 V21
105 mA (A01)
80 uA (S0)
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP Power & Ground

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

22 OF 109
SHEET
8
MCP Core Power
22 8
7
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
=PPVCORE_S0_MCP 23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
C2500
(No IG vs. EG data) 4.7UF
20% 4V X5R-1 402
C2501
4.7UF
20% 4V X5R-1 402
C2502
4.7UF
20% 4V X5R-1 402
C2503
4.7UF
20% 4V X5R-1 402
C2504
1UF
10% 10V X5R 402-1
C2505
1UF
10% 10V X5R 402-1
C2506
1UF
10% 10V X5R 402-1
C2507
1UF
10% 10V X5R 402-1
C2508
0.1UF
20% 10V CERM 402
C2509
0.1UF
20% 10V CERM 402
C2510
0.1UF
20% 10V CERM 402
C2511
0.1UF
20% 10V CERM 402
C2512
0.1UF
20% 10V CERM 402
C2513
0.1UF
20% 10V CERM 402
D
8
MCP PCIE (DVDD) Power =PP1V05_S0_MCP_PEX_DVDD 57 mA (A01)

8
MCP SATA (DVDD) Power =PP1V05_S0_MCP_SATA_DVDD 43 mA (A01)

8
L2570
=PP1V05_S0_MCP_AVDD_UF 333 mA (A01)
1 0603
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) Apple: 5x 2.2uF 0402 (11 uF)
2
D
PP1V05_S0_MCP_PEX_AVDD
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
30-OHM-5A
206 mA (A01)
C2515
4.7UF
20% 4V X5R-1 402
C2516
1UF
10% 10V X5R 402-1
C2517
1UF
10% 10V X5R 402-1
C2518
0.1uF
20% 10V CERM 402
C2519
0.1uF
20% 10V CERM 402
C2520
4.7UF
20% 4V X5R-1 402
C2521
0.1uF
20% 10V CERM 402
C2570
2.2UF
20% 6.3V CERM 402-LF
C2571
2.2UF
20% 6.3V CERM 402-LF
C2572
2.2UF
20% 6.3V CERM 402-LF
C2573
2.2UF
20% 6.3V CERM 402-LF
C2574
2.2UF
20% 6.3V CERM 402-LF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) MCP 1.05V AUX Power
22 8
MCP 1.05V RMGT Power

18 8
L2575
30-OHM-5A
1 0603 2
Apple: 2x 2.2uF 0402 (4.4 uF) PP1V05_S0_MCP_SATA_AVDD

=PP1V05_S5_MCP_VDD_AUXC 105 mA (A01)
=PP1V05_ENET_MCP_RMGT 131 mA (A01)
127 mA (A01)
C2525
0.1uF
20% 10V CERM 402
C2526
0.1uF
20% 10V CERM 402
C2528
4.7UF
20% 4V X5R-1 402
C2529
0.1uF
20% 10V CERM 402
C2575
2.2UF
20% 6.3V CERM 402-LF
C2576
2.2UF
20% 6.3V CERM 402-LF
MCP FSB (VTT) Power

22 14 8
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 7x 2.2uF 0402 (15.4 uF)
62 8
L2580
=PP1V05_S0_MCP_PLL_UF 562 mA (A01)
1 0402
=PP1V05_S0_MCP_FSB 1182 mA (A01)
30-OHM-1.7A
2
PP1V05_S0_MCP_PLL_FSB
14
270 mA (A01)
C2530
2.2UF
20% 6.3V CERM 402-LF
C2531
2.2UF
20% 6.3V CERM 402-LF
C2532
2.2UF
20% 6.3V CERM 402-LF
C2533
2.2UF
20% 6.3V CERM 402-LF
C2534
2.2UF
20% 6.3V CERM 402-LF
C2535
2.2UF
20% 6.3V CERM 402-LF
C2536
2.2UF
20% 6.3V CERM 402-LF
C2592
10UF
20% 6.3V X5R 603
C2580
4.7UF
20% 4V X5R-1 402
C2581
0.1UF
20% 10V CERM 402
MCP Memory Power

16 8
L2582
30-OHM-1.7A
1 0402 2
=PP1V8R1V5_S0_MCP_MEM 4771 mA (A01, DDR3)
PP1V05_S0_MCP_PLL_PEX
17
84 mA (A01)
C2540
4.7UF
20% 4V X5R-1 402
C2541
0.1UF
20% 10V CERM 402
C2542
0.1UF
20% 10V CERM 402
C2543
0.1UF
20% 10V CERM 402
C2544
0.1UF
20% 10V CERM 402
C2545
0.1UF
20% 10V CERM 402
C2546
0.1UF
20% 10V CERM 402
C2547
0.1UF
20% 10V CERM 402
C2548
0.1UF
20% 10V CERM 402
C2549
0.1UF
20% 10V CERM 402
C2582
4.7UF
20% 4V X5R-1 402
C2583
0.1UF
20% 10V CERM 402
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) MCP 3.3V Power
22 21 8
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) Apple: 4x 2.2uF 0402 (8.8 uF)
8
L2555
=PP3V3_S0_MCP_PLL_UF 19 mA (A01)
1 0402
L2584
30-OHM-1.7A
20
1 0402 2
Apple: 1x 2.2uF 0402 (2.2 uF) PP3V3_S0_MCP_PLL_USB

2
=PP3V3_S0_MCP 450 mA (A01)
30-OHM-1.7A
PP1V05_S0_MCP_PLL_SATA
20
84 mA (A01)
19 mA (A01)
C2550
2.2UF
20% 6.3V CERM 402-LF
C2551
2.2UF
20% 6.3V CERM 402-LF
C2552
2.2UF
20% 6.3V CERM 402-LF
C2553
2.2UF
20% 6.3V CERM 402-LF
C2555
2.2UF
20% 6.3V CERM 402-LF
C2584
4.7UF
20% 4V X5R-1 402
C2585
0.1UF
20% 10V CERM 402
B
L2586
MCP 3.3V AUX/USB Power
22 8
B
30-OHM-1.7A
1 0402 2
23 18 8
MCP 3.3V Ethernet Power =PP3V3_ENET_MCP_RMGT 83 mA (A01)
PP1V05_S0_MCP_PLL_CORE
16
=PP3V3_S5_MCP 266 mA (A01)
87 mA (A01)
C2560
2.2UF
20% 6.3V CERM 402-LF
C2564
2.2UF
20% 6.3V CERM 402-LF
C2586
4.7UF
20% 4V X5R-1 402
C2587
0.1UF
20% 10V CERM 402
L2588
MCP 3.3V/1.5V HDA Power
21 8
1
30-OHM-1.7A
2 0402
PP1V05_S0_MCP_PLL_NV
21
=PP3V3R1V5_S0_MCP_HDA 7 mA (A01)
37 mA (A01)
C2562
2.2UF
20% 6.3V CERM 402-LF
C2588
4.7UF
C2589
0.1UF
20% 10V CERM 402
C2590
0.1UF
20% 10V CERM 402
MCP79 Ethernet VRef

23 18 8
20% 4V X5R-1 402
R2591
1.47K
A
L2595
8
1% 1/16W MF-LF 402
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP_MII_VREF
=PP1V05_ENET_MCP_PLL_MAC 5 mA (A01)
1
30-OHM-1.7A
2 0402
PP1V05_ENET_MCP_PLL_MAC
18
OUT
18
5 mA (A01)
MCP Standard Decoupling

DRAWING NUMBER SIZE
R2590 C2595
4.7UF
20% 4V X5R-1 402 2 2 1 1
1
1
C2596
0.1UF
20% 10V CERM 402
C2591
0.1UF
20% 10V
1.47K
1% 1/16W MF-LF 402
2
Apple Inc.
R
051-7982
REVISION
CERM 402
C.0.0
BRANCH PAGE

25 OF 109
SHEET
7
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) NO STUFF Apple: 1x 2.2uF 0402 (2.2 uF)
18 8
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF) PP3V3_S0_MCP_DAC
2
L2650
8
=PP3V3R1V8_S0_MCP_IFP_VDD 190 mA (A01, 1.8V)

1
=PP3V3_S0_MCP_DAC_UF 206 mA (A01)

1
30-OHM-1.7A
18
206 mA (A01)
C2610
2.2UF
20% 6.3V CERM 402-LF
0402
NO STUFF
1
C2650
2.2UF
20% 6.3V CERM 402-LF
R2651
0
5% 1/16W MF-LF 402
18 8
=PP1V05_S0_MCP_HDMI_VDD 95 mA (A01)
C2615
4.7UF
20% 4V X5R-1 402
C2616
0.1UF
20% 10V CERM 402
72 18 72 18
MCP_HDMI_RSET MCP_HDMI_VPROBE NO STUFF

1 1
72 18 72 18
MCP_IFPAB_RSET MCP_IFPAB_VPROBE NO STUFF

1 1
NO STUFF
R2620
1K
1% 1/16W
R2630
1K
1% 1/16W
C2620
0.1UF
20% 10V CERM 402
C2630
0.1UF
20% 10V CERM 402
MF-LF 402
MF-LF 402
WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640
8
Apple: ??? PP3V3_S0_MCP_VPLL

2
=PP3V3_S0_MCP_VPLL_UF 16 mA (A01)
1
30-OHM-1.7A
18
16 mA (A01)
0402
C2640
4.7UF
20% 6.3V CERM 603
C2641
0.1uF
20% 10V CERM 402
A
SYNC FROM T18 REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672 NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650) CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC REMOVE HDCP ROMS
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP Graphics Support

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

26 OF 109
SHEET
Platform Reset Connections

LPC Reset (Unbuffered)
R2820
0
8 =PP3V42_G3H_RTC_D
1 5% 1/16W MF-LF 402 2
PP3V3_G3_RTC
7 21 22
PLACEMENT_NOTE=Place close to U1400
R2881
33
1 5% 1/16W MF-LF 402 1 PLACEMENT_NOTE=Place close to U1400 5% 1/16W MF-LF 402 2
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
73 19
IN
LPC_RESET_L
DEBUG_RESET_L
OUT
38
C2819
10%
R2883
33
2
D
SMC_LRESET_L
1UF
6.3V CERM 402
OUT
36
PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79
PLACE C2819 CLOSE TO MCP79
PCIE Reset (Unbuffered)

R2892
0
17
IN
PCIE_RESET_L
1 5% 1/16W MF-LF 402 2 5% 1/16W MF-LF 402 1
BKLT_PLT_RST_L
OUT
69
R2891
0
1
MINI_RESET_L
OUT
30
RTC Crystal
21
C2810
12pF
1 2
R2871
0
2 5% 1/16W MF-LF 402
PCA9557D_RESET_L
OUT
26
IN
RTC_CLK32K_XTALOUT
R2810
0
5% 1/16W MF-LF 402
5% 50V CERM 402
C
NO STUFF
C
RTC_CLK32K_XTALOUT_R
R2811
10M
5% 1/16W MF-LF 402
CRITICAL
Y2810
32.768K
1
2
C2811
12pF
1 2
7X1.5X1.4-SM
21
OUT
RTC_CLK32K_XTALIN
MCP 25MHz Crystal

21
5% 50V CERM 402
C2815
12pF
R2870
33
19
IN
MCP_CLK25M_XTALOUT
IN
MEM_VTT_EN_R
1 5% 1/16W MF-LF 402
MEM_VTT_EN MAKE_BASE=TRUE
=DDRVTT_EN
OUT
58 64
R2815
0
NO STUFF
1
R2816
1M
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
5% 50V CERM 402
R2825
MCP_CLK25M_XTALOUT_R
73 19
IN
LPC_CLK33M_SMC_R
PLACEMENT_NOTE=Place close to U1400 1
33
2 5% 1/16W MF-LF 402 1
LPC_CLK33M_SMC
OUT
36 73
CRITICAL
R2826
33
2 5% 1/16W MF-LF 402
Y2815
25.0000M
SM-3.2X2.5MM 1 2
NC NC
LPC_CLK33M_LPCPLUS
OUT
38 73
C2816
12pF
1 2
21
OUT
MCP_CLK25M_XTALIN
B
8
MCP S0 PWRGD & CPU_VLD

=PP3V3_S5_MCPPWRGD MCPSEQ_SMC
1
5% 50V CERM 402
R2829
22
73 21
IN
PM_CLK32K_SUSCLK_R
1 5% 1/16W MF-LF 402
PM_CLK32K_SUSCLK
B
OUT
36 73
C2850
0.1UF
20% 10V CERM 402
Reset Button
36
IN
PM_SYSRST_L XDP
MCPSEQ_SMC
5 TC7SZ08AFEAPE 63 36
IN
ALL_SYS_PWRGD
SOT665
R2853
0
1 5% 1/16W MF-LF 402 2
R2898
0 MCP_PS_PWRGD
R2899
33
2
1 2 5% 1/16W MF-LF 402
10K pull-up to 3.3V S0 inside MCP PM_SYSRST_DEBOUNCE_L NO STUFF

1
U2850
59
S0_AND_IMVP_PGOOD
OUT
21
13 10
IN
XDP_DBRESET_L
1 5% 1/16W MF-LF 402
OUT
21
IN
VR_PWRGOOD_DELAY
B
3
R2890
0
5% 1/16W MF-LF 402
NO STUFF
C2899
1UF
10% 10V
MCPSEQ_MIX
SILK_PART=SYS RST
2
R2852
0
1 2
X5R 402
MCPSEQ_MIX
R2851
0
1 2
5% 1/16W MF-LF 402
MCP_CPU_VLD MCPSEQ_SMC
OUT
21
5% 1/16W MF-LF 402
R2850
0
1 2
21
IN
MCP_CPUVDD_EN
SYNC_MASTER=K24_MLB
5% 1/16W MF-LF 402
MCPSEQ_SMC represents MCP79 MLB power sequencing connections, but results in MCP79 ROMSIP sequence happening after CPU powers up. MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization. SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion). NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
SYNC FROM T18 CHANGE RESET BUTTOM TO RESET PADS REMOVE UNUSED PCIE RESET SIGNALS REMOVE R2824 AND NET PCI_CLK33M_SLOT_A CHANGE RTC COIN CELL TO LDO & SUPERCAP ALIAS MEM_VTT_EN TO =DDRVTT_EN CHANGE Y2810 AND U2850 TO SMALLER PARTS
PAGE TITLE
SB Misc
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

28 OF 109
SHEET
8
Page Notes
Power aliases required by this page: - =PP3V3_S3_VREFMRGN
7
MEM A VREF DQ DAC channel A 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV B 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV
6
MEM A VREF CA A 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV MEM B VREF DQ B 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV
5
MEM B VREF CA C 0x00 0x55 -0.91 mA 0.52 mA 0.70 V 0.091 V 1.044 V CPU FSB VREF
- =PP3V3_S5_VREFMRGN
Min DAC code

- =PPVTT_S3_DDR_BUF
Max DAC code

Signal aliases required by this page: - =I2C_VREFDACS_SCL - =I2C_VREFDACS_SDA - =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA
Max sink I Max source I Nominal Vref Min Vref Max Vref Vref Stepping (per DAC LSB)
SO-DIMM A and SO-DIMM B Vref settings should be margined separately (i.e. not simultaneously) due to current limitation of TPS51116 regulator.
=PPVTT_S3_DDR_BUF
58 8
11.2 mV
BOM options provided by this page: VREFMRGN NO_VREFMRGN
10mA max load
D
R2903
200
1 1% 1/16W MF-LF 402 2 VREFMRGN
PP0V75_S3_MEM_VREFDQ_A
27 VREFMRGN
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
VREFMRGN
1
B1 A2
U2902
MAX4253
UCSP A1 A4 VREFMRGN_DQ_SODIMMA_BUF 1
C2903
0.1UF
20% 10V CERM 402 A3
V+
VREFMRGN
R2904
100
2 1% 1/16W MF-LF 402
=PP3V3_S3_VREFMRGN
8
VB4
Place close to J3100.1
26 VREFMRGN_DQ_SODIMMA_EN
VREFMRGN
VREFMRGN
1
C2900
2.2UF
20% 6.3V CERM 402-LF
C2901
0.1UF
20% 10V CERM 402 B1 C2
R2901
100K
5% 1/16W MF-LF 402
R2905
200
1 VREFMRGN 1% 1/16W MF-LF 402 2
VREFMRGN
PP0V75_S3_MEM_VREFDQ_B
28 VREFMRGN
U2902
MAX4253
UCSP C1 C4
V+
R2906
100
VREFMRGN_DQ_SODIMMB_BUF 1 1% 1/16W MF-LF 402 2
VREFMRGN
8
VREFMRGN C3
U2900
VOUTA VOUTB VOUTC VOUTD
1 2 4 5
VREFMRGN_DQ_SODIMM
VDD
39
VB4
26 VREFMRGN_DQ_SODIMMB_EN
IN BI
=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA
6 SCL 7 SDA 9 A0
MSOP
DAC5574
39
VREFMRGN_CA_SODIMM
R2902
100K
5% 1/16W MF-LF 402
R2909
200
VREFMRGN 1 1% 1/16W MF-LF 402 2
VREFMRGN
VREFMRGN_CPUFSB
ADDR=0x98(WR)/0x99(RD)
10 A1
NC
VREFMRGN
B1 A2 1
PP0V75_S3_MEM_VREFCA_A
27 VREFMRGN
U2903
MAX4253
UCSP A1 A4 VREFMRGN_CA_SODIMMA_BUF 1
GND
3
C2904
0.1UF
20% 10V CERM 402 A3
V+
VREFMRGN
R2910
100
2 1% 1/16W MF-LF 402
VB4
26 VREFMRGN_CA_SODIMMA_EN
R2907
100K
5% 1/16W MF-LF 402
R2911
1 VREFMRGN 1% 1/16W MF-LF 402
VREFMRGN
200
PP0V75_S3_MEM_VREFCA_B
28 VREFMRGN
B1 C2
U2903
MAX4253
UCSP C1 C4
V+
VREFMRGN C3
R2912
100
VREFMRGN_CA_SODIMMB_BUF 1 1% 1/16W MF-LF 402 2
VB4
26 VREFMRGN_CA_SODIMMB_EN
R2908
100K
5% 1/16W MF-LF 402
2 VREFMRGN 1
VREFMRGN
1
B1 A2
U2904
MAX4253
UCSP A1 A4
C2905
0.1UF
20% 10V CERM 402 A3
V+
VREFMRGN
NC
VB4
B
B1
B
VREFMRGN
16 1 C2
U2904
MAX4253
UCSP C1 C4 VREFMRGN_CPUFSB_BUF
C2902
0.1UF
20% 10V CERM 402
V+
R2914
100
1 1% 1/16W MF-LF 402 2
VREFMRGN
VREFMRGN
VREFMRGN C3
CPU_GTLREF
OUT
10 70
VCC
U2901
PCA9557
QFN 3
VB4
Place close to U1000.AD26
26 VREFMRGN_CPUFSB_EN
ADDR=0x30(WR)/0x31(RD)
4 5
A0 A1 A2
39 39
IN BI
=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
1 2
SCL SDA
THRM
P0 P1 P2 P3 P4 P5 P6 P7 RESET*
NC
7 9 10 11 12 13 14
VREFMRGN_CPUFSB_EN 26 VREFMRGN_CA_SODIMMA_EN 26 VREFMRGN_DQ_SODIMMA_EN 26 VREFMRGN_CA_SODIMMB_EN 26 VREFMRGN_DQ_SODIMMB_EN 26
R2913
100K
5% 1/16W MF-LF 402
2 VREFMRGN 1
NC NC
PCA9557D_RESET_L
15
IN
25
PAD
17
GND
8
A
Required zero ohm resistors when no VREF margining circuit stuffed
SYNC_MASTER=K24_MLB
PAGE TITLE
FSB/DDR3 Vref Margining

DRAWING NUMBER SIZE
PART NUMBER
116S0004 116S0004 116S0004 116S0004
QTY
1 1 1 1
DESCRIPTION
RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF
REFERENCE DES
R2903 R2905 R2909 R2911
CRITICAL
CRITICAL CRITICAL CRITICAL CRITICAL
BOM OPTION
NO_VREFMRGN NO_VREFMRGN NO_VREFMRGN NO_VREFMRGN
R
Apple Inc.
051-7982
REVISION
C.0.0
BRANCH PAGE
29 OF 109
SHEET
8
Page Notes
Power aliases required by this page: - =PP1V5_S0_MEM_A - =PP1V5_S3_MEM_A - =PP0V75_S0_MEM_VTT_A - =PPSPD_S0_MEM_A (2.5 - 3.3V)
7
8 =PP1V5_S3_MEM_A
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)

1
C3100
10UF
20% 6.3V X5R 603
C3101
10UF
20% 6.3V X5R 603
C3110
0.1UF
20% 10V CERM 402
C3111
0.1UF
20% 10V CERM 402
C3112
0.1UF
20% 10V CERM 402
C3113
0.1UF
20% 10V CERM 402
C3114
0.1UF
20% 10V CERM 402
C3115
0.1UF
20% 10V CERM 402
C3116
0.1UF
20% 10V CERM 402
C3117
0.1UF
20% 10V CERM 402
Signal aliases required by this page: - =I2C_SODIMMA_SCL - =I2C_SODIMMA_SDA
BOM options provided by this page:
26 PP0V75_S3_MEM_VREFDQ_A
(NONE)
D
1
C3130
2.2UF
20% 6.3V
C3131
0.1UF
20% 10V
CERM 402-LF
CERM 402
1 3
71 15
IN
MEM_A_CKE<0>
73 75
KEY
NC
71 15
77 79 81
IN
MEM_A_BA<2>
71 15 71 15
IN IN
MEM_A_A<12> MEM_A_A<9>
83 85 87
71 15 71 15
IN IN
89 91 93
71 15 71 15
IN IN
95 97 99
71 15
IN IN
MEM_A_CLK_P<0> MEM_A_CLK_N<0>
101 103 105
71 15
71 15 71 15
IN IN
MEM_A_A<10> MEM_A_BA<0>
107 109 111
71 15 71 15
IN IN
MEM_A_WE_L MEM_A_CAS_L
113 115 117
71 15 71 15
IN IN
MEM_A_A<13> MEM_A_CS_L<1>
119 121 123
NC
71 15 71 15
125 127
BI BI
MEM_A_DQ<34> MEM_A_DQ<35>
129 131 133
71 15 71 15
BI BI
MEM_A_DQS_N<4> MEM_A_DQS_P<4>
135 137 139
71 15 71 15
BI BI
141 143 145
71 15 71 15
BI BI
147 149 151
71 15
IN
MEM_A_DM<5>
153 155
71 15 71 15
BI BI
157 159 161
71 15 71 15
BI BI
163 165 167
71 15 71 15
BI BI
169 171 173
71 15 71 15
BI BI
175 177 179
71 15 71 15
BI BI
181 183 185
71 15
IN
MEM_A_DM<7>
187 189
71 15 71 15
BI BI
191 193 195
MEM_A_SA<0>
8 =PPSPD_S0_MEM_A
197 199
MEM_A_SA<1>
201 203
CKE0 CKE1 VDD OMIT VDD NC J3100 A15 A14 BA2 F-RT-THB VDD VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK0 CK1 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD ODT1 A13 NC S1* VDD VDD VREFCA TEST VSS VSS DQ36 DQ32 DQ33 DQ37 VSS VSS DQS4* DM4 DQS4 VSS DQ38 VSS DQ34 DQ39 DQ35 VSS VSS DQ44 DQ40 DQ45 DQ41 VSS VSS DQS5* DQS5 DM5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ55 DQ50 VSS DQ51 VSS DQ60 DQ61 DQ56 DQ57 VSS VSS DQS7* DM7 DQS7 VSS VSS DQ62 DQ58 DQ63 DQ59 VSS VSS SA0 EVENT* VDDSPD SDA SA1 SCL VTT VTT (SYMBOL 2 OF 2)
DDR3-SODIMM-DUAL-M97-3
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
MEM_A_CKE<1>
IN
15 71
71 15 71 15
BI BI
5 7 9
IN IN
9 15 71 71 15
IN
MEM_A_DM<0>
11 13
IN IN
15 71 15 71
71 15 71 15
BI BI
15 17 19
IN IN
15 71 15 71
71 15 71 15
BI BI
21 23 25
IN IN
15 71 15 71
71 15 71 15
BI BI
27 29 31
MEM_A_CLK_P<1> MEM_A_CLK_N<1>
IN IN
15 71 15 71
71 15 71 15
BI BI
33 35 37
MEM_A_BA<1> MEM_A_RAS_L
IN IN
15 71 15 71
71 15 71 15
BI BI
39 41 43
MEM_A_CS_L<0> MEM_A_ODT<0>
IN IN
15 71 15 71
71 15 71 15
BI BI
45 47 49
MEM_A_ODT<1>
IN
15 71
71 15 71 15
BI BI
51 53 55
NC
71 15 71 15
BI BI
57 59 61
BI BI
15 71 15 71 71 15
IN
MEM_A_DM<2>
63 65
MEM_A_DM<4>
IN
15 71
71 15 71 15
BI BI
67 69 71
BI BI
15 71 15 71
VREFDQ VSS VSS OMIT DQ4 DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* J3100 DQS0 DM0 F-RT-THB VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 RESET* DQS1 VSS VSS DQ14 DQ10 DQ15 DQ11 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 VSS DQS2 DQ22 VSS DQ23 DQ18 VSS DQ19 DQ28 VSS DQ24 DQ29 VSS DQ25 VSS DQS3* DQS3 DM3 VSS VSS DQ30 DQ26 DQ31 DQ27 VSS VSS
DDR3-SODIMM-DUAL-M97-3
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
BI BI
15 71 15 71
BI BI
15 71 15 71
(SYMBOL 1 OF 2)
BI BI
15 71 15 71
BI BI
15 71 15 71
MEM_A_DM<1> MEM_RESET_L
IN IN
15 71 28 29
BI BI
15 71 15 71
BI BI
15 71 15 71
MEM_A_DM<3>
IN
15 71
BI BI
15 71 15 71
BI BI
15 71 15 71
BI BI
15 71 15 71
BI BI
15 71 15 71
KEY
BI BI
15 71 15 71
516-0201
BI BI
15 71 15 71
BI BI
15 71 15 71
BI BI
15 71 15 71
MEM_A_DM<6>
IN
15 71
BI BI
15 71 15 71
PP0V75_S3_MEM_VREFCA_A
26
BI BI
15 71 15 71
1
C3135
2.2UF
20% 6.3V
C3136
0.1UF
20% 10V
BI BI
15 71 15 71
CERM 402-LF
CERM 402
BI BI
15 71 15 71
MEM_EVENT_L =I2C_SODIMMA_SDA =I2C_SODIMMA_SCL
OUT
21 28 36
BI IN
39 39
"Factory" (top) slot

=PP0V75_S0_MEM_VTT_A
8
1 1
A
2
C3140
2.2UF
20% 6.3V CERM 402-LF 2
R3140
10K
5% 1/16W MF-LF 402
R3141
10K
5% 1/16W MF-LF 402 2 1
C3150
2.2UF
20% 6.3V CERM 402-LF
C3151
2.2UF
20% 6.3V
SYNC_MASTER=K24_MLB
PAGE TITLE
CERM 402-LF
DDR3 SO-DIMM Connector A

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
516-0201
SPD ADDR=0xA0(WR)/0xA1(RD)
C.0.0
BRANCH PAGE

31 OF 109
SHEET
8
Page Notes
Power aliases required by this page: - =PP1V5_S0_MEM_B - =PP1V5_S3_MEM_B - =PP0V75_S0_MEM_VTT_B - =PPSPD_S0_MEM_B (2.5 - 3.3V)
7
8 =PP1V5_S3_MEM_B
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)

1
C3200
10UF
20% 6.3V X5R 603
C3201
10UF
20% 6.3V X5R 603
C3210
0.1UF
20% 10V CERM 402
C3211
0.1UF
20% 10V CERM 402
C3212
0.1UF
20% 10V CERM 402
C3213
0.1UF
20% 10V CERM 402
C3214
0.1UF
20% 10V CERM 402
C3215
0.1UF
20% 10V CERM 402
C3216
0.1UF
20% 10V CERM 402
C3217
0.1UF
20% 10V CERM 402
Signal aliases required by this page: - =I2C_SODIMMB_SCL - =I2C_SODIMMB_SDA
BOM options provided by this page:
26 PP0V75_S3_MEM_VREFDQ_B
(NONE)
D
1
C3230
2.2UF
20% 6.3V
C3231
0.1UF
20% 10V
CERM 402-LF
CERM 402
1 3
71 15
IN
MEM_B_CKE<0>
73 75 77
KEY
71 15
IN
MEM_B_BA<2>
79 81
71 15 71 15
IN IN
MEM_B_A<12> MEM_B_A<9>
83 85 87
71 15 71 15
IN IN
89 91 93
71 15 71 15
IN IN
95 97 99
71 15
IN IN
MEM_B_CLK_P<0> MEM_B_CLK_N<0>
101 103 105
71 15
71 15 71 15
IN IN
MEM_B_A<10> MEM_B_BA<0>
107 109 111
71 15 71 15
IN IN
MEM_B_WE_L MEM_B_CAS_L
113 115 117
71 15 71 15
IN IN
MEM_B_A<13> MEM_B_CS_L<1>
119 121 123 125 127
71 15 71 15
BI BI
MEM_B_DQ<33> MEM_B_DQ<36>
129 131 133
71 15 71 15
BI BI
MEM_B_DQS_N<4> MEM_B_DQS_P<4>
135 137 139
71 15 71 15
BI BI
141 143 145
71 15 71 15
BI BI
147 149 151
71 15
IN
MEM_B_DM<5>
153 155
71 15 71 15
BI BI
157 159 161
71 15 71 15
BI BI
163 165 167
71 15 71 15
BI BI
169 171 173
71 15 71 15
BI BI
175 177 179
71 15 71 15
BI BI
181 183 185
R3240
10K
5% 1/16W MF-LF 402
71 15
IN
MEM_B_DM<7>
187 189
71 15 71 15
BI BI
191 193 195
MEM_B_SA<0>
8 =PPSPD_S0_MEM_B
197 199
MEM_B_SA<1>
201 203 205 207 209 211
CKE0 CKE1 VDD VDD OMIT NC A15 BA2 A14 J3200 VDD VDD F-RT-BGA3 A11 A12/BC* A9 A7 VDD VDD A6 A8 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK1 CK0 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD A13 ODT1 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DQS4* DM4 VSS DQS4 VSS DQ38 DQ34 DQ39 DQ35 VSS VSS DQ44 DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ47 DQ43 VSS VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DM6 DQS6* DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS DQ60 VSS DQ56 DQ61 DQ57 VSS DQS7* VSS DQS7 DM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS SA0 EVENT* VDDSPD SDA SCL SA1 VTT VTT
DDR3-SODIMM
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212
MEM_B_CKE<1>
IN
15 71
71 15 71 15
BI BI
5 7 9
IN IN
9 15 71 71 15
IN
MEM_B_DM<0>
11 13
IN IN
15 71 15 71
71 15 71 15
BI BI
15 17 19
IN IN
15 71 15 71
71 15 71 15
BI BI
21 23 25
IN IN
15 71 15 71
71 15 71 15
BI BI
27 29 31
MEM_B_CLK_P<1> MEM_B_CLK_N<1>
IN IN
15 71 15 71
71 15 71 15
BI BI
33 35 37
MEM_B_BA<1> MEM_B_RAS_L
IN IN
15 71 15 71
71 15 71 15
BI BI
39 41 43
MEM_B_CS_L<0> MEM_B_ODT<0>
IN IN
15 71 15 71
71 15 71 15
BI BI
45 47 49
MEM_B_ODT<1>
IN
15 71
71 15 71 15
BI BI
51 53 55
71 15 71 15
BI BI
57 59 61
BI BI
15 71 15 71 71 15
IN
MEM_B_DM<3>
63 65
MEM_B_DM<4>
IN
15 71
71 15 71 15
BI BI
67 69 71
BI BI
15 71 15 71
VREFDQ VSS OMIT DQ4 VSS DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* J3200 DQS0 DM0 F-RT-BGA3 VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ10 DQ14 DQ11 DQ15 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ18 DQ23 DQ19 VSS VSS DQ28 DQ24 DQ29 DQ25 VSS DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS
DDR3-SODIMM
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
BI BI
15 71 15 71
BI BI
15 71 15 71
(2 OF 2)
(1 OF 2)
BI BI
15 71 15 71
BI BI
15 71 15 71
MEM_B_DM<1> MEM_RESET_L
IN IN
15 71 27 29
BI BI
15 71 15 71
BI BI
15 71 15 71
MEM_B_DM<2>
IN
15 71
BI BI
15 71 15 71
BI BI
15 71 15 71
BI BI
15 71 15 71
BI BI
15 71 15 71
KEY
BI BI
15 71 15 71
516S0706
BI BI
15 71 15 71
BI BI
15 71 15 71
B
DDR3 GROUND RETURN CAPS (MCP SIDE)
8 =PP1V5_S0_MEM_MCP
BI BI
15 71 15 71
MEM_B_DM<6>
IN
15 71
C3222
0.1UF
20% 10V CERM 402
C3223
0.1UF
20% 10V CERM 402
C3224
0.1UF
20% 10V CERM 402
C3225
0.1UF
20% 10V CERM 402
C3226
0.1UF
20% 10V CERM 402
C3227
0.1UF
20% 10V CERM 402
C3228
0.1UF
20% 10V CERM 402
C3229
0.1UF
20% 10V CERM 402
BI BI
15 71 15 71
PP0V75_S3_MEM_VREFCA_B
26
BI BI
15 71 15 71
1
C3235
2.2UF
20% 6.3V
C3236
0.1UF
20% 10V
BI BI
15 71 15 71
CERM 402-LF
CERM 402
BI BI
15 71 15 71
MEM_EVENT_L =I2C_SODIMMB_SDA =I2C_SODIMMB_SCL
OUT BI IN
21 27 36 39
"Expansion" (bottom) slot

39
=PP0V75_S0_MEM_VTT_B
MTG PINS
1 1
A
2
C3240
2.2UF
20% 6.3V CERM 402-LF 2
R3241
10K
5% 1/16W MF-LF 402
MTG PIN MTG PIN MTG PIN MTG PIN
MTG PIN
MTG PIN
C3250
2.2UF
20% 6.3V
C3251
2.2UF
20% 6.3V
MTG PIN
MTG PIN
SYNC_MASTER=K24_MLB
PAGE TITLE
CERM 402-LF
CERM 402-LF
DDR3 SO-DIMM Connector B

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE
516S0706
SPD ADDR=0xA2(WR)/0xA3(RD)

32 OF 109
SHEET
DDR3 RESET Support

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.
R3309
16
IN
MCP_MEM_RESET_L
0
2 5% 1/16W MF-LF 402 1
MEM_RESET_L
OUT
27 28
=PP1V5_S3_MEMRESET
R3310 1
1K
Q3305
DMB53D0UDW
SOT-363
=PP3V3_S5_MEMRESET
5% 1/16W MF-LF 402
10K
Q1
R3300
5% 1/16W MF-LF 402
R3305
100K
5% 1/16W MF-LF 402
3.3V S5 is used because MEM_RESET must be high before 1.5V starts to rise to avoid glitch on MEM_RESET_L.
2
MEM_RESET_RC_L
MEM_RESET
20K
5% 1/16W MF-LF 402 2 2
0.1UF
20% 10V CERM 402
C3300
Q2
R3301 1
SYNC_MASTER=K24_MLB
PAGE TITLE
DDR3 Support
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

33 OF 109
SHEET
7
17
6
OUT PCIE_MINI_PRSNT_L
Q3401
SSM6N15FEAPE
SOT563
AP_PWR_EN
IN
21 32
D
17
3V S3 WLAN FET
OUT
MINI_CLKREQ_L
MOSFET CHANNEL
TPCP8102 P-TYPE 20-30 MOHM @2.5V 0.727 A (EDP)
Q3401
SSM6N15FEAPE
SOT563
RDS(ON) LOADING
MINI_CLKREQ_Q_L
155S0367 727 MA PEAK 606 MA NOMINAL MAX
CRITICAL
CRITICAL
CRITICAL
Q3450
TPCP8102
23V1K-SM
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=3.3V
L3405
90-OHM-100MA DLP11S
SYM_VER-1
R3452
0.002
1% 1/4W MF 1206 2
47 30
72 7
72 72 72 7
10%
16V
X5R
402
4 G
CONN_PCIE_MINI_R2D_N 1
2
CRITICAL
PCIE_MINI_R2D_N
0.1uF
PCIE_MINI_R2D_C_N
IN
17 72
10%
16V
X5R
402
0.1uF
IN
17 72
PCIE_MINI_R2D_P
PCIE_MINI_R2D_C_P
PP3V3_WLAN
PP3V3_WLAN_F
PP3V3_WLAN_R
CONN_PCIE_MINI_R2D_P 4
1 0603
1 3
2 4
C3431
PLACEMENT_NOTE=Place close to J3401.
FERR-120-OHM-3A
L3404
=PP3V3_S3_WLAN
1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V
8 30
516S0582
CRITICAL
72 7
L3402
90-OHM-100MA DLP11S
SYM_VER-1
C3430
C3422
0.1uF
20% 10V CERM 402
C3421
0.1uF
20% 10V CERM 402
C3420
10UF
20% 10V X5R 805
C3451
0.033UF
10% 16V X5R 402
R3451
10K
5% 1/16W MF-LF 402
C3450
0.1UF
1 2
R3450
100K
1 5% 1/16W MF-LF 402 2
CONN_PCIE_MINI_D2R_P 4
PCIE_MINI_D2R_P
500913-0302
F-ST-SM 32 31
72 7
J3401
OUT
17 72
CRITICAL
AIRPORT
P3V3WLAN_SS
PM_WLAN_EN_L
IN
30 32
CONN_PCIE_MINI_D2R_N 1
PCIE_MINI_D2R_N
OUT
17 72
L3401
90-OHM-100MA DLP11S
SYM_VER-1
10% 16V X5R 402
2 4 6 8 10
1 3 5 7 9 11 13 15 17 19
72 7 72 7
PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N
PLACEMENT_NOTE=Place close to Q3450.
IN
17 72
PLACEMENT_NOTE=Place close to Q3450.
PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N
1 2
ISNS_AIRPORT_P
IN
17 72
OUT OUT
47 76 47 76
ISNS_AIRPORT_N
NC NC
12 14 16 18 20 22 24 26 28 30
BLUETOOTH
4 73 7 73 7
L3403
90-OHM DLP0NS
SYM_VER-1
CRITICAL
21 23 25 27 29
CONN_USB2_BT_P CONN_USB2_BT_N
1 7 2
USB_BT_P USB_BT_N
BI
20 73
BI
20 73
PP3V3_S3_BT_F
1 C3432
0.01UF
10% 16V CERM 402
L3406
2 1
34
33
=PP3V3_S3_BT
FERR-120-OHM-1.5A
0402-LF
PLACEMENT_NOTE=PLACE L3406 NEAR J3401.
PLACEMENT_NOTE=PLACE C3432 NEAR J3401
RC VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN 3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET
PP3V3_WLAN_F =PP3V3_S3_WLAN PCIE_WAKE_L

OUT
7 17
30 47
8 30
R3453
110K
5% 1/16W
74LVC1G17
TC7SZ08AFEAPE 5 SOT665
7 2
U3402
SOT353-1 4
5
2
MF-LF 402
A
1
WLAN_SMIT_BUF
R3455
1
WLAN_SMIT_RC
1 5% 1/16W MF-LF 402 2
MINI_RESET_CONN_L
U3401
B
3
NC
3 1
WLAN_SMIT_DISCHRG
Q3455
3
NC
C3453
MINI_RESET_L
1
R3454
62K
5%
SSM3K15FV
SOD-VESM-HF
IN
25
1UF
10% 6.3V CERM 402 2
2
NOSTUFF
1/16W MF-LF 402
SYNC_MASTER=K24_MLB
2
PAGE TITLE
PM_WLAN_EN_L
30 32
X16 WIRELESS CONNECTOR

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
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34 OF 109
SHEET
=PP1V05_ENET_PHY (221mA typ - 1000base-T)
D
8
7mA typ - Energy Detect)
C3710
0.1UF =PP3V3_ENET_PHY
10% 16V X5R 402
C3711
0.1UF
10% 16V X5R 402
WF: Marvell numbers, update for Realtek
CRITICAL
2
L3715
FERR-120-OHM-1.5A
0402-LF
(43mA typ - 1000base-T) (19mA typ - Energy Detect) WF: Marvell numbers, update for Realtek
1
C3700
0.1UF
10% 16V X5R 402
C3701
0.1UF
10% 16V X5R 402
C3702
0.1UF
10% 16V X5R 402
CRITICAL
PP1V05_ENET_PHYAVDD
L3705
FERR-120-OHM-1.5A
0402-LF
C3714
2.2UF
10% 6.3V X5R 402
C3715
2.2UF
10% 6.3V X5R 402
C3716
0.1UF
10% 16V X5R 402
PP3V3_ENET_PHYAVDD
C3705
0.1UF
10% 16V X5R 402
C3706
0.1UF
10% 16V X5R 402
=PP3V3_ENET_PHY_VDDREG
If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45. NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
R3750
41 15 21 37 44 45 28 36 10 40 6 NO STUFF 3 4.7K
5% 1/16W MF-LF 402
R3751
4.7K
5% 1/16W MF-LF 402
R3752
4.7K
5% 1/16W MF-LF 402
=RTL8211_REGOUT
AVDD33
DVDD33
DVDD10
R3720
10K
R3725
4.7K
5% 1/16W MF-LF 402
AVDD10
FB10
VDDREG
If internal switcher is used, must place inductor within 5mm

2
of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor. If internal switcher is not used, VDDREG and REGOUT can float.
C
R3796
74 18
Alias to =PP3V3_ENET_PHY for internal switcher. Alias to GND for external 1.05V supply.
9
5% 1/16W MF-LF 402
CRITICAL 39
U3700
ENSWREG RTL8251CA-VB-GR
TQFP
IN
=RTL8211_ENSWREG
REGOUT
48
IN
ENET_CLK125M_TXCLK
0
5% 1/16W 402 MF-LF
74 ENET_CLK125M_TXCLK_R
22
TXC
RXC
19
74 ENET_CLK125M_RXCLK_R
R3790
22
2 5% 1/16W MF-LF 402
ENET_CLK125M_RXCLK
OUT
18 74
74 18 74 18 74 18 74 18
IN IN IN IN
ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3>
23 24 25 26
PLACE R3796 CLOSE TO U1400, PIN D24
TXD[0] TXD[1] TXD[2] TXD[3]
RGMII/MII
RXD[0] RXD[1]/TXDLY RXD[2]/AN0 RXD[3]/AN1
14 16 17 18
74 74 74 74
ENET_RXD_R<0> ENET_RXD_R<1> ENET_RXD_R<2> ENET_RXD_R<3>
R3791 R3792 R3793 R3794
22 22 22 22
1 1 1 1
ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3>
OUT OUT OUT OUT
18 74 18 74 18 74 18 74
74 18
IN
ENET_TX_CTRL
27
TXCTL
RXCTL
13
74
ENET_RXCTL_R
R3795
22
2 5% 1/16W MF-LF 402
ENET_RX_CTRL
OUT
18 74
74 18 74 18
IN BI
ENET_MDC ENET_MDIO
30 31
MDC MDIO
MANAGEMENT
MDI+[0] MDI-[0] MDI+[1] MDI-[1] MDI+[2] MDI-[2]
1 2 4 5 8 9 11 12
ENET_MDI_P<0> ENET_MDI_N<0> ENET_MDI_P<1> ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2> ENET_MDI_P<3> ENET_MDI_N<3>
BI BI BI BI BI BI BI BI
33 74 33 74
R3724
0
74 18
33 74 33 74
IN
ENET_RESET_L
RTL8211_PHYRST_L
29
PHYRSTB*
RESET MEDIA DEPENDENT
5% 1/16W MF-LF 402
33 74 33 74
C3725
0.1UF RTL8211_RSET 46
20% 10V CERM 402
RSET
REFERENCE
ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.

2
HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.
NO STUFF
MDI+[3] MDI-[3]
33 74 33 74
B
1
TP_RTL8211_CLK125
32
CLK125 CLOCK LED0/PHYAD0 LED1/PHYAD1 LED2/RXDLY

34 35 38 RTL8211_PHYAD0 RTL8211_PHYAD1 RTL8211_RXDLY NO STUFF 47
B
LED GND
20 33 7
R3730
2.49K
1% 1/16W MF-LF 402
74 32
IN
RTL8211_CLK25M_CKXTAL1 TP_RTL8211_CKXTAL2
42 43
CKXTAL1 CKXTAL2
C3790
10PF
5% 50V CERM 402
R3755
4.7K
5% 1/16W MF-LF 402
R3756
4.7K
5% 1/16W MF-LF 402
R3757
4.7K
5% 1/16W MF-LF 402
Reserved for EMI per RealTek request.
SYNC_MASTER=K24_MLB
PAGE TITLE
Ethernet PHY (RTL8211CL)

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
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Configuration Settings:
PHYAD = 01 (PHY Address 00001)

AN[1:0] = 11 (Full auto-negotiation) RXDLY TXDLY = 0 = 0 (RXCLK transitions with data) (No TXCLK Delay)
37 OF 109
SHEET
3.3V ENET FET

@ 2.5V Vgs: Rds(on) = 90mOhm max I(max) = 1.7A (85C) CRITICAL
Q3810
NTR4101P
SOT-23-HF
=PP3V3_S5_P3V3ENETFET
2
=PP3V3_ENET_FET
D
R3800
10K
5% 1/16W MF-LF 402
C3811
0.033UF
10% 16V X5R 402
1
R3810
100K P3V3ENET_EN_L
1 5% 1/16W MF-LF 402 2
C3810
0.01UF
2 1
P3V3ENET_SS
10% 16V CERM 402
Q3801
SSM6N15FEAPE
SOT563
IN
=P3V3ENET_EN
MOBILE: Recommend aliasing PM_SLP_RMGT_L and =P3V3ENET_EN. Nets separated on
ARB for alternate power options.
WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L
C
Q3805
SSM6N15FEAPE
SOT563
OUT
30
Pull-up is with power FET.
1.05V ENET FET

8
C
1.8V Vgs
=PP1V05_ENET_P1V05ENETFET
C3840
AC_OR_S0_L
0.1UF
20% 10V CERM 402
1 3
30 21
IN
AP_PWR_EN
CRITICAL
2
D
Q3840
1
Q3805
SSM6N15FEAPE
SOT563
=PP3V3_S5_P1V05ENETFET
1
R3840
100K
2 5% 1/16W MF-LF 402
Q3801
SSM6N15FEAPE
SOT563
P1V05ENET_SS
G S
SI2312BDS
SOT23
R3842
5
Q3841
SSM6N15FEAPE
SOT563
=PP1V05_ENET_FET
69.8K
1% 1/16W MF-LF 402
37 36 21
IN
SMC_ADAPTER_EN
R3841
10K
1 1
C3841
0.01UF
10% 16V
P1V05ENET_EN_L
67 63 36 21 7
1 1%
2 2 1/16W MF-LF 402
IN
PM_SLP_S3_L
CERM 402
Q3841
SSM6N15FEAPE
SOT563
P1V05ENET_EN_L_RC
IN
=P1V05ENET_EN
Non-ARB: Recommend aliasing PM_SLP_RMGT_L and =P1V05ENET_EN. Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
SYNC_MASTER=K24_MLB
PAGE TITLE
R3895
22
74 18
Ethernet & AirPort Support

2
IN
MCP_CLK25M_BUF0_R
RTL8211_CLK25M_CKXTAL1
OUT
31 74
DRAWING NUMBER
SIZE
5% 1/16W MF-LF 402 PLACEMENT_NOTE=Place close to U1400
Apple Inc.
R
051-7982
REVISION
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38 OF 109
SHEET
8
- COPY THIS PAGE FROM K36 CSA.39
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902
ENET_CONN_CTAP
C3900
0.1UF
10% 16V X5R 402
C3901
0.1UF
10% 16V X5R 402
C3902
0.1UF
10% 16V X5R 402
C3903
0.1UF
10% 16V X5R 402
ETHERNET CONNECTOR
CRITICAL
74 31
BI
ENET_MDI_P<1>
T3901 SM
OMIT CRITICAL
12
74
ENET_MDI_TRAN_P<1>
J3900
RJ45-10/100TX-K83
F-R-TH 1
74 31
BI
ENET_MDI_N<1>
11
74
ENET_MDI_TRAN_N<1>
ENET_MDI
TRAN_P0 TRAN_N0 TRAN_P1 TRAN_P2 TRAN_N2 TRAN_N1 TRAN_P3 TRAN_N3
10
R3903
ENET_CENTER_TAP<1>
1% 1 1/16W 2
75
402
2 3 4
TX
MF-LF
TLA-6T213HF
C
74 31
R3902
ENET_CENTER_TAP<3>
1% 1 1/16W 2 MF-LF
75
402
74 74
5 6 ENET_MDI_TRAN_P<3> ENET_MDI_TRAN_N<3> 7 8
BI
ENET_MDI_P<3>
74 31
BI
ENET_MDI_N<3>
RX
CRITICAL
9 10 11 12
12
74
SHIELD PINS
74 31
BI
ENET_MDI_N<2>
T3902 SM
ENET_MDI_TRAN_N<2>
74 31
BI
ENET_MDI_P<2>
11
74
ENET_MDI_TRAN_P<2>
514-0692
10
R3901
ENET_CENTER_TAP<2>
1% 1 1/16W 2
75
402
TX
MF-LF
TLA-6T213HF
4 9
R3900
ENET_CENTER_TAP<0>
1% 1 1/16W 2
75
402
74
MF-LF
74 31
BI
ENET_MDI_N<0>
ENET_MDI_TRAN_N<0>
74 31
BI
ENET_MDI_P<0>
74 ENET_MDI_TRAN_P<0>
RX
ENET_BOB_SMITH_CAP
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
1 1
C3911
10PF
5% 50V CERM 402-1
C3913
10PF
5% 50V CERM 402-1 2
C3915
10PF
5% 50V CERM 402-1
CRITICAL
C3917
10PF
5% 50V CERM 402-1
C3910
1000PF
10% 2KV CERM 1206
CRITICAL CRITICAL
1
CRITICAL
1
CRITICAL CRITICAL
CRITICAL CRITICAL
1
C3912
10PF
5% 50V CERM 402-1
C3914
10PF
5% 50V CERM 402-1
CRITICAL
C3916
10PF
5% 50V CERM 402-1
C3918
10PF
5% 50V CERM 402-1
PLACEMENT_NOTE=PLACE C3911-C3918 ON MDI LINES WITHOUT ANY STUBS
SYNC_MASTER=K24_MLB
PAGE TITLE
ETHERNET CONNECTOR
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
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39 OF 109
SHEET
4
CRITICAL
3
Q4590
TPCP8102
23V1K-SM
ODD Power Control

3
8
=PP5V_S3_ODD S
2
PP5V_SW_ODD_R
8
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
D G
NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.

34 8
R4596
100K
5% 1/16W MF-LF 402
C4595
0.068UF
10% 10V CERM 402
=PP3V3_S0_ODD
R4595
ODD_PWR_EN_LS5V_L
1
C4596
0.01UF
1 10% 16V CERM 402 2
100K
5% 1/16W MF-LF 402
ODD_PWR_SS
R4597
100K
5% 1/16W MF-LF 402
CRITICAL
D
ISNS_ODD_P
OUT
47 76
Q4596
SSM6N15FEAPE
SOT563
R4598 1
0.002
ODD_PWR_EN
2
1% 1/4W MF 1206 2 4
ISNS_ODD_N
OUT
47 76
Q4596
SSM6N15FEAPE
SOT563
5
21
IN
ODD_PWR_EN_L
47 7
PP5V_SW_ODD
CRITICAL
SATA ODD
34 8
90-OHM-100MA
DLP11S
SYM_VER-1
FL4520
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79 PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
=PP3V3_S0_ODD CRITICAL
72
SATA_ODD_R2D_UF_P 0.01UF
C4521
CERM 402
SATA_ODD_R2D_C_P
IN
20 72
10% 16V 1 2
C
36 7
R4590
33K
J4500
54722-0164
F-ST-SM 1 3 5 7 2 4 6 8 10 12 14 16 72 7 72 7
72
SATA_ODD_R2D_UF_N 0.01UF
C4520
CERM 402
SATA_ODD_R2D_C_N
IN
20 72
10% 16V
5% 1/16W MF-LF 402 2
PLACEMENT_NOTE=Place FL4520 close to J4500
SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P
OUT
SMC_ODD_DETECT
Indicates disc presence
9 11 13 15
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500 PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
90-OHM-100MA
DLP11S
SYM_VER-1
FL4525
C4526
0.01UF
72
SATA_ODD_D2R_UF_N
CERM 402
CRITICAL 3 SATA_ODD_D2R_N
OUT
20 72
10% 16V 1 2
516S0616
C4525
0.01UF
72
SATA_ODD_D2R_UF_P
CERM 402
SATA_ODD_D2R_P
OUT
20 72
10% 16V
CRITICAL
J4502
78171-0002
M-RT-SM
R4531
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

1 7 SYS_LED_ANODE_R
4.7
37
SYS_LED_ANODE
2
402 5% MF-LF
1 2
PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
B
CRITICAL
1/16W
SIL
518S0519
1
C4501
0.1UF
20% 10V CERM 402
C4502
0.1UF
20% 10V CERM 402
C4531
0.001UF
10% 50V CERM 402
CRITICAL
R4599
0.002
1% 1/4W MF 1206
L4500
FERR-70-OHM-4A
7
PP5V_S0_HDD_FLT
1 0603 PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
PP5V_S0_HDD_R
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2MM VOLTAGE=5V
1 3
2 4
=PP5V_S0_HDD
ISNS_HDD_P CRITICAL 90-OHM-100MA

DLP11S
SYM_VER-1
OUT OUT
47 76
FL4502
ISNS_HDD_N
47 76
72 7
SATA_HDD_D2R_C_N
C4515
0.01UF
2 10% 16V CERM
72
SATA_HDD_D2R_UF_N
SATA_HDD_D2R_N
CRITICAL
OUT
20 72
402
54722-0164
F-ST-SM 1 3 5 7 2 4 6 8 10 12 14 16
J4501
72 7
SATA_HDD_D2R_C_P
C4516
0.01UF
2 10% 16V CERM
72
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_P
OUT
20 72
402 PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
PLACEMENT_NOTE=Place C4515 next to C4516 PLACEMENT_NOTE=Place C4516 close to J4501
SATA HDD
NC
9 11 13 15
CRITICAL 90-OHM-100MA
DLP11S
SYM_VER-1
FL4501
PLACEMENT_NOTE=Place C4511 next to C4510 PLACEMENT_NOTE=Place C4510 close to MCP79

72
SYNC_MASTER=K24_MLB
SATA_HDD_R2D_C_N
IN PAGE TITLE
402
72 7
SATA_HDD_R2D_N
SATA_HDD_R2D_UF_N
C4511
0.01UF
2 10% 16V
CERM
SATA Connectors
DRAWING NUMBER SIZE
20 72
516S0616
72 7
SATA_HDD_R2D_P
72
SATA_HDD_R2D_UF_P
C4510
0.01UF
2 10% 16V
SATA_HDD_R2D_C_P
CERM 402
IN
Apple Inc.
R
051-7982
REVISION
C.0.0
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45 OF 109
SHEET
POR IS PLASTIC USB CONNECTOR PARTS BUT METAL PARTS SCHEMATIC AND CAD SYMBOLS HAVE BEEN USED AS ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES
Port Power Switch
USB PORT A (FRONT PORT)

PLACEMENT_NOTE=NEAR J4600
CRITICAL
CRITICAL
U4690
L4605
FERR-220-OHM-2.5A
7
C
20 20
TPS2064DGN
8
=PP5V_S3_EXTUSB USB_EXTA_OC_L
IN
MSOP
OUT1
PP5V_S3_RTUSB_A_ILIM
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
1 0603
PP5V_S3_RTUSB_A_F
OMIT
CRITICAL
OUT
8 3
OC1* EN1 OC2* EN2 OUT2

6
PP5V_S3_RTUSB_B_ILIM
C4605
0.01uF
20% 16V CERM 402
J4600
PLACEMENT_NOTE=NEAR J4600 CRITICAL
2
OUT
USB_EXTB_OC_L
5 4
USB-K83
F-RT-TH 5 6
L4600
90-OHM DLP0NS
SYM_VER-1
GND TPAD
NOSTUFF
1
1
CRITICAL
CRITICAL
73 USB_EXTA_MUXED_N
73 CONN_USB_EXTA_N 1 2
C4690
10UF
20% 6.3V X5R 603
C4691
0.1UF
20% 10V CERM 402
C4695
10UF
20% 6.3V X5R 603
C4696
100UF
20% 6.3V POLY-TANT CASE-B2-SM
C4617
10UF
20% 6.3V X5R 603
C4616
100UF
73 USB_EXTA_MUXED_P 1 2 73 CONN_USB_EXTA_P
20% 6.3V POLY-TANT CASE-B2-SM
3 4
2 5 3 4
We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.
NC IO NC IO
7 8
6 VBUS 1 GND
63
IN
=USB_PWR_EN
CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION
514-0689
D4600
RCLAMP0502N
SLP1210N6 CRITICAL NOSTUFF
PLACEMENT_NOTE=NEAR J4610 CRITICAL We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
1 0603 2
PP5V_S3_RTUSB_B_F
Place L4600 and L4605 at connector pin
C4615
0.01uF
20% 16V CERM 402
USB/SMC Debug Mux

2
B
OMIT
CRITICAL
=PP3V42_G3H_SMCUSBMUX SMC_DEBUG_YES
J4610
USB-K83
1
C4650
0.1UF
20% 10V CERM 402
R4650
10K
5% 1/16W MF-LF 402
PLACEMENT_NOTE=NEAR J4610 CRITICAL
F-RT-TH 5 6
L4610
90-OHM DLP0NS
SYM_VER-1
2 2
1 3 73 CONN_USB_EXTB_N 73 2 3 4
73 20
BI
USB_EXTB_N
VCC
38 37 36 38 37 36
CONN_USB_EXTB_P
IN OUT
SMC_RX_L SMC_TX_L
5 4
M+ MD+ D-
SMC_DEBUG_YES
Y+ Y-
1 2
73 20
BI
USB_EXTB_P
U4650
PI3USB102ZLE
TQFN
2 5 3 4 6 VBUS
73 20 73 20
BI BI
USB_EXTA_N
CRITICAL
1 GND
NC IO NC IO
USB_EXTA_P
514-0689 SEL
10 USB_DEBUGPRT_EN_L SEL=0 Choose SMC SEL=1 Choose USB
OE* GND
3
IN
36
D4610
RCLAMP0502N
SLP1210N6 CRITICAL NOSTUFF
SMC_DEBUG_NO
A
1
R4651
0
2 5% 1/16W MF-LF 402 1 5% 1/16W MF-LF 402
SYNC_MASTER=K24_MLB
PAGE TITLE
SMC_DEBUG_NO
USB PORT B (BACK PORT)

2
External USB Connectors

DRAWING NUMBER SIZE
R4652
0
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

46 OF 109
SHEET
8
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.
37 7 37 8
PP3V3_S5_AVREF_SMC =PP3V3_S5_SMC
D
C4902
22UF
20% 6.3V CERM 805 2 2 1 1
D
C4903
0.1UF
20% 10V CERM 402 2 1
C4904
0.1UF
20% 10V CERM 402
C4905
0.1UF
20% 10V CERM 402
C4906
0.1UF
20% 10V CERM 402
U4900
37 37 63 25 63
OUT OUT IN IN
SMC_EXCARD_PWR_EN SMC_RSTGATE_L ALL_SYS_PWRGD RSMRST_PWRGD
B12 A13 A12 B13
M12
H10
B1
M1
21 59 21
OUT OUT OUT OUT
PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L ESTARLDO_EN
C13 C12 D10 D13
J10 J11 H12 N10 M11 L10 N11 N12 M13 N13 L12 A7 B6 C7 D5 A6 B5 C6 J4 G3 H2 G1 H4 G4 F4 F1
NC
SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L SMC_CPU_ISENSE SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_MISC_ISENSE SMC_WAKE_SCI_L
C4920
0.1UF
20% 10V CERM 402
E1
NC
OUT
21 32 37
L11
D11
P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52
H8S2117
LGA-HF
(1 OF 3)
OMIT
P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P90 P91 P92 P93 P94 P95 P96 P97
L13 K12 K11 J12 K13
SMC_PM_G2_EN
PLACEMENT_NOTE=PLACE C4907 CLOSE TO U4900 PIN E1
OUT
7 57 63
NC NC NC
SMC_ADAPTER_EN
R4999
4.7
1 5% 1/16W MF-LF 402 2
SMC_VCL PP3V3_S5_SMC_AVCC
C4907
0.47UF
10% 6.3V CERM-X5R 402
IN IN IN IN IN IN IN IN IN IN OUT
37 37
AVCC
2
VCC
VCL AVREF NC
E5
37
41
U4900
H8S2117
LGA-HF
R4909
R4901
10K
5% 1/16W MF-LF 402
PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PIN M12

40
NC
10K
5% 1/16W MF-LF 402
NC NC NC
37
E11 D12 F11 E13
PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PIN M12

37 37
(3 OF 3)
OMIT
41 40 41 37 37 37 21 38 37
SMC_P24
NC
37
E12 F13
IN
SMC_RESET_L SMC_XTAL SMC_EXTAL
D3 A3 A2
RES* XTAL EXTAL
MD1 MD2
D1 H1 SMC_KBC_MDE
SMC_MD1
IN
38
SMC_P26
NC
73 38 19 73 38 19 73 38 19
E10 A9 D9 C8 B7 A8 D8 D7 D6
NMI
E3
SMC_NMI
IN
38
BI BI BI BI IN IN IN BI
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L LPC_CLK33M_SMC LPC_SERIRQ
NC
PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L (OC) SMB_MGMT_CLK SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_CLK32K_SUSCLK (OC) SMB_0_S0_DATA
OUT IN OUT IN BI IN IN IN IN IN IN IN BI
19 38
ETRST
19 38 35 36 37 38 35 36 37 38 39
H3 L9
SMC_TRST_L NO STUFF
1
73 38 19 73 38 19 25 73 25 38 19
IN
38
AVSS VSS
D2 L3 F10 B11 C5
R4902
10K
5% 1/16W MF-LF 402
R4998
10K
5% 1/16W MF-LF 402
R4903
0
5% 1/16W MF-LF 402
XW4900
SM 2 1
37 44 37 55 37 7 21 32 63 67 7 21 37 63 37 25 73 39
NC
37 39 46
D4 A5
SMC_P41 (OC)
BI OUT
SMB_MGMT_DATA SMS_ONOFF_L
B4 A1
NC NC
37 9
C2 B2 C1 C3 G2 F3
NOTE: P94 and P95 are shorted, P95 could be spare.
GND_SMC_AVSS
37 40 41
OUT OUT OUT IN BI
SMC_GFX_THROTTLE_L SMC_SYS_KBDLED SMC_TX_L SMC_RX_L SMB_0_S0_CLK (OC)
38 37 36 35 38 37 36 35 39
E4
U4900
(DEBUG_SW_1) (DEBUG_SW_2)
25 35 28 27 21 37 37
SMC_PA0 SMC_PA1 (OC) (OC) (OC) (OC) (OC) (OC)
N3 N1 M3 M2 N2 L1 K3 L2 B8 C9 B9 (See below) A10 C10
OUT OUT BI
PM_SYSRST_L USB_DEBUGPRT_EN_L MEM_EVENT_L

37
SMC_PA5
55 21
BI OUT
SYS_ONEWIRE PM_BATLOW_L
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
H8S2117
LGA-HF
(2 OF 3)
OMIT
PE0 PE1 PE2 PE3 PE4 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PH0 PH1 PH2 PH3 PH4 PH5
K1 J3 K2 J1 K4 K5 N5 M6 L5 M5 N4 L4 M4 M8 N7 K8 K7 K6 N6 M7 L6 E2 F2 J2 A4 B3 C4 (OC) (OC) (OC) (OC) (OC) (OC)
SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS
IN IN IN OUT IN
37 37 38 37 38 37 38 37 38
NC
SMC_SYS_LED SMC_LID
B
OUT IN
37 37 44 55
NC
21 34 7
OUT IN
SMC_RUNTIME_SCI_L SMC_ODD_DETECT
37
NC NC
SMC_MCP_SAFE_MODE
OUT
37
SMC_PB3
37
IN
SMC_EXCARD_CP
NC NC NC
=SMC_SMS_INT SMB_BSA_DATA SMB_BSA_CLK SMB_A_S3_DATA SMB_A_S3_CLK SMB_B_S0_DATA SMB_B_S0_CLK SMC_PROCHOT SMC_THRMTRIP SMC_PH2 ALS_GAIN
37
NC
37 37
B10 C11 A11 G11 G13 F12 H13 G10 G12 H11 J13 M10 N9 K10 L8 M9 N8 K9 L7
IN IN OUT OUT OUT OUT IN IN IN IN IN IN IN IN IN IN IN IN
SMC_EXCARD_OC_L SMC_GFX_OVERTEMP_L SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE ALS_LEFT ALS_RIGHT
IN BI BI BI BI BI BI OUT OUT
37 39 39 39 39 39 39
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
43 37 37 37 43 37 37 37
37 37
46 46 46 37 37
OUT
37
NC NC
37 37 37
SYNC_MASTER=K24_MLB
PAGE TITLE
1 C4950
0.033UF
10% 16V X5R 402
SMC
DRAWING NUMBER SIZE
C4951 0.033UF
10%
2
PLACEMENT_NOTE=PLACE C4950 CLOSE TO U4900 PIN M10 PLACEMENT_NOTE=PLACE C4951 CLOSE TO U4900 PIN N9 PLACEMENT_NOTE=PLACE C4952 CLOSE TO U4900 PIN K10
Apple Inc.
1 C4952
0.033UF
10% 16V X5R 402
051-7982
REVISION
16V X5R 402
C.0.0
BRANCH PAGE

SMC_PB3: SMC_IG_THROTTLE_L for MG systems. Otherwise, TP/NC okay (was ISENSE_CAL_EN)
49 OF 109
SHEET
.
6
36 36
SMC_BIL_BUTTON_L SMC_FAN_1_CTL
5
NC_SMC_BIL_BUTTON_L
MAKE_BASE=TRUE
4
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
3
37 8
2
SMC FSB to 3.3V Level Shifting =PP3V3_S0_SMC
36
SMC_FAN_2_CTL
NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
R5061
100K
5% 1/16W MF-LF 402
R5060
10K
5% 1/16W MF-LF 402
TO SMC
36
SMC_FAN_3_CTL
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
SMC Reset "Button" / Brownout Detect

36
SMC_GFX_THROTTLE_L SMC_IG_THROTTLE_L
MAKE_BASE=TRUE
21
36 37 36 8 =PP3V3_S5_SMC 55 37 36
ESTARLDO_EN
NC_ESTARLDO_EN
MAKE_BASE=TRUE
SMC_PROCHOT_3_3_L
56
OUT
36
SMC_BC_ACOK
MAKE_BASE=TRUE
=CHGR_ACOK
CPU_PROCHOT_BUF
6
D
SMC_MANUAL_RST_L NOSTUFF
1
C5000
0.1uF
20% 10V CERM 402
36
SMC_P24 SMC_P26 SMC_P41 SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE ALS_LEFT

SMC_GPU_VSENSE
TP_SMC_P24
MAKE_BASE=TRUE
R5000
CRITICAL
2
Q5060
DMB53D0UV
SOT-563
1K
5% 1/16W MF-LF 402 2
36
TP_SMC_P26
MAKE_BASE=TRUE
U5000
NCP303LSN
SOT23-5-HF 5
NC
36
TP_SMC_P41
MAKE_BASE=TRUE
TO CPU
R5062
CPU_PROCHOT_L
1
3.3K
5% 1/16W MF-LF 402
CD NC GND
3
OUT IN
1 2
36
SMC_RESET_L
SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE
41
70 14 10
OUT
36 38 36
BI
CPU_PROCHOT_L_R
Q5060
DMB53D0UV
SOT-563
SMC_MCP_DDR_ISENSE
MAKE_BASE=TRUE
41
S
1
R5001
0 SILK_PART=SMC_RST
5%
C5001
0.01UF
10%
36
SMC_CPU_FSB_ISENSE
MAKE_BASE=TRUE
41
Q5059
SSM6N15FEAPE
SOT563
1/10W MF-LF
Q5032
2
16V CERM
36
SMC_MCP_VSENSE
MAKE_BASE=TRUE
40
SSM3K15FV
SOD-VESM-HF
603 2
3
36
402
SMC_EXCARD_PWR_EN SMC_RSTGATE_L SMC_PB3 ALS_GAIN SMC_ANALOG_ID ALS_RIGHT
TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE
36
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
36 37 36 8 =PP3V3_S5_SMC
NC_SMC_PB3
MAKE_BASE=TRUE
SMC_PROCHOT
IN
36
2
36
NC_ALS_GAIN
MAKE_BASE=TRUE
U5001
SN74LVC1G02
36
SMC_TPAD_RST
SOT553-5 4
NC_SMC_ANALOG_ID
MAKE_BASE=TRUE
44 SMC_TPAD_RST_L
70 14 10
OUT
PM_THRMTRIP_L
36
NC_ALS_RIGHT
MAKE_BASE=TRUE
3
44 37 36 SMC_ONOFF_L
02
=PP3V3_S5_SMC
3
Q5059
SSM6N15FEAPE
SOT563
8 36 37
R5095
0
R5010
2
36
OUT
SMC_EXCARD_OC_L
EXCARD_OC_L
IN
20
10K
5% 1/16W MF-LF
SMC AVREF Supply
5% 1/16W MF-LF 402
402
SMC_THRMTRIP
IN
36
C
8
=PPVIN_S5_SMCVREF
1
CRITICAL
36
OUT
=SMC_SMS_INT
SMS_INT_L
MAKE_BASE=TRUE
IN
=PP3V3_S5_SMC
C
37 36 8 36
SMC_PA0 SMC_PA1
VR5020
REF3333
SOT23-3
PP3V3_S5_AVREF_SMC
MIN_LINE_WIDTH=0.4 mm
7 36
IN GND
OUT
MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
R5091 R5092
100K 100K
1 3
C5026
0.01UF
10% 16V
5%
1/16W
MF-LF
402
36
5%
1/16W
MF-LF
402
CERM 402
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE

RADAR 5925345
44 37 36 55 44 36
SMC_ONOFF_L SMC_LID SMC_PH2 SMC_TX_L SMC_RX_L
C5020
0.47UF
10% 6.3V
C5025
10uF
20% 6.3V
R5070 R5071 R5072 R5073 R5074
10K 100K 10K 10K 100K
5%
1 2
1/16W
MF-LF
402
2 CERM-X5R 402 X5R 603
5%
1/16W
MF-LF
402
R5011
0
21
GND_SMC_AVSS
36 38 36 35
5%
1 2
1/16W
MF-LF
402
MCP_SPKR
1 5% 1/16W MF-LF 402
SMC_MCP_SAFE_MODE
36 40 41
IN
36 38 36 35
5%
1 2
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
TABLE_ALT_HEAD
PART NUMBER

353S1912
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
38 36 38 36
SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_BC_ACOK SMC_GFX_OVERTEMP_L
R5077 R5078 R5079 R5080 R5087 R5050
10K 10K 10K 10K 470K 10K
5%
1 2
1/16W
MF-LF
402
5%
1 2
1/16W
MF-LF
402
353S1381
ALL
ISL60002-33, INTERSIL
38 36 38 36 55 37 36 36
5%
1 2
1/16W
MF-LF
402
5%
1 2
1/16W
MF-LF
402
5%
1 2
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
B
System (Sleep) LED Circuit
8
36
SMC_BS_ALRT_L
R5076 R5051 R5052 R5053 R5054 R5055 R5085 R5086
100K
B
1 2
5%
1/16W
MF-LF
402
36 36 36 36 36
SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH SMC_GPU_ISENSE SMC_NB_MISC_ISENSE
10K 10K 10K 10K 10K
5%
1 2
1/16W
MF-LF
402
5%
1 2
1/16W
MF-LF
402
5%
1 2
1/16W
MF-LF
402
5%
1 2
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
=PP5V_S3_SYSLED
36 32 21
SMC_ADAPTER_EN SMC_CASE_OPEN 10K 10K
1 2
SMC Crystal Circuit

1 1
Debug Power "Button"

36
5%
1 2
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R5031
523
1% 1/16W MF-LF 402
R5030
80.6
1% 1/16W MF-LF 402
C5010
15pF
36 SMC_XTAL
1 2 SMC_ONOFF_L NOSTUFF
1 1
36
SMC_EXCARD_CP
R5088
10K
5%
1/16W
MF-LF
402
OUT
NOSTUFF
36 37 44
36 63 36 21 7
PM_SLP_S5_L PM_SLP_S4_L
R5090
100K
5%
1/16W
MF-LF
402
SYS_LED_ILIM
CRITICAL
1
Y5010
20.00MHZ
2 5X3.2-SM SOD 2
5% 50V CERM 402 SILK_PART=PWR_BTN
R5015
0
5% 1/10W MF-LF 603 2 2
R5016
0
5% 1/10W MF-LF 603
PLACE R5015,R5001 ON BOTTOM SIDE PLACE R5016 ON TOP SIDE 37 8
=PP3V3_S0_SMC
C5011
15pF
1 2
SYS_LED_L_VDIV
1
2SA2154MFV-YAE
SILK_PART=PWR_BTN
Q5030
3
36
SMC_EXTAL
36
SMC_PA5
R5089
10K
R5032
1.47K
1% 1/16W MF-LF 402
SYS_LED_ANODE
OUT
34
5% 50V CERM 402
5%
1/16W
MF-LF
402
SYS_LED_L
A
Q5033
SSM3K15FV
SOD-VESM-HF
SYNC_MASTER=K24_MLB
D
PAGE TITLE 3
SMC Support
DRAWING NUMBER SIZE
36
IN
SMC_SYS_LED
Apple Inc.
1
051-7982
REVISION
C.0.0
BRANCH PAGE

50 OF 109
SHEET
LPC+SPI Connector
CRITICAL LPCPLUS
J5100
55909-0374
M-ST-SM
38 8 8
=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS LPC_AD<0> LPC_AD<1> SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS DEBUG_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L
31
32
D
LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3> SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
IN BI BI
25 73 19 36 73 19 36 73
1 73 36 19 73 36 19
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
BI BI
3 5 7
73 38 73 38 73 36 19 36 19 37 36 25
IN OUT IN OUT OUT IN OUT IN OUT IN
9 11 13 15 17 19 21 23 25 27 29
OUT IN IN BI IN OUT OUT OUT OUT OUT OUT
38 38 73 38 19 36 19 36 36 37 36 37 36 37 36 35 36 37 18
Alternate SPI ROM Support
36 37 36 36 37 36 35
33
34
48 38 8
=PP3V3_S5_ROM
R5190 1
10K
5% 1/16W MF-LF 402 2
73 48 38 21
516S0573
IN
SPI_CLK_R
73 48 38 21
C
R5191
10K
5% 1/16W MF-LF 402 2
1
IN
SPI_MOSI_R
C
LPCPLUS_NOT
R5146
0
1 2
SPI_MLB_CS_L
PLACEMENT_NOTE=PLACE NEXT TO U5110 =PP3V3_S5_ROM
8 38 48
5% 1/16W MF-LF 402
38 8
=PP3V3_S5_LPCPLUS
1
LPCPLUS
R5144
20K
C5124
0.1UF
20% 10V CERM 402
100K
5% 1/16W MF-LF 402
SEL HIGH OUTPUTS TO B1(ON BOARD ROM) SEL LOW OUTPUTS TO B0 (FRANKCARD ROM)
2
U5110
SPIROM_USE_MLB
MAKE_BASE=TRUE
21
BI
=SPI_CS1_R_L_USE_MLB
73 21
38
NC7SB3157P6XG 6 S SC70 B1 1
R5140
LPCPLUS
2
5% 1/16W MF-LF 402 2
VCC
SPI_MLB_CS_L SPI_ALT_CS_L Pull-up on debug card
OUT
38 4838 48
CRITICAL
4 A
GND B0 3 OUT
38
IN
SPI_CS0_R_L
PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO
LPCPLUS
R5156
0
73 38
OUT
SPI_ALT_CLK
1 5% 1/16W MF-LF 402
SPI_CLK_R
IN
21 38 48 73
LPCPLUS
R5157
0
1 5% 1/16W MF-LF 402 2
73 38
OUT
SPI_ALT_MOSI
SPI_MOSI_R
IN
21 38 48 73
LPCPLUS
R5158
0
73 38
PLACEMENT_NOT=PLACENEXT TO WHERE IT BRANCHES INTO TWO
IN
SPI_ALT_MISO
1 5% 1/16W MF-LF 402
SPI_MISO
OUT
21 48 73
SYNC_MASTER=K24_MLB
PAGE TITLE
PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO
LPC+SPI Debug Connector

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SHEET
MCP79 SMBUS "0" CONNECTIONS
SMC "0" SMBus Connections

8 =PP3V3_S0_SMBUS_SMC_0_S0
SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state
D
MCP79
U1400 (MASTER)
D
TRACKPAD
J5800 (Write: 0x90 Read: 0x91)
8 =PP3V3_S0_SMBUS_MCP_0
8 =PP3V3_S3_SMBUS_SMC_A_S3
R5200
2.0K
5% 1/16W MF-LF 402
R5201
2.0K
5% 1/16W MF-LF 402
SO-DIMM "A"
J3100 (Write: 0xA0 Read: 0xA1)
SMC
U4900 (MASTER)
R5250
4.7K
5% 1/16W MF-LF 402
R5251
4.7K
5% 1/16W MF-LF 402
MCP Temp
EMC1403-5: U5535 (Write: 0x98 Read: 0x99)
SMC
U4900 (MASTER)
R5270
1K
5% 1/16W MF-LF 402
R5271
1K
5% 1/16W MF-LF 402
73 21 13 SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
=I2C_SODIMMA_SCL =I2C_SODIMMA_SDA
27
36 SMB_0_S0_CLK 36 SMB_0_S0_DATA
75 SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
=I2C_MCPTHMSNS_SCL =I2C_MCPTHMSNS_SDA
42
36 SMB_A_S3_CLK 36 SMB_A_S3_DATA
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
=I2C_TPAD_SCL =I2C_TPAD_SDA
45
73 21 13 SMBUS_MCP_0_DATA
MAKE_BASE=TRUE
27
75 SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
42
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
45
SO-DIMM "B"
J3200 (Write: 0xA2 Read: 0xA3)
SENSOR ADC
U6000 (WRITE: 0X10 READ: 0X11)
1
MCPSMC_DIGITEMP_YES
R5203
0
5% 1/16W MF-LF 2 402 1MCPSMC_DIGITEMP_YES
=I2C_SODIMMB_SCL =I2C_SODIMMB_SDA
28
=I2C_SMC_ADCS_SCL =I2C_SMC_ADCS_SDA
47
28
47
SENSOR ADC CAN ONLY WORK IN S0 AS IT HAS I2C BUS PULLED UP TO S0 POWER RAIL
R5204
0
5% 1/16W MF-LF 2 402
Mikey
U6880 (WRITE: 0X72 READ: 0X73)
SMC "Battery A" SMBus Connections

39 54 8 =PP3V42_G3H_SMBUS_SMC_BSA
SMC "B" SMBus Connections
39 I2C_MIKEY_SCL_R
MAKE_BASE=TRUE
=I2C_MIKEY_SCL =I2C_MIKEY_SDA
C
8 =PP3V3_S0_SMBUS_SMC_B_S0
1 1 1 1
39 I2C_MIKEY_SDA_R
MAKE_BASE=TRUE
39 54
SMC
U4900 (MASTER)
R5280
1K
5% 1/16W MF-LF 402
R5281
1K
5% 1/16W MF-LF 402
BATTERY
J6950 (See Table)
SMC
U4900 (MASTER)
R5260
2.0K
5% 1/16W MF-LF 402
R5261
2.0K
5% 1/16W MF-LF 402
CPU Temp
EMC1403-5: U5515 (Write: 0x98 Read: 0x99)
MCP79 SMBUS "1" CONNECTIONS

36 SMB_BSA_CLK 36 SMB_BSA_DATA 8 =PP3V3_S0_SMBUS_MCP_1
SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
=SMBUS_BATT_SCL =SMBUS_BATT_SDA
55
39 36 SMB_B_S0_CLK 39 36 SMB_B_S0_DATA
75 SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
=I2C_CPUTHMSNS_SCL =I2C_CPUTHMSNS_SDA
42
SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
55
75 SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
42
MCPSMC_DIGITEMP_NO
1
MCPSMC_DIGITEMP_NO
MCP79
U1400 (MASTER) (SLAVE: WRITE:0XE0 READ:0XE1)
73 21 SMBUS_MCP_1_CLK 73 21 SMBUS_MCP_1_DATA
R5230
2.0K
5% 1/16W MF-LF 402
R5231
2.0K
5% 1/16W MF-LF 402
Mikey
U6880
Battery Charger
ISL6258A - U7000
MCPSMC_DIGITEMP_NO
SMC "B" SMBUS SIGNALS ALSO GET CONNECTED TO MCP SMBUS 1 CONNECTIONS(SEE LEFT SIDE)
(WRITE: 0X72 READ: 0X73)
2 2
R5232 0 2 1 R5233 0 2 1
5%39 I2C_MIKEY_SCL_R 1/16W MF-LF 402
Battery
39 54
(Write: 0x12 Read: 0x13)
=I2C_MIKEY_SCL =I2C_MIKEY_SDA
Battery Manager - (Write: 0x16 Read: 0x17) Battery Temp - (Write: 0x90 Read: 0x91)
=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA
56
39 54 56
39 I2C_MIKEY_SDA_R
5% 1/16W MF-LF 402 MCPSMC_DIGITEMP_NO
B
MCPSMC_DIGITEMP_YES 1
SMC "Management" SMBus Connections

R5235
The bus formerly known as "Battery B"
8 =PP3V3_S3_SMBUS_SMC_MGMT
0
5% 1/16W MF-LF 2 402 1
MCPSMC_DIGITEMP_YES
SMC
0
U4900 (MASTER)
R5290
4.7K
5% 1/16W MF-LF 402
R5291
4.7K
5% 1/16W MF-LF 402
Vref DACs
U2900 (Write: 0x98 Read: 0x99)
R5234
5% 1/16W MF-LF 2 402
36 SMB_MGMT_CLK
75 SMBUS_SMC_MGMT_SCL
MAKE_BASE=TRUE
=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA
26
SMC
U4900 (MASTER)
36 SMB_MGMT_DATA
75 SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
26
SMC "B" SMBUS

SMB_B_S0_CLK SMB_B_S0_DATA
36 39
Margin Control
U2901 (Write: 0x30 Read: 0x31)
36 39
=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
26
26
MCP SMBUS1 ACTS AS SLAVE DEVICE FOR MCPSMC_DIGITEMP_YES STUFFED
SYNC_MASTER=K24_MLB
PAGE TITLE
K84 SMBUS CONNECTIONS

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SHEET
7
CPU Voltage Sense / Filter
XW5309
8
=PPVCORE_S0_CPU_VSENSE
1
SM 2
R5309
4.53K
CPUVSENSE_IN
1 1% 1/16W MF-LF 402
SMC_CPU_VSENSE
OUT
36
PLACEMENT_NOTE=Place near U1000 center
C5309
0.22UF
20% 6.3V
X5R 402
GND_SMC_AVSS Place RC close to SMC
36 37 40 41
MCP Voltage Sense / Filter

XW5359
8
=PPVCORE_S0_MCP_VSENSE
1
SM 2
R5359
4.53K
MCPVSENSE_IN
1 1% 1/16W MF-LF 402
SMC_MCP_VSENSE
OUT
37
PLACEMENT_NOTE=Place near U1400 center
C5359
0.22UF
20% 6.3V
X5R 402
36 37 40 41
C
PBUS VOLTAGE SENSE ENABLE & FILTER
Q5315
NTUD3169CZ
SOT-963
N-CHANNEL
D
PBUSVSENS_EN_L
R5316
63
IN
=PBUSVSENS_EN
G S
100K
1% 1/16W MF-LF 402 2
Enables PBUS VSense divider when high.
1 3 D
PPBUS_G3HRS5_VSENSE
R5385
5
8
G S
27.4K
1% 1/16W MF-LF 402 2
=PPBUS_G3HRS5
RTHEVENIN = 4573 OHMS SMC_PBUS_VSENSE
P-CHANNEL
R5315
100K
1% 1/16W MF-LF 402
OUT
36
1
1
R5386
5.49K
1%
C5385
0.22UF
20% 6.3V
1/16W MF-LF 402
2 2
PBUSVSENS_EN_L_DIV
X5R 402
36 37 40 41
SYNC_MASTER=K24_MLB
PAGE TITLE
VOLTAGE SENSING
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MCP VCore Current Sense Filter

R5416
4.53K
60
MCPCORES0_IMON
1
1% 1/16W MF-LF 402
SMC_MCP_CORE_ISENSE
OUT
37
C5472
0.22UF
20% 6.3V
X5R 402
D
36 37 40 41
MCP MEM VDD Current Sense
=PP3V3_S0_MCPDDRISNS
64
IN
P1V5_S0_KELVIN
MEM_SENSE
64
IN
P1V5_S0_SENSE
1 1 5
U5400
OPA348 SC70-5
4
MEM_SENSE
1
C5400
0.1uF
20% 10V CERM 402
R5410
0
5% 1/16W MF-LF 402
MEM_SENSE
MEM_SENSE C5434
0.1UF
1 2 3 2
MCP MEM VDD Current Sense Filter

MEM_SENSE
R5417
4.53K
1 2
1% 1/16W MF-LF 402 1
P1V5_S0_SENSE_E
Q5401
2 SOD
10% 16V X5R 402
Gain: 50x
SMC_MCP_DDR_ISENSE
2SA2154MFV-YAE
1
MEM_SENSE R5411
0
1 5% 1/16W MF-LF 402 2
OUT
37
MEM_SENSE
C5435
0.22UF
20% 6.3V 2 X5R 402
MEM_SENSE
P1V5_S0_SENSE_B
P1V5_S0_SENSE_AMP
C
36 37 40 41
P1V5_S0_SENSE_C GND_SMC_AVSS
R5412
118
1% 1/16W MF-LF 402
Place RC close to SMC
MEM_SENSE
CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE

8
=PP3V3_S0_CPUVTTISNS
1
1P05_HIGH_SIDE_SENSE
R5492
0.01
0.5% 1W MF 0612-1
C5417
0.1uF
20% 10V CERM 402
CPU VCore Load Side Current Sense / Filter

3
2
V+
R5471
6.19K
IN
=PPCPUVCORE_VTT_ISNS_R
1 3
2 4
=PPCPUVCORE_VTT_ISNS
OUT
U5402
INA213
5
R5418
59
IN
IMVP6_IMON
SMC_CPU_ISENSE
OUT
36
1% 1/16W
76 ISNS_CPUVTT_N
ININ+
SC70
OUT
REF
4.53K
CPUVTT_IOUT
1
1%
SMC_CPU_FSB_ISENSE
OUT
37
MF-LF 402
R5480
17.4K
1% 1/16W MF-LF 402
C5470
0.22UF
20% 6.3V
1
76 ISNS_CPUVTT_P
1/16W MF-LF 402
C5436
0.22UF
20% 6.3V
2 X5R 402
GND
2
GND_SMC_AVSS
X5R 402
36 37 40 41
GND_SMC_AVSS
36 37 40 41
DC-IN (BMON) CURRENT SENSE

R5401
4.53K
56
DC-IN (AMON) CURRENT SENSE

R5481
4.53K
IN
CHGR_BMON
1
1% 1/16W MF-LF 402
SMC_BATT_ISENSE
OUT
36
56
IN
CHGR_AMON
1
1% 1/16W
SMC_DCIN_ISENSE
OUT
36
C5490
0.22UF
20% 6.3V X5R 402
MF-LF 402
C5487
0.22UF
20% 6.3V X5R 402
GND_SMC_AVSS 36 37 40 41
GND_SMC_AVSS
36 37 40 41
PLACE R5401 AND C5490 CLOSE TO SMC
SYNC_MASTER=K24_MLB
PAGE TITLE
Current Sensing
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SHEET
CPU T-Diode Thermal Sensor

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
8
=PP3V3_S0_CPUTHMSNS
1
R5515
47
2 5% 1/16W MF-LF 402
PP3V3_S0_CPUTHMSNS_R
D
76 10
APN 353S2571
1 VDD
C5515
0.1uF
20% 10V CERM 402
R5516
10K
1% 1/16W MF-LF 402
R5517
10K
5% 1/16W MF-LF 402
BI
CPU_THERMD_P
SIGNAL_MODOL=EMPTY
U5515
EMC1413
DFN 2 DP1 3 DN1
2
C5521
DETECT CPU DIE TEMPERATURE 0.0022uF
10% 50V CERM 402
THERM*/ADDR
7 8 9 10
CPUTHMSNS_THERM_L CPUTHMSNS_ALERT_L =I2C_CPUTHMSNS_SDA =I2C_CPUTHMSNS_SCL

39
CRITICAL
ALERT* SMDATA SMCLK
76 10
BI
CPU_THERMD_N
4 DP2/DN3 5 DN2/DP3 GND 6
BI BI
39
THRM_PAD 11
76 CPUTHMSNS_D2_P 3
SIGNAL_MODOL=EMPTY
Q5501
DETECT FIN-STACK TEMPERATURE
C5520
0.0022uF
10% 50V CERM 402
PLACEMENT NOTE: PLACE U5515 NEAR CPU
BC846BMXXH
SOT732-3 2 76 CPUTHMSNS_D2_N
MCP T-Diode Thermal Sensor

MCP_T_DIODE_SENSOR
8
INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
=PP3V3_S0_MCPTHMSNS
1
R5535
47
2 5% 1/16W MF-LF 402
MCP_T_DIODE_SENSOR
PP3V3_S0_MCPTHMSNS_R
MCP_T_DIODE_SENSOR
APN 353S2571 1
VDD
MCP_T_DIODE_SENSOR
1
C5535
0.1uF
20% 10V CERM 402
R5536
10K
1% 1/16W MF-LF 402
R5537
10K
5% 1/16W MF-LF 402
76 21
BI
MCP_THMDIODE_P
SIGNAL_MODOL=EMPTY
U5535
EMC1413
DFN 2 DP1 3 DN1
2
2
MCP_T_DIODE_SENSOR
C5522
DETECT MCP DIE TEMPERATURE 0.0022uF
10% 50V CERM 402
THERM*/ADDR
7 8 9 10
MCPTHMSNS_THERM_L MCPTHMSNS_ALERT_L =I2C_MCPTHMSNS_SDA =I2C_MCPTHMSNS_SCL
CRITICAL ALERT* SMDATA SMCLK

THRM_PAD 11
B
MCP_T_DIODE_SENSOR
76 21
BI
MCP_THMDIODE_N
4 DP2/DN3 5 DN2/DP3 GND 6
BI BI
39
MCP_T_DIODE_SENSOR
39
76 MCPTHMSNS_D2_P
SIGNAL_MODOL=EMPTY
C5540
0.0022uF
PLACEMENT NOTE: PLACE U5535 NEAR MCP
Q5502
BC846BMXXH
SOT732-3
DETECT HEAT-PIPE TEMPERATURE
10% 50V CERM 402
76 MCPTHMSNS_D2_N
MCP_T_DIODE_SENSOR
PLACEMENT_NOTE=PLACE CLOSE TO J4501 IN A CONVENIENT LOCATION
SYNC_MASTER=K24_MLB
PAGE TITLE
Thermal Sensors
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SHEET
=PP5V_S0_FAN_RT =PP3V3_S0_FAN_RT
CRITICAL
C
R5665
36
R5660 1
47K 5%
1/16W MF-LF 402
7
J5601
78171-0004 NC
M-RT-SM 5
2
1 2 3 4
SMC_FAN_0_TACH
47K 2
5% 1/16W MF-LF 402
FAN_RT_TACH
5V DC TACH MOTOR CONTROL GND
NC
R5661 1
1/16W MF-LF 402
1
100K 5%
2
Q5660
SSM3K15FV
SOD-VESM-HF
518S0521
FAN_RT_PWM
36
SMC_FAN_0_CTL
SYNC_MASTER=K24_MLB
PAGE TITLE
Fan
DRAWING NUMBER SIZE
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SHEET
KEYBOARD CONNECTOR PSOC USB CONTROLLER

TMP102 3V3 LDO
IC
PIN NAME
CURRENT
R_SNS
V_SNS
POWER
CRITICAL
V+
10UA 80UA
2.55 KOHM
0.0255 V 0.204 V
0.255E-6 W 16.32E-6 W 36E-3 W 0.72E-3 W 96E-6 W 294E-6 W
J5713
APN 518S0637
VDD VOUT
60MA MAX 60MA MAX 8MA (TYP) 14MA (MAX)
10 OHM 0.2 OHM 1.5 OHM
0.6 V 0.012 V 0.012 V 0.021 V
NC
IN
=PP3V3_S3_TPAD
32
USB INTERFACES TO MLB SPI HOST TO Z2
TRACKPAD PICK BUTTONS KEYBOARD SCANNER

PSOC
VDD
44 8
D
45 7 44 45 7 44 44
30 29
PP3V3_S3_PSOC
44 44 44 44 44 44
44
18V BOOSTER VIN 4MA (MAX) 4.7 OHM 0.0188 V 75.2E-6 W
44 7 44 7 44 7 44 7 44 7 44 7 44 7 44 7 44 7
WS_KBD1
28
WS_KBD2
27
WS_KBD3
26
PICKB_L BUTTON_DISABLE
WS_KBD4
25
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
WS_KBD5
24
Z2_HOST_INTN WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY
WS_KBD6
23
WS_KBD7
22
WS_KBD8
21
WS_KBD9
20
56
55
44
54
53
52
51
50
49
48
47
46
45
43
44 7
WS_KBD10
19
P2_5 P2_7 P0_1 P0_3 P0_5 P0_7 VSS VDD P0_6 P0_4 P0_2 P0_0 P2_6 P2_4
R5714
113
44 7
2
WS_KBD11
18
44 45 7
WS_CONTROL_KEY Z2_KEY_ACT_L NC TP_P4_5
45 7 45 7 45 7 45 7 45 7 45 7 45 7 45 7 45 7
Z2_DEBUG3 Z2_RESET PSOC_MISO PSOC_F_CS_L PSOC_MOSI PSOC_SCLK Z2_MISO Z2_CS_L Z2_MOSI Z2_SCLK
P1_7 P1_5 P1_3 18 P1_1 19 VSS 20 D+ 21 D22 VDD 23 P7_7 24 P7_0 25 P1_0 26 P1_2 27 P1_4 28 P1_6
45 7
P2_3 P2_1 3 P4_7 4 P4_5 5 P4_3 6 P4_1 7 P3_7 8 P3_5 9 P3_3 10 P3_1 11 P5_7 12 P5_5 13 P5_3 14 P5_1
2
CRITICAL
U5701
CY8C24794
MLF
(SYM-VER2)
APN 337S2983 OMIT
P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 THRML PAD
42 41 40 39 38 37 36 35 34 33 32 31 30 29
WS_KBD17 WS_KBD16N WS_KBD15_C WS_KBD14 WS_KBD13 WS_KBD12 WS_KBD11 WS_KBD10 WS_KBD9 WS_KBD8 WS_KBD7 WS_KBD1 WS_KBD2 WS_KBD3
7 44 44 44 7 44 7 44
44 WS_KBD15_C
1
1% 1/16W MF-LF 402
44 7 44 7 44 7
WS_KBD12
17
WS_KBD13
16
WS_KBD14
15 14
7 WS_KBD15_CAP 7 WS_KBD16_NUM
13
44 7 7 44 7 44 7 44 7 44 7 44 7 44 7 44 7 44
5%
WS_KBD17
12
R5715
10K 44 WS_KBD16N
1
1% 1/16W MF-LF 402
44 7 44 7
2
WS_KBD18
11
WS_KBD19
10
44 7 44 7
WS_KBD20
9
WS_KBD21
8
R5710
1K
44 7 44 7
WS_KBD22
7
WS_KBD23
6 5
37 36
OUT
SMC_ONOFF_L
7 WS_KBD_ONOFF_L 44 8 =PP3V42_G3H_TPAD 44 7 WS_LEFT_SHIFT_KBD 44 7 WS_LEFT_OPTION_KBD 44 7 WS_CONTROL_KBD

4 3 2 1
7 44
1
1/16W MF-LF 402
57
C5710
0.1UF
20% 10V CERM 402
15
16
17
ISOLATION CIRCUIT
TP_PSOC_SCL WS_KBD4 WS_KBD5 WS_KBD6 TP_PSOC_SDA TP_ISSP_SDATA_P1_0 ISSP SDATA/I2C SDA
44 8 5
CRITICAL
TC7SZ08AFEAPE
SOT665
NC
31 F-RT-SM
FF14-30A-R11B-B-3H C5725
0.1UF
7 44 7 44 7 44
=PP3V42_G3H_TPAD
44 8
SMC_MANUAL_RESET LOGIC
20% 10V CERM 402
=PP3V3_S3_TPAD
A
4 U5725
44 8
=PP3V42_G3H_TPAD
1
TP_PSOC_P1_3 Z2_CLKIN
7 45 44 7
WS_LEFT_SHIFT_KEY
44
C5758
0.1UF
10% 16V X7R-CERM 402
WS_LEFT_SHIFT_KBD
B
3 2
TP_P7_7 TP_ISSP_SCLK_P1_1 ISSP SCLK/I2C SCL =PP3V42_G3H_TPAD

44 8
C5726
0.1UF
APN 311S0406
DIFFERENTIAL_PAIR=USB2_TPAD
CRITICAL
20% 10V CERM 402
R5701
24
73 20 44 8 2 73 USB_TPAD_R_P
TC7SZ08AFEAPE
SOT665
CRITICAL
5
SN74LVC1G10
SC70
=PP3V3_S3_TPAD
A
4 U5726
USB_TPAD_P
1 5%
1/16W MF-LF 402
WS_LEFT_OPTION_KEY
44 7 WS_LEFT_SHIFT_KBD 44 44 7 WS_LEFT_OPTION_KBD 44 7
1 3 6
A B C
2 U5703
PP3V3_S3_PSOC
44
44 7
WS_LEFT_OPTION_KBD
Y
SMC_TPAD_RST_L
37
B
3
WS_CONTROL_KBD
TO MLB CONNECTOR
R5702
24
73 20
USB_TPAD_N
1 5%
1/16W MF-LF 402
2 73 USB_TPAD_R_N
C5727
0.1UF
R5769
1 33K
5%
=PP3V42_G3H_TPAD
44 8
R5770
33K
5%
R5771
33K
5% 1/16W MF-LF 402 2
DIFFERENTIAL_PAIR=USB2_TPAD
CRITICAL
20% 10V CERM 402
5 44 8
TC7SZ08AFEAPE
SOT665
1/16W MF-LF 402 2
1/16W MF-LF 402
=PP3V3_S3_TPAD
A
U5727
WS_CONTROL_KEY
44
44 7
WS_CONTROL_KBD
B
3
U5701 CHIP DECOUPLING PLACE C5701, C5702 & C5703 CLOSE TO U5701 VDD PIN 22 PLACE C5704, C5705 & C5706
Alternate Parts
TABLE_ALT_HEAD
CLOSE TO U5701
VDD PIN 49
PART NUMBER
TPAD BUTTONS DISABLE

311S0406

311S0447
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
ALL
NXP PART AS ALTERNATE
R5704
1.5
44
=PP3V3_S3_TPAD
2 8 44
44
BUTTON_DISABLE
PP3V3_S3_PSOC
1
5% 1/16W MF-LF 402
PLACE THESE COMPONENTS CLOSE TO J5800 THIS ASSUMES THERES A PP3V42_G3H PULL UP ON MLB
C5701
4.7UF
20% 6.3V X5R 603
C5702
100PF
5% 50V CERM 402
C5703
0.1UF
10% 16V X7R-CERM 402
C5704
100PF
5% 50V CERM 402
C5705
0.1UF
10% 16V X7R-CERM 402
C5706
4.7UF
20% 6.3V X5R 603
Q5701
SSM3K15FV
SOD-VESM-HF
A
PLACEMENT_NOTE=PLACE C5702 CLOSE TO U5701 VDD PIN 22 PLACEMENT_NOTE=PLACE C5704 CLOSE TO U5701 VDD PIN 49
SYNC_MASTER=K24_MLB
THE TPAD BUTTONS WILL BE DISABLE
1 SMC_LID 55 37 36
PAGE TITLE
WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V
WELLSPRING 1
DRAWING NUMBER SIZE
IN
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SHEET
5
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION: - POWER CONSUMPTION - DROOP LINE REGULATION - RIPPLE TO MEET ERS - 100-300 KHZ CLEAN SPECTRUM - STARTUP TIME LESS THAN 2MS
APN 152S0504
- R5812,R5813,C5818 MODIFIED
CRITICAL
45 8
=PP5V_S3_TPAD
CRITICAL
D
R5806
PP18V5_S3_SW
5% 1/16W MF-LF
L5801
3.3UH-870MA
D5802
SOD-323
0
1 2
R5805
INPUT_SW
5% 1/16W MF-LF 402
0
0.50MM 0.20MM
BOOST_SW
VLF3010AT-SM-HF
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE
PP18V5_S3
7 45
IPD FLEX CONNECTOR

APN 516S0689
B0520WSXG
APN 371S0313
1
1
402
PP5V_S3_BOOSTER
C5818
39PF
5% 50V
R5812
1M
1% 1/16W MF-LF 402
CRITICAL
APN 353S1401
CERM 402
J5800
55560-0228
0.50MM M-ST-SM
VIN
1
U5805
1
1
C5819
1UF
10%
0.20MM
L
TPS61045
QFN
FB CTRL
CRITICAL
BOOST_FB
2
2 44 7
1 3 5 7 9 11 13 15 17 19 21
0.50MM 0.20MM
C5800
0.1UF
20% 10V
25V X5R 603-1
Z2_CS_L
4 6 8 10 12 14 16
Z2_KEY_ACT_L Z2_RESET PSOC_F_CS_L PICKB_L PSOC_MISO PSOC_MOSI PSOC_SCLK =I2C_TPAD_SDA =I2C_TPAD_SCL PP18V5_S3
7 44 7 44 7 44 7 44 7 44 7 44 7 44 39 39 7 45
DO
Z2_BOOST_EN
7 45
1
44 7 Z2_DEBUG3 44 7 Z2_MOSI
CERM 402
SW PGND THRML GND
R5813
71.5K
1%
1/16W
44 7
Z2_MISO
44 7 Z2_SCLK 45 7 Z2_BOOST_EN 44 7 Z2_HOST_INTN
PAD
1
C5816
0.1UF
10%
C5817
2.2UF
10%
R5811
100K
1% 1/16W 2
MF-LF
402
NC
44 7 45 7
18 20 22
16V X7R-CERM 402
16V X5R 603 MF-LF 402
Z2_CLKIN
PP3V3_S3_LDO
0.50MM 0.20MM
3V3 LDO FOR IPD
R5873
=PP5V_S3_TPAD
45 8
10
1 1% 1/16W MF-LF 402 2
PP5V_S3_VR
45 7
PP3V3_S3_LDO
CRITICAL
2
R5836
APN 353S1364
0.2
VDD
1
402-HF
1/6W
1%
MF
C5838
0.1UF
10%
16V X7R-CERM 402
C5854
4.7UF
20% 6.3V
C5853
2.2UF
10%
16V
VR5802
MM3243DRRE MLF 1
X5R 603
CE GND
VOUT
PP3V3_S3_LDO_R
X5R 603
SYNC_MASTER=K24_MLB
PAGE TITLE
WELLSPRING 2
DRAWING NUMBER SIZE
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SHEET
R5921 PULLS UP SEL PINS TO ENTER STANDBY MODE WHEN PIN IS NOT BEING DRIVEN BY SMC
Analog SMS
R5922
1
10
5% 1/16W MF-LF 402
PP3V3_S3_SMS_FILT
1 2
=PP3V3_S3_SMS
C5922
0.1UF
10% 16V X5R 402
1 C5926
0.01UF
10% 16V CERM 402
VDD R5921
10K
5% 1/16W MF-LF 402
U5920
BMA141
LGA AMUX AX AY AZ GND 3 4 11 10 9 8
Desired orientation when placed on board top-side:
B
36
NC
7 12 6 5
NC
SMS_X_AXIS
DNC
CRITICAL
B
OUT
36
IN
SMS_ONOFF_L
SMS_PWRDN
MAKE_BASE=TRUE
SEL0 SEL1 ST
SMS_Y_AXIS
+Y
OUT
36
Front of system SMS_Z_AXIS +X
OUT
36
+Z (up)
NOSTUFF C5923
0.033UF
10% 16V X5R 402
NOSTUFF
1 C5924
0.033UF
10% 16V X5R 402
NOSTUFF
1 C5925
0.033UF
10% 16V X5R 402
Circle indicates pin 1 location when placed in correct orientation
C4950-C4952 CAP VALUES WILL BE USED TO GET CUT-OFF FREQUENCY OF ~146HZ
A
PAGE TITLE
A
SMS
DRAWING NUMBER SIZE
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59 OF 109
SHEET
8
PLACEMENT_NOTE=PLACE NEAR Q3450 OMIT
6
PLACEMENT_NOTE=PLACE NEAR Q4590 OMIT
5
8
4
DEBUG_ADC
3
R6003
1
2
DEBUG_ADC
1
R6004
1
=PP5V_S3_DEBUG_ADC_AVDD
10
5% 1/16W MF-LF 402
PP5V_S3_DEBUG_ADC_AVDD_FILT
PP5V_S3_DEBUG_ADC_DVDD_FILT
10
5% 1/16W MF-LF 402
=PP5V_S3_DEBUG_ADC_DVDD
8
XW6010
SM
30
XW6020
SM
DEBUG_ADC
1
DEBUG_ADC
1
DEBUG_ADC
1
DEBUG_ADC
1
PP3V3_WLAN_F
PP3V3_WLAN_F_XW DEBUG_ADC
1
34 7
PP5V_SW_ODD
PP5V_SW_ODD_XW DEBUG_ADC
1 2
C6000
0.1UF
20% 10V CERM 402
C6001
10UF
20% 6.3V X5R 603 12 13 21
C6002
0.1UF
20% 10V CERM 402
C6003
10UF
20% 6.3V X5R 603
R6010
634K
1% 1/16W MF-LF 402
R6020
1M PLACEMENT_NOTE=PLACE RC NEAR U6000 DEBUG_ADC
PLACEMENT_NOTE=PLACE RC NEAR U6000 DEBUG_ADC
R6012
1
1% 1/16W MF-LF 2 402
R6022
1
AVDD ADC_CH1 DEBUG_ADC

1
47 47
DVDD
DEBUG_ADC
PP3V3_WLAN_F_DIV DEBUG_ADC
1
226K
1% 1/16W MF-LF 402
ADC_CH0 DEBUG_ADC
1
47
PP5V_SW_ODD_DIV DEBUG_ADC
1
226K
1% 1/16W MF-LF 402
U6000
47 47 47 47 47 47 47
R6001
AD0 AD1 SDA SCL VREF REFCOMP
14 15
PLACEMENT_NOTE=PLACE CLOSE TO U4900
R6011
1M
1% 1/16W MF-LF 402
C6012
2.2UF
10% 6.3V X5R 402
R6021
681K
1% 1/16W MF-LF 402
C6022
2.2UF
10% 6.3V X5R 402
ADC_CH0 ADC_CH1 ADC_CH2 ADC_CH3 ADC_CH4 ADC_CH5 ADC_CH6 ADC_CH7
22 23 24 1 2 3 4 5 6
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
LTC2309
QFN
33
1 2
D
BI
39 39
=I2C_SMC_ADCS_SDA DEBUG_ADC
DEBUG_ADC
5% 1/16W MF-LF 402
17 16
ADC_SDA ADC_SCL ADC_VREF ADC_REFCOMP DEBUG_ADC

1
R6002
33
1 2
=I2C_SMC_ADCS_SCL
IN
5% 1/16W MF-LF 402
DIVIDER: ~ 2/5 DIVIDER: ~ 2/3 I2C ADDRESS: 0X10 / 0X11

10 9
DEBUG_ADC
1
DEBUG_ADC
1
GND
11 18 19 20
THRM PAD
25
C6004
0.1UF
20% 10V CERM 402
C6005
10UF
20% 6.3V X5R 603
C6006
2.2UF
20% 6.3V CERM 402-LF
ADC RANGE: 0V TO 4.096V LSB: 0.001V
47 8
=PP5V_S3_DEBUG_ISNS DEBUG_ADC
1
DEBUG_ADC
1
C6030
0.1UF
20% 10V CERM 402
C6040
0.1UF
20% 10V CERM 402
DEBUG_ADC
DEBUG_ADC
2
R6030
76 30
DEBUG_ADC
76
R6050
76 34
IN
ISNS_AIRPORT_P
243
1 1% 1/16W MF-LF 402 2
ISNS_AIRPORT_R_P
5
U6030
OPA330
SC70-5
IN
ISNS_ODD_P
499
1 1% 1/16W MF-LF 402 2 76
ISNS_ODD_R_P
5
DEBUG_ADC
1 3
U6040
OPA330
SC70-5
C
76 30
+IN -IN
V+ V2
R6034
ISNS_AIRPORT_IOUT
1
1 3
226K
1% 1/16W MF-LF 402
+IN -IN
V+ V2
R6054
ISNS_ODD_IOUT
1
DEBUG_ADC
ADC_CH2 DEBUG_ADC
1
47
226K
1% 1/16W MF-LF 402
C
ADC_CH4 DEBUG_ADC
1
47
DEBUG_ADC
R6031
IN
R6051
76 34
ISNS_AIRPORT_N
243
1 1% 1/16W MF-LF 402 2 76
ISNS_AIRPORT_R_N
GAIN: 1239X
C6034
2.2UF
IN
10% 6.3V X5R 402
ISNS_ODD_N
499
1 1% 1/16W MF-LF 402 2 76
ISNS_ODD_R_N
GAIN: 561X
C6054
2.2UF
10% 6.3V X5R 402
DEBUG_ADC
DEBUG_ADC 1
1
DEBUG_ADC
DEBUG_ADC
C6032
470PF
10% 50V CERM 402
R6032
301K
1% 1/16W MF-LF 402
R6033
1
DEBUG_ADC 1
1
DEBUG_ADC
301K
1% 1/16W MF-LF 402
C6052
470PF
10% 50V CERM 402
R6052
280K
1% 1/16W MF-LF 402 1
R6053
280K
1% 1/16W MF-LF 402 2
2 2
DEBUG_ADC
2 2
DEBUG_ADC
C6033
470PF
1 10% 50V CERM 402 2
C6053
470PF
1 10% 50V CERM 402 2
47 8
1
DEBUG_ADC
1
DEBUG_ADC
C6031
0.1UF
C6041
0.1UF
20% 10V 402
R6040
76 58
IN
ISNS_1V5_S3_P
3.65K
1 1% 1/16W MF-LF 402 2 76
ISNS_1V5_S3_R_P
5
DEBUG_ADC
20% 10V 2 CERM 402
2 CERM
PLACEMENT_NOTE=PLACE RC NEAR U6000 DEBUG_ADC DEBUG_ADC
U6031
OPA330
SC70-5
B
1 3
+IN -IN
V+ V2
R6044
ISNS_1V5_S3_IOUT
1
R6060
ADC_CH3 DEBUG_ADC
1
47 76 34
226K
1% 1/16W MF-LF 402
DEBUG_ADC
IN
ISNS_HDD_P
412
1 1% 1/16W MF-LF 402 2 76
ISNS_HDD_R_P
5
DEBUG_ADC
U6041
OPA330
SC70-5
R6041
76 58
IN
ISNS_1V5_S3_N
3.65K
1 1% 1/16W MF-LF 402 2 76
ISNS_1V5_S3_R_N
GAIN: 273X
C6044
2.2UF
10% 6.3V X5R 402
76 34
1 3
+IN -IN
V+ V2
R6064
ISNS_HDD_IOUT
1
226K
1% 1/16W MF-LF 402
DEBUG_ADC
ADC_CH5 DEBUG_ADC
1
47
R6061
IN
DEBUG_ADC
DEBUG_ADC 1
1
DEBUG_ADC
ISNS_HDD_N
412
1 1% 1/16W MF-LF 402 2 76
ISNS_HDD_R_N
GAIN: 845X
C6064
2.2UF
10% 6.3V X5R 402
C6042
470PF
10% 50V CERM 402
R6042
1M
1% 1/16W MF-LF 402 1
R6043
1M
1% 1/16W MF-LF 402 2
2 2
DEBUG_ADC
DEBUG_ADC
C6043
470PF
1 10% 50V CERM 402 2
DEBUG_ADC 1
1
DEBUG_ADC
C6062
470PF
10% 50V CERM 402
R6062
348K
1% 1/16W MF-LF 402 1
R6063
348K
1% 1/16W MF-LF 402 2
2 2
DEBUG_ADC
PLACEMENT_NOTE=PLACE NEAR D9710 OMIT
C6063
470PF
1 10% 50V CERM 402 2
47 8
1
XW6080
PPVOUT_S0_LCDBKLT
68 65 7
SM 1 2
C6050
0.1UF
20% 10V CERM 402
PPVOUT_S0_LCDBKLT_XW DEBUG_ADC
1
R6080
1M PLACEMENT_NOTE=PLACE RC NEAR U6000 DEBUG_ADC
A
76 68
V+
1% 1/16W MF-LF 2 402
R6082
1
SYNC_MASTER=K19_IMLB
PAGE TITLE
U6050
IN
ISNS_LCDBKLT_N ISNS_LCDBKLT_P
INA210
5
R6074
OUT
REF
6
ININ+
SC70
ISNS_LCDBKLT_IOUT
226K
1% 1/16W MF-LF 402
ADC_CH6 DEBUG_ADC
1
PPVOUT_S0_LCDBKLT_DIV DEBUG_ADC
47 1
226K
1% 1/16W MF-LF 402
ADC_CH7 DEBUG_ADC
1
DEBUG SENSORS AND ADC

DRAWING NUMBER SIZE
DEBUG_ADC
76 68
R6081
47.0K
1% 1/16W MF-LF 402
C6082
2.2UF
10% 6.3V X5R 402
R
IN
Apple Inc.
051-7982
REVISION
GAIN: 200X
C6074
2.2UF
10% 6.3V X5R 402
2
C.0.0
BRANCH PAGE
GND
2
60 OF 109
SHEET
DIVIDER: 1/22
38 8
=PP3V3_S5_ROM NO STUFF
C
R6150
73 38 21
R61901
10K
5% 1/16W MF-LF 402 2
R6100 1
3.3K
5% 1/16W MF-LF 402 2
R6101
3.3K
C6100
0.1UF
20% 10V CERM 402
VCC
2
5% 1/16W MF-LF 2 402
U6100
32MBIT
SOP
6
CRITICAL
C
R6152
5 73
IN
SPI_CLK_R
0
1 5% 1/16W MF-LF 402 2 73
SPI_CLK
SCLK OMIT
SI/SIO0
MX25L3205DM2I-12G
SPI_MOSI
0
1 5% 1/16W MF-LF 402 2
SPI_MOSI_R
IN
21 38 73

38
R6105
SO/SIO1
2 73
IN
SPI_MLB_CS_L
SPI_WP_L SPI_HOLD_L
3
7
CE* WP*/ACC HOLD*
SPI_MISO_R NO STUFF
0
5% 1/16W MF-LF 402
SPI_MISO
OUT
21 38 73
R6191
10K
5% 1/16W MF-LF 402
GND
4
MCP79 SPI Frequency Select
Frequency 31 MHz 42 MHz 25 MHz 1 MHz
SPI_MOSI 0 0 1 1
SPI_CLK 0 1 0 1
25MHz is selected with R5190 and R5191 Any of the 4 frequencies can be selected with R6190, R6191, R5190 and R5191
SYNC_MASTER=K24_MLB
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE
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61 OF 109
SHEET
AUDIO CODEC
APPLE P/N 353S2355
L6201
FERR-220-OHM
8
U6201 CONSUMES 33MA MAX. FROM 1.8V RAIL

=PP5V_S3_AUDIO PP1V8_S0_AUDIO_DIG
8 49 51 53 2
IN
=PP1V8_S0_AUDIO
VOLTAGE=1.8V MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM
1 0402
C6210
4.7UF
20% 4V X5R 402
C6211
0.1UF
10% 16V X5R 402
=PP3V3_S0_AUDIO PP4V5_AUDIO_ANALOG
8 49 53 54
D
53 51 49 49 7
D
IN
7 49
C6216 C6219
10UF
1
C6215
0.1UF
10% 16V X5R 402
1UF
C6214
0.1UF
2 10% 16V X5R 402
C6213
10UF
20% 6.3V X5R 603-1
GND_AUDIO_HP_AMP PP4V5_AUDIO_ANALOG
CRITICAL
24
46
25
20% 16V TANT-POLY 2012-LLP
C6218
2
C6217
10UF
20% 16V TANT-POLY 2012-LLP
0.1UF
10% 16V X5R 402
10% 10V X5R 402-1
CRITICAL
IN
C6221
10UF
1
C6220
10UF
20% 6.3V X5R 603-1
GND_AUDIO_HP_AMP GND_AUDIO_CODEC
49 51 53 49 50 53 54
R6210
2.67K
1% 1/16W MF-LF 402
20% 6.3V X5R 603-1
VBIAS_DAC CS4206_FP CS4206_FN
29 44 41
CRITICAL
VD VA_REF VA_HP VA VBIAS_DAC HPOUT_L VHP_FILT+ VHP_FILTU6201 HPOUT_R CS4206ACNZC HPREF

QFN
38 40 39 35 34 36 37 31 30 32 33
MIN_LINE_WIDTH=0.20MM MIN_LINE_WIDTH=0.20MM MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM
AUD_HP_PORT_L AUD_HP_PORT_R AUD_HP_PORT_REF TP_AUD_LO1_P_L TP_AUD_LO1_N_L AUD_LO1_P_R AUD_LO1_N_R AUD_LO2_P_L AUD_LO2_N_L AUD_LO2_P_R AUD_LO2_N_R
OUT OUT IN
51 51
53
GPIO0 = ANALOG SW CONTROL GPIO1 = HP AMP CONTROL GPIO3 = SPKR AMP SHDN CONTROL
53 51
OUT AUD_GPIO_0 OUT AUD_GPIO_1
2
12
52
TP_AUD_GPIO_2 NC AUD_GPIO_3 OUT

IN
14 15 13
GPIO0/DMIC_SDA1 GPIO1/DMIC_SDA2 /SPDIF_OUT2 GPIO2 GPIO3 SENSE_A
LINEOUT_L1+ LINEOUT_L1LINEOUT_R1+ LINEOUT_R1LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+ LINEOUT_R2-
NC NC
52 52
FR SPKR AMP. SIG. SOURCE
54
AUD_SENSE_A CS4206_FLYP CS4206_FLYC
52 52 52
LFT. SPKR AMP. SIG. SOURCE RT. SPKR AMP. SIG. SOURCE
45
C6222
2.2UF
20% 6.3V CERM 402-LF
C6223
2.2UF
20% 6.3V CERM 402-LF
43 42
FLYP FLYC FLYN

CRITICAL
52
MICBIAS
16
AUD_CODEC_MICBIAS
OUT
54
CS4206_FLYN
VL_HD VCOM
28
C
1
CS4206_VCOM
C
AUD_LI_P_L AUD_LI_REF AUD_LI_P_R
IN IN IN
50 50 50
VL_IF LINEIN_L+ LINEIN_CLINEIN_R+

21
22
73 21
IN IN
HDA_BIT_CLK HDA_SYNC
BITCLK
73 21
23
R6211
73 21
10
SYNC SDI SDO RESET* MICIN_L+ MICIN_LMICIN_R+ MICIN_R18 17 19 20
OUT
HDA_SDIN0
22
AUD_SDI_R
8 5 11
73 21 73 21
IN IN
NC
HDA_SDOUT HDA_RST_L TP_AUD_SPDIF_IN
5% 1/16W MF-LF 402
AUD_MIC_INP_L AUD_MIC_INN_L AUD_MIC_INP_R AUD_MIC_INN_R
IN IN IN IN
54 54 54
EXT MIC CODEC INPUT BI MIC CODEC INPUT
54
47
R6212
53
AUD_SPDIF_OUT_CHIP
48
SPDIF_IN SPDIF_OUT
VREF+_ADC
27
CS4206_VREF_ADC
NC NC
OUT
AUD_SPDIF_OUT
22
DMIC_SCL
TP_AUD_DMIC_CLK
5% 1/16W MF-LF 402
DGND THRM_PAD AGND

49 26 7 CRITICAL
C6224
1UF
20% 16V TANT 0603-SM
C6225
10UF
1
NOSTUFF
20% 2 16V POLY-TANT CASE-B2-SM
R6213
100K
5% 1/16W MF-LF 402
B
54 53 50 49
GND_AUDIO_CODEC
4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2456 NOTES ON CODEC I/O
L6200
FERR-220-OHM
53 51 49 8
U6200
TPS71745
6
MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM VOLTAGE=4.5V

1
IN
=PP5V_S3_AUDIO
1 0402
4V5_REG_IN 4V5_REG_EN
IN
EN
SON
OUT
NR/FB
PP4V5_AUDIO_ANALOG 4V5_NR
OUT
7 49
CRITICAL
4 3 5
1
R6200
54 53 49 8
IN
=PP3V3_S0_AUDIO
2.21K
1 1% 1/16W MF-LF 402 2
DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS
GND
1
NC
C6200
1UF
10% 10V X5R 402
C6201
1UF
10% 10V X5R 402
C6202
0.1UF
10% 16V X7R-CERM 402
C6203
1UF
10% 10V X5R 402
PLACE NEAR U6200
2 2
XW6200
SM 1 2
GND_AUDIO_CODEC
49 50 53 54
NOSTUFF
R6201
0
1 5% 1/16W MF-LF 402 2
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: CODEC/REGULATOR
DRAWING NUMBER SIZE
XW6201
SM 1 2
Apple Inc.
051-7982
REVISION
GND_AUDIO_HP_AMP
49 51 53
C.0.0
BRANCH PAGE
PLACE NEAR C6220 AND C6221

62 OF 109
SHEET
D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS) FC_HP = 3.6 HZ FC_LP = 43KHZ VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
R6301
53
C6301
2.2UF AUD_LI_L_DIV
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1 2
IN
AUD_LI_L
7.87K2
1% 1/16W MF-LF 402
AUD_LI_P_L
OUT
49
C
NOSTUFF
1
20% 10V X5R-CERM 402
C6303
820PF
R6302
21.5K CRITICAL
10% 2 50V CERM 402
1% 1/16W MF-LF 2 402
C6302
2.2UF
1 2 20% 10V X5R-CERM 402
53
IN
AUD_LI_GND
1
AUD_LI_REF
OUT
49
R6300
10 CRITICAL
1% 1/16W MF-LF 2 402
C6312
2.2UF
1 2
54 53 49
IN
GND_AUDIO_CODEC
1
NOSTUFF
C6313
820PF
1
20% 10V X5R-CERM 402
10% 2 50V CERM 402
R6312
21.5K
1% 1/16W MF-LF 2 402
B
C6311
2.2UF
1 2
CRITICAL
R6311
53
IN
AUD_LI_R
7.87K 2
1% 1/16W MF-LF 402
AUD_LI_R_DIV
AUD_LI_P_R
OUT
49
20% 10V X5R-CERM 402
A
PAGE TITLE
A
AUDIO: LINE INPUT FILTER
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

63 OF 109
SHEET
D
53 49 8
D
FERR-120-OHM-1.5A =PP5V_S3_AUDIO 1 2
0402-LF 1
L6520
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_PP5V_F
HP/LO AMP APN: 353S1637
C6520
0.1UF
C6521
10UF MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM
12 VDD CRITICAL
10% 2 16V X7R-CERM 402
20% 2 6.3V X5R 603
AUD_LO_AMP_OUTL
OUT
51 53
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

R6520
49
AUD_LO_AMP_INL_M
51 51
MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM
OUTL 11 OUTR 10 C1P 1 C1N 3
AUD_LO_AMP_INR_M AUD_GPIO_1_R
6 INL 8 INR
AUD_LO_AMP_OUTR
1
OUT
51 53
U6500
MAX9724A
TQFN
MAX9724_C1P
CRITICAL
1
R6523
2.21K
1
IN
AUD_GPIO_1
0
5% 1/16W MF-LF 402
5 SHDN* 13 THRM PAD 7 SGND 2 PGND 9 SVSS
C6524
1UF
51 49
4 PVSS
IN
AUD_HP_PORT_L
CRITICAL
MAX9724_C1N
10% 2 10V X5R 402
1% 1/16W MF-LF 2 402
R6524
2.21K
1% 1/16W MF-LF 2 402
C6500
0.1UF
10% 16V X7R-CERM 402
1 1 2
R6522
100K
NC
AUD_HP_ZOBEL_L
5% 1/16W MF-LF 2 402 1
MAX9724_SVSS
CRITICAL CRITICAL
1
C
53 51 49
R65001
39
5% 1/16W MF-LF 402
C6522
1UF
C6523
1UF
GND_AUDIO_HP_AMP
2
53 51 49
10% 10V 2 X5R 402
10% 2 10V X5R 402
IN
GND_AUDIO_HP_AMP
R65101
39
5% 1/16W MF-LF 402
MAX9724 GAIN/FILTER COMPONENTS AV_PB = -1V/V, FC_LPF = 35.2KHZ
NC
AUD_HP_ZOBEL_R
CRITICAL
CRITICAL
1
C6510
0.1UF
10% 16V X7R-CERM 402
51 49
C6530
330PF
1 5% 50V COG 402 2
IN
AUD_HP_PORT_R
R6531
1
13.7K2
1% 1/16W MF-LF 402
B
51 49
AUD_HP_PORT_L
IN
R6530
1
13.7K2
1% 1/16W MF-LF 402
AUD_LO_AMP_INL_M
51
AUD_LO_AMP_OUTL
OUT
51 53
AUD_HP_PORT_R
51 49
R6532
1
IN
13.7K2
1% 1/16W MF-LF 402
AUD_LO_AMP_INR_M
51
AUD_LO_AMP_OUTR
OUT
51 53
R6533
1
13.7K2
1% 1/16W MF-LF 402
CRITICAL
C6531
330PF
1 5% 50V COG 402 2
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: HEADPHONE FILTER

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

65 OF 109
SHEET
5
NO STUFF
4
C6612
DYNAMIC (SUB) AND PIEZO (SATELLITE) SPKR AMPLIFIERS SATELLITE SUB SUB GAIN SAT GAIN HPF FC = 775 HZ 80 HZ < HPF FC < 132 HZ 6DB (2V/V) 5.6DB (1.91V/V)
R6615
1
180PF
1 2 5% 50V CERM 402
26.1K2
1% 1/16W MF-LF 402
NO STUFF
C6613
180PF
1 2
D
R6616
1
5% 50V CERM 402
26.1K 2
1% 1/16W MF-LF 402
ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

52 8
APN:353S2630
C6607 1
1UF
CRITICAL 10% 10V X5R 2 402
=PP5V_S3_AUDIO_AMP
CRITICAL D3 A2
1
C6601
10UF
OMIT
PVDD
SVDD
49
IN
FERR-1000-OHM 1 2 SPKRAMP_INR_P AUD_LO2_P_R

0402
L6610
0.015UF
1 10% 16V X7R 402 2
C6610
LM48311_R_P_C 113.7K2
1% 1/16W MF-LF 402
R6613
U6610
LM48556TL
BGA
A3 IN+ B3 INC3 SD* CRITICAL OUT+ B2 OUT- A1 C1P C1N CPVSS C2 D1 C1
10% 16V 2 X5R-CERM 0805
R6612
1
SPKRAMP_R_P_OUT_R
OMIT
6.8
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_P_OUT 7 53 MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_N_OUT 7 53
LM48311_R_P LM48311_R_N
R6617
SPKRAMP_R_N_OUT_R LM48556_C1P_R
CRITICAL
1 1
6.8
5% 1/8W MF-LF 805
49
IN
C6611 FERR-1000-OHM R6614 0.015UF 2 SPKRAMP_INR_N 1 2 LM48311_R_N_C 113.7K2 AUD_LO2_N_R 1

0402
10% 16V X7R 402 1% 1/16W MF-LF 402
L6611
CRITICAL
C6604
4.7UF
5% 1/8W MF-LF 805
R6611
100K
PGND D2
SVSS B1
R6610
1
LM48556_VSS_R
CRITICAL
1
10% 10V 2 X5R 805
49
IN
AUD_GPIO_3
52
SPKRAMP_SHDN
52 8
5% 1/16W MF-LF 402
5% 1/16W MF-LF 2 402
LM48556_C1N_R
C6602
10UF
10% 16V 2 X5R-CERM 0805
C
CRITICAL
1
=PP5V_S3_AUDIO_AMP
APN:353S2621
C6608
CRITICAL
1
C6603
47UF
1UF
FERR-1000-OHM
49
L6620
0402
C6620
0.1UF
1 2
10% 10V X5R 2 402
B2 B1 PVDD VDD CRITICAL
U6620
LM48311
A1 IN+ C1 INA2 SD* PGND GND BGA OUTA A3 OUTB C3
20% 2 6.3V TANT1 2012-LLP
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_P_OUT 7 53 MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_N_OUT 7 53
IN
AUD_LO1_P_R
SPKRAMP_INSUB_P
FERR-1000-OHM
49
L6621
0402
10% 16V X5R 402
CRITICAL
LM48311_SUB_P LM48311_SUB_N
C6621
0.1UF
1 2
IN
AUD_LO1_N_R
SPKRAMP_INSUB_N
10% 16V X5R 402
B3
C2
52
SPKRAMP_SHDN
NO STUFF
C6634
180PF
1 2 5% 50V CERM 402
R6634
1
26.1K2
1% 1/16W MF-LF 402
B
180PF
1 2 5% 50V CERM 402
NO STUFF
C6635
R6635
1
26.1K2
1% 1/16W MF-LF 402

52 8
APN:353S2630
=PP5V_S3_AUDIO_AMP
CRITICAL D3 A2
1
C6605
10UF
OMIT
CRITICAL
C6609 1
1UF
PVDD
SVDD
FERR-1000-OHM
49
L6630
0402
C6630
SPKRAMP_INL_P 0.015UF
1 10% 16V X7R 402 2
R6631
LM48311_L_P_C
CRITICAL
1
IN
AUD_LO2_P_L
13.7K2
1% 1/16W MF-LF 402
LM48311_L_P
10% 10V X5R 2 402 A3 IN+ B3 INC3 SD*
U6630
LM48556TL
BGA
CRITICAL OUT+ B2 OUT- A1 C1P C1N CPVSS PGND D2 SVSS B1 C2 D1 C1
10% 16V 2 X5R-CERM 0805
R6630
1
SPKRAMP_L_P_OUT_R
OMIT
6.8
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_P_OUT 7 53 MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_N_OUT

7 53
R6633
SPKRAMP_L_N_OUT_R LM48556_C1P_L
CRITICAL
1 1
LM48311_L_N
6.8
5% 1/8W MF-LF 805
49
IN
AUD_LO2_N_L
A
52
C6631 FERR-1000-OHM R6632 0.015UF 13.7K2 1 2 SPKRAMP_INL_N 1 2 1 0402 LM48311_L_N_C 1% 10%

16V X7R 402 1/16W MF-LF 402
L6631
C6633
4.7UF
5% 1/8W MF-LF 805
LM48556_C1N_L LM48556_VSS_L
CRITICAL
1
10% 10V 2 X5R 805
SYNC_MASTER=AUDIO
PAGE TITLE
SPKRAMP_SHDN
AUDI0: SPEAKER AMP

DRAWING NUMBER SIZE
C6632
10UF
R
Apple Inc.
051-7982
REVISION
10% 16V 2 X5R-CERM 0805
C.0.0
BRANCH PAGE
66 OF 109
SHEET
AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX

54 49 8
=PP3V3_S0_AUDIO
AUD_SPDIF_OUT
IN
49
L6701
FERR-1000-OHM
1 2
HS_MIC_HI
OUT
54
0402
AUD_CONNJ1_MIC
L6702
FERR-1000-OHM
1 2
PLACE NEAR J6700

HS_MIC_LO
XW6702
OUT
54 SM
D
APN:514-0694
OMIT
0402
AUD_HP_PORT_REF
OUT
49
AUD_CONNJ1_SLEEVE
CRITICAL
L6703
FERR-120-OHM-1.5A
1 0402-LF 2
PLACE NEAR J6700

AUD_CONN_GND
XW6700
SM 1 2
GND_AUDIO_HP_AMP
49 51
J6700
AUDIO-JACK-TRANS-K83
F-RT-TH
CRITICAL
CRITICAL
L6704
FERR-220-OHM
1 2 0402
PLACE NEAR J6700
XW6701
AUD_CONN_L
BI
53 1 SM 2
8 2 1 7 6
AUD_LI_GND
50
AUD_CONNJ1_SLEEVEDET AUD_CONNJ1_TIP AUD_CONNJ1_RING
CRITICAL
L6705
FERR-220-OHM
1 2 0402
AUD_CONN_GND
5353
AUD_CONN_R
BI
53
AUDIO
PHS DETECT GND HP DETECT A - VIN B - VCC C - GND
9 10 11
CRITICAL
2 2
5 3 4
AUD_IP_PERPH_DET_JACK AUD_CONNJ1_TIPDET
L6706
FERR-1000-OHM
1
0402
AUD_IP_PERPH_DET
OUT
54
MIC CONNECTOR
APN:518S0520
CRITICAL
J6701
78171-0003
M-RT-SM 4
R6700
CRITICAL 1
10K
5% 1/16W MF-LF 402
AUD_J1_SLEEVEDET_R
2
OPERATING VOLTAGE 3.3
OUT
54 54 7 54 7 54 7
POF
1
DZ6705
12 13 14
2
DZ6703
6.8V-100PF
402
C6700
1UF
10%
6.3V
6.8V-100PF
402
SHELL
2
CRITICAL CRITICAL
CRITICAL
2 2
BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI
1 2 3
SHIELD PINS
CERM 402
DZ6704
6.8V-100PF
402
1 1
CRITICAL
1 1 2
R6701
1
DZ6702
6.8V-100PF
402
DZ6701
6.8V-100PF
402
DZ6700
6.8V-100PF
402
4.7
5% 1/16W MF-LF 402
AUD_J1_TIPDET_R
2
OUT
54
1
1
C6701
100PF
5%
50V
CERM 402
SPEAKER CONNECTORS
APN:518S0519
CRITICAL
J6702
78171-0002
M-RT-SM 3
52 7
R6724
51 49 8
IN IN
=PP5V_S3_AUDIO
0
5% 1/16W MF-LF 402
52 7
SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT
1 2
LEFT PIEZO
PP_MAX14504_VCC
C6703
100PF
1
C6702
100PF
5%
C6710
1UF
10% 10V X5R 402
5%
50V
R6716
AUD_LO_AMP_OUTL
51
CERM 402
2 50V CERM
402
0
1 5% 1/16W MF-LF 402 2
OUT
AUD_LO_AMP_OUTL_SWITCH
APN: 353S2536
A3 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
CRITICAL
J6703
78171-0002 AUD_CONN_L
BI 1
53 M-RT-SM
CRITICAL
B
AUD_LO_AMP_OUTR
51
L6707
2 SPKRAMP_SUB_P_OUT_CONN
0603
VCC
R6717
0
1 5% 1/16W MF-LF 402 2
FERR-120-OHM-3A
U6700
AUD_LO_AMP_OUTR_SWITCH
C4 C1 A4 A1
R6712
24K
B
DYN. FULL RANGE
OUT
MAX14504 NC1 NC2 NO1 NO2 CB NEG GND

B3 C3
52 7 52 7
IN IN
WLP CRITICAL
COM1
B4
5% 1/16W MF-LF 2 402
SPKRAMP_SUB_P_OUT SPKRAMP_SUB_N_OUT
1 2
SPKRAMP_SUB_N_OUT_CONN
CRITICAL
C6705
100PF
5%
50V
1C6704
L6708
2
0603
COM2
B1
100PF
5%
FERR-120-OHM-3A
R6718
50
AUD_LI_L
IN
0
1 5% 1/16W MF-LF 402 2
AUD_LI_L_SWITCH
C2
EN*
B2
CERM 2 402
2 CERM
402
50V
AUD_CONN_R
BI
53
SWITCH_CP
A2
J6704
CRITICAL
CRITICAL
78171-0003
L6709
2
0603
R6719
50
M-RT-SM 4
AUD_LI_R
IN
0
1 5% 1/16W MF-LF 402 2
AUD_LI_R_SWITCH
C6711
0.0033UF
10% 50V CERM 402
FERR-120-OHM-3A
R6713
24K
52 7 52 7
IN IN
5% 1/16W MF-LF 2 402
SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT
SPKRAMP_R_P_OUT_CONN SPKRAMP_R_N_OUT_CONN
1 2 3
RT. PIEZO
CRITICAL
R6720
AUD_GPIO_0
49
C6707
100PF
AUD_SWITCH_CTRL
5%
50V
C6706
100PF
5%
L6710
5 2
0603
FERR-120-OHM-3A
IN
0
5% 1/16W MF-LF 402
CERM 2 402
1
2 50V CERM
402
R6721
100K
5% 1/16W MF-LF 402
ANALOG AUDIO IO SWITCH

GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED
R6715
AUD_CONN_GND
53
0
1 5% 1/16W MF-LF 402 2
AUD_SWITCH_GND
SYNC_MASTER=AUDIO
GND STUFFING OPTIONS FOR CMOS SWITCH

54 50 49
R6714
0
1 5% 1/16W MF-LF 402 2
NOSTUFF
PAGE TITLE
GND_AUDIO_CODEC
R6727
0
1 5% 1/16W MF-LF 402 2
AUDIO: JACK
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

67 OF 109
SHEET
8
CODEC OUTPUT SIGNAL PATHS
FUNCTION HP/LINE OUT LINE IN SATELLITES SUB SPDIF OUT VOLUME 0X02 (2) 0X05 (5) 0X04 (4) 0X03 (3) N/A
7
CONVERTER 0X02 (2) 0X05 (5) 0X04 (4) 0X03 (03) 0X08 (8) PIN COMPLEX 0X09 (9,A) 0X0C (12) 0X0B (11) 0X0A (10) 0X10 (16)
6
MUTE CONTROL GPIO_0 AND GPIO_1 GPIO_0 AND GPIO_1 GPIO_3 GPIO_3 N/A DET ASSIGNMENT 0X09 (A) 0X09 (A) AND UI ELEMENT
3
PORT B LEFT(HEADSET MIC) HP=80HZ, LP=8.82KHZ
MIKEY
2
L6880
FERR-1000-OHM MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V
2
54 53 49 8
=PP3V3_S0_AUDIO
PP3V3_S0_HS_RX
N/A N/A 0X0D (B)
0402
DRC MIKEY APN:353S2256

1
CRITICAL MIKEY
CODEC INPUT SIGNAL PATHS

FUNCTION BUILT-IN MIC CONVERTER 0X06 (6) 0X06 (6) PIN COMPLEX 0X0D (13,B,RIGHT) 0X0D (13,V22,B,LEFT) VREF/ENABLE MIC_BIAS (80%) MCP79 GPIO_38 DET ASSIGNMENT N/A
PULLUPS ON MCP PAGE
C6880
1UF
10%
6.3V
AVDD
2
MIKEY
CERM 402
U6880
CD3275
DRC
D
49
HEADSET MIC
MCP79 GPIO_17 (PERIPH DETECT) MCP79 GPIO_4 (LOAD DETECT)

39
D
1 2 10 HS_MIC_BIAS MIKEY HS_SW_DET
1
IN BI OUT IN
=I2C_MIKEY_SCL =I2C_MIKEY_SDA AUD_I2C_INT_L AUD_IPHS_SWITCH_EN MIKEY
6 5 7 8
SCL SDA INT*
54 MICBIAS
PORT A DETECT (HEADPHONES)
PORT B DETECT(SPDIF DELEGATE)
39
DETECT BYPASS
CRITICAL
21
HS_RX_BP
C6882
2.2UF
20% 6.3V TANT 402
OUT AUD_SENSE_A
54 PP3V3_S0_AUDIO_F
1 1
19
ENABLE GND
9
4
THM
11 MIKEY
1
R6806
39.2K
1
R6805
20.0K
1% 1/16W MF-LF 402
R6880
100K
5% 1/16W MF-LF 402
APN:376S0613
R6801
300K
5% 1/16W MF-LF 402
AUD_OUTJACK_INSERT_L
2
1% 1/16W MF-LF 402
GND_AUDIO_CODEC MIKEY MIKEY

1 1
49 50 53 54
C6881
0.01UF
2
AUD_PORTA_DET_L
NC
AUD_PORTB_DET_L
NC
16V 402
10% CERM
Q6800
SSM6N15FEAPE
SOT563
R6881
1K
R6882
2.2K
5% 1/16W MF-LF 2 2 402
Q6801
SSM6N15FEAPE
SOT563
Q6801
SSM6N15FEAPE
SOT563
GND_AUDIO_CODEC
54 53 50 49
1%
R6802
47K
53
MIKEY CRITICAL
1/16W MF-LF 402
C6883
0.1UF
49
MIKEY
IN
AUD_J1_TIPDET_R
1 5% 1/16W MF-LF 402
AUD_J1_DET_RC
5 1
R6884
2.2K
4 5
C6801
0.1UF
2 20% CERM 10V 402
2 4
OUT AUD_MIC_INP_L
MIKEY CRITICAL
HS_MIC_HI_RC MIKEY
1
1 5% 1/16W
HS_MIC_HI
IN
53 54
C6886
0.1UF
49
10% 25V X5R 402
R6883
100K
5% 1/16W MF-LF 402
MIKEY
MF-LF 402
C6884
0.0082UF
2 10% X7R 25V 402
MIKEY
54 53 50 49 GND_AUDIO_CODEC
OUT AUD_MIC_INN_L
C6885
27PF
2 5% CERM 50V 402
R6803
220K
54 PP3V3_S0_AUDIO_F
1 1 5% 1/16W MF-LF 402 2
AUD_J1_SLEEVEDET_INV
10% 25V X5R 402 1
CRITICAL
XW6880
SM 2
CRITICAL
R6804
220K
5% 1/16W MF-LF 402
HS_MIC_LO
IN
53
C
2
Q6800
SSM6N15FEAPE
SOT563
54 53 AUD_J1_SLEEVEDET_R
PLACE NEAR C6886
C
R6851
2.4K
1 1% 1/16W MF 402-1 2
54 53
IN
AUD_J1_SLEEVEDET_R
1
PORT B RIGHT(BUILT-IN MIC)

C6802
0.01UF
2 10% 16V CERM 402 2
R6850
1
100
49
IN
AUD_CODEC_MICBIAS
1
1% 1/16W MF-LF 402
MIC_BIAS_FILT CRITICAL
C6852
2.2UF
20% 6.3V TANT 402
54 PP3V3_S0_AUDIO_F
VOLTAGE=3.3V
CRITICAL
L6862
FERR-1000-OHM =PP3V3_S0_AUDIO
1
0402
EXTRACTION NOTIFICATION CKT

49
C6850
0.1UF
L6850
FERR-1000-OHM BI_MIC_HI_F
1 2
OUT AUD_MIC_INP_R
CRITICAL
BI_MIC_HI
IN
7 53
54 53 49 8
IN
0402 10% 25V X5R 402 1
C6851
1 1
MIKEY
0.1UF
49
R6852
100K
5% 1/16W MF-LF 402
CRITICAL
CRITICAL
PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA
R6864
220K
5% 1/16W MF-LF 402
OUT AUD_MIC_INN_R
C6853
0.001UF
50V 402 10% CERM 2 2
C6854
27PF
5% CERM 50V 402
C6861
0.1UF
10V 402 20% CERM
MIKEY
1
R6865
100K
54 53 50 49 GND_AUDIO_CODEC 5% 1/16W MF-LF 402
10% 25V X5R 402
L6851
FERR-1000-OHM
1 2
R6853
2.4K
1
1% 1/16W MF 402-1
BI_MIC_LO_F
2
BI_MIC_LO
IN
7 53
0402
1MIKEY
R6862
300K
5% 1/16W MF-LF 402
MIKEY
Q6802
SSM6N15FEAPE
SOT563
2 6
MIKEY
XW6851
SM 1 2
R6861
0
AUD_IP_PERIPHERAL_DET
5% 1/16W MF-LF 402
BI_MIC_SHIELD
AUD_PERPH_DET_R
OUT
17
IN
7 53
B
53 AUD_IP_PERPH_DET
PLACE NEAR J6701
MIKEY
2
HP=80HZ
MIKEY
Q6802
1
SSM6N15FEAPE
SOT563
R6860
15K
1 5% 1/16W MF-LF 402 2
PERPH_DET_FILT
MIKEY
1
C6860
0.1UF
AUD_J1_TIPDET_INV
20% 10V CERM 402
MIKEY MIC LOAD DET CKT

PP3V3_S0_AUDIO_F
54 54
HS_MIC_BIAS
MIKEY_LOAD_DET
1
MIKEY_LOAD_DET
CRITICAL
MIKEY_LOAD_DET
1
MIKEY_LOAD_DET
1
R6870
2.21K
A1
VCC 54 53
C6872
0.1UF
R6872
100K
MIKEY_LOAD_DET
U6870
MAX9028EBT+
UCSP
VEE1
1% 1/16W MF-LF 2 402
HS_MIC_HI
B3 B1
10% 16V 2 X5R 402
1% 1/16W MF-LF 2 402
R6873
0
5% 1/16W MF-LF 402
A2 B2
MIC_LOAD_COMP_OUT 1
2 MIKEY_MIC_LOAD_DET
OUT
COMP. TRIP PT. = 2.64V MIKEY_LOAD_DET

1
VEE0
HS_MIC_BIAS_COMP
A3 MIKEY_LOAD_DET
1
R6871
100K
MIKEY_LOAD_DET
1
C6870
27PF
C6871
27PF
OUTPUT HIGH WHEN MIC BIAS LOADED OUTPUT LOW WHEN MIC BIAS UNLOADED
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: JACK TRANSLATORS

DRAWING NUMBER SIZE
1% 1/16W MF-LF 2 402
5% 2 50V CERM 402
5% 2 50V CERM 402

R
Apple Inc.
051-7982
REVISION
GND_AUDIO_CODEC
54 53 50 49
C.0.0
BRANCH PAGE
68 OF 109
SHEET
8
MagSafe DC Power Jack
CRITICAL
J6900
78048-0573
M-RT-SM 1 2 3 7 PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V 1
CRITICAL
F6905
6AMP-24V
1 2
=PP18V5_DCIN_CONN
8 55
1206-1
4 5 7 ADAPTER_SENSE
1
R6928
0
2 2 5% 1/16W MF-LF 402
C6905
0.01UF
20% 50V CERM 603
=PP3V42_G3H_ONEWIRE
R6929
2
SMC_BC_ACOK_VCC
5
SOT665 TC7SZ08AFEAPE
2
518S0656
2.0K
402 MF-LF 1/16W 5%
VCC
ONEWIRE_PU
1
A
4
SMC_BC_ACOK
36 37
U6901
B
3 1 1
U6900
MAX9940
SC70-5 4 INT
C6908
0.1UF
20% 10V CERM 402
PLACEMENT_NOTE=PLACE NEAR U6901
36
BI
SYS_ONEWIRE
EXT 5
2
GND
2
NC
3 NC
1-Wire OverVoltage Protection

ADAPTER_SENSE_R
C
516S0787
C
J6955
ASP-146700-03
F-ST-SM
8
=PP3V42_G3H_HALL
1 3 5
2 4 6
R6905
47
55 8
D6905
HN2D01JEAPE
2
=PP18V5_DCIN_CONN
1 5% 1/8W MF-LF 805
PPDCIN_S5_P3V42G3H
SOT665 5
3.425V "G3Hot" Supply

R6961 Supply needs to guarantee 3.31V delivered to SMC VRef generator
0
7 SMC_LID_R
1
5% MF-LF
2
402
SMC_LID
36 37 44
1/16W
NOSTUFF
1
56 55 7
BATT_POS_F
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 mm VOLTAGE=12.6V
PPVIN_G3H_P3V42G3H
C6955
0.001UF
10% 50V CERM 402
NC
NC
P3V42G3H_BOOST
DIDT=TRUE 2
C6990
10UF
10% 25V X5R 805
C6994
VIN
2
BOOST
0.22uF
20% 6.3V X5R 402 2
CRITICAL
U6990
LT3470A
8
L6995
33UH-20%-0.44A-0.455OHM
=PP3V42_G3H_REG
SHDN* NC
DFN CRITICAL
SW
BIAS
4 2
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE
1 D52LC-SM
HALL EFFECT CONNECTOR
Vout = 3.425V 250MA MAX OUTPUT <Ra>
NC
GND
5
FB THRM PAD
9
1
1
C6995
22pF
5% 50V CERM 402
R6995
348K
1% 1/16W MF-LF 402
(Switcher limit)
CRITICAL
2 1
C6999
22UF
20% 6.3V CERM 805
P3V42G3H_FB
<Rb>
R6996
200K
1% 1/16W MF-LF 402 1
Vout = 1.25V * (1 + Ra / Rb) CRITICAL
J6950
BAT-K24
M-RT-TH
BATTERY CONNECTOR
56 55 7 BATT_POS_F 7 SYS_DETECT_L
P1 P2 P3 P4 P5 P6 P7 P8 P9 SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN
1 2 3 4 5 6 7 8 9 10 11 12 13
=SMBUS_BATT_SCL =SMBUS_BATT_SDA
39 39
CRITICAL
D6950
1 2
RCLAMP2402B
SC-75
R6950
10K
5% 1/16W MF-LF 402
C6950
0.1UF
10% 25V X5R 402
SYNC_MASTER=K24_MLB
PAGE TITLE
DC-In & Battery Connectors

2
NOSTUFF
DRAWING NUMBER
SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE
NOTICE OF PROPRIETARY PROPERTY: 518-0359

69 OF 109
SHEET
PBUS SUPPLY / BATTERY CHARGER

Q7001
HAT1128R01 SOI
Q7000
8
=PP18V5_G3H_CHGR
3
HAT1128R01 SOI
CRITICAL
8
PPVDCIN_G3H_PRE2
CRITICAL
D4 D3 D2 D1 S3 S2 S1 GATE
3 2 1
7
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
PPVDCIN_G3H_PRE
8 7 6 5
6 5
D
2 1
S3 S2 S1 GATE 4
D4 D3 D2 D1
D7010
1SS418
SOD-723-HF
D
R7099
1
100K
5% 1/16W MF-LF 402
R7098 C7063
0.1UF
10% 25V X5R 402
2 1
=PP3V42_G3H_CHGR
56 8
4
2
100K
5% 1/16W MF-LF 402
C7060
0.1UF
10% 25V X5R 402
CHGR_LOWCURRENT_GATE_R
R7060
R7062
5% 1/16W MF-LF 402
R7001
R7010
CHGR_DCIN
56
57.6K
1% 1/16W MF-LF 402 2
56 41
1
CHGR_SGATE
62K
1 5% 1/16W MF-LF 402 2
2 5
CHGR_AMON
62K
30.1K
1% 1/16W MF-LF 402
VCC
4
CHGR_LOWCURRENT_GATE
R7061
1.82K
1% 1/16W MF-LF 402
3 CHGR_LOWCURRENT_REF
GND
2
CRITICAL
U7060
TL331
SOT23-5
R7023
(CHGR_ACIN)
C7010
0.1UF
10% 25V X5R 402
56 1
CHGR_VDD
CHGR_VDDP
1
10
5% 1/16W MF-LF 402 1 2
R7040 C7041
2 56 8
4.7
C7040
1UF
10% 10V X5R 402-1
XW7020
1 2
PLACEMENT_NOT=PLACE XW7020 ON PAD OF R7020 PLACEMENT_NOT=PLACE XW7021 ON PAD OF R7020 SM OMIT CRITICAL
=PP3V42_G3H_CHGR
1UF
R7011
9.31K
1% 1/16W MF-LF 402
C7047
1UF
10% 10V X5R 402-1
10% 10V X5R 402-1 19
5% 1/16W MF-LF 402
C7024
0.047UF
10% 10V CERM 402
CHGR_CSIP_XW7020
R7021
2 5% 1/16W MF-LF 402 1 2
R7020
0.02
20
10
OMIT
XW7021
SM
2
12
VDD
39 39
VDDP AGATE CSIP CSIN BGATE DCIN BOOT UGATE PHASE LGATE
TRKL*
1 28 27 16 2 25 24 23 21
13
0.5% 1W MF 2 0612-1 1
PP18V5_S5_CHGR_SW_R CRITICAL CRITICAL

1
PLACEMENT_NOTE=PLACE C7027 ACROSS PIN 5 OF Q7020 AND PINS 1/2/3 OF Q7021
C
CHGR_ACIN
=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA
11 10
VHST SCL CRITICAL SDA
CHGR_AGATE CHGR_CSIP CHGR_CSIN

56 CHGR_BGATE CHGR_DCIN 56
CHGR_CSIN_XW7021
1
C7020
22UF
20% 25V POLY-TANT CASE-D2-SM
C7021
22UF
20% 25V POLY-TANT CASE-D2-SM
C7022
1UF
10% 25V X5R 603-1
C7023
1UF
10% 25V X5R 603-1
C7027
0.001UF
20% 50V CERM 402
C7061
0.1UF
10% 25V X5R 402
C7062
0.1UF
10% 25V X5R 402 GND_CHGR_SGND 5
56
U7000
NC
CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSOP CHGR_CSON
4 3 QFN
ISL6258AHRTZ
VREF ACIN ICOMP VCOMP VNEG CSOP CSON THRM_PAD
2
DIDT=TRUE
CRITICAL
5 7 8 18 17
CHGR_BOOT CHGR_UGATE CHGR_PHASE CHGR_LGATE TP_CHGR_TRKL CHGR_AMON 41 56 CHGR_BMON 41 =CHGR_ACOK 37
Q7020
4
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
RJK0305DPB
LFPAK-HF
CRITICAL
1 2
TO SYSTEM
=PPBUS_G3H
8
C7042
0.033UF
10% 16V X5R 402
DIDT=TRUE
C7025
0.1UF
10% 25V X5R 402
CRITICAL
R7008
CRITICAL
2 1 2 3
F7000
7AMP
1206
0.01
2 0.5% 1W MF 0612-1
R7045 1
56.2K
1% 1/16W MF-LF 402 2 CHGR_VCOMP_R
C7043
1UF
1 10% 16V X5R 402 2
AGND
PGND
C7044
0.01UF
10% 16V CERM 402
AMON BMON ACOK
9 15 14
L7000
1
PPVBAT_G3H_CHGR_REG
1 3
2 4
1
PPVBAT_G3H_CHGR_OUT
56
DIDT=TRUE
4.7UH-9.5A
5
IHLP4040DZ-SM
29
26
22
C7028
0.001UF
20% 50V CERM 402
CRITICAL
1
C7011
1UF
10% 25V X5R 603-1
C7008
33UF
20% 16V POLY-TANT CASED2E-SM
C7045
56
GND_CHGR_SGND
0.001UF
10% 50V CERM 402 2
CHGR_PIN6 CHGR_PIN26 OMIT

1 2
56
4
56
DIDT=TRUE
CRITICAL
R7046 1
3.01K
1% 1/16W MF-LF 402
XW7000
SM
C7026
0.001UF
Q7021
RJK0305DPB
LFPAK-HF
1 2 3
PWM FREQ. = 400 kHz MAX CURRENT = 7A

(??? limited)
PLACEMENT_NOT=PLACE XW7000 CLOSE TO U7000

2 56
10% 50V 2 X7R 402
GND_CHGR_SGND
1
CHGR_VNEG_R
R7031
2.2
2 5% 1/16W MF-LF 402 1 76
(CHGR_CSOP)
C7046
470PF
10% 50V CERM 402
CHGR_CSO_R_P
R7047
0
2 5% 1/16W MF-LF 402 76
CHGR_CSO_R_N
(CHGR_CSON)
(CHGR_CSO_R_N)
AMON PULLDOWN LOGIC

56 41
CHGR_AMON
56 8
=PP3V42_G3H_CHGR
Q7070
R7074
1M
1
SSM6N15FEAPE D
SOT563
NOSTUFF
R7075
5% 1/16W MF-LF 402
56
CHGR_PIN26 OMIT
1 2
BATTERY CHARGE LIMITING FETS

Q7050
GND_CHGR_SGND
56
5% 1/16W MF-LF 402 2 2
1M
SI7137DP
SO-8
56
PPVBAT_G3H_CHGR_OUT
1
XW7052
SM
PLACEMENT_NOT=PLACE XW7052 CLOSE TO U7000 D
CRITICAL
BATT_POS_F
5 7 55
CHGR_VDD_L
56
C7050
0.01uF
10% 16V CERM 402
C7051
0.1UF
10% 16V X5R 402
CHGR_PIN6
2
Q7070
A
56 CHGR_VDD
SSM6N15FEAPE
SOT563
OMIT
1 2
GND_CHGR_SGND
56
SYNC_MASTER=K24_MLB
PAGE TITLE
XW7054
SM
CHGR_BGATE
56
R7073
1K
PLACEMENT_NOT=PLACE XW7054 CLOSE TO U7000
PBUS Supply/Battery Charger

DRAWING NUMBER SIZE
5% 1/16W MF-LF 402 2
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

CHGR_VDD_R
70 OF 109
SHEET
8
- COPY THIS PAGE FROM K36 CSA.76
5V S3/3.3V S5 POWER SUPPLY

D
VOUT = (2 * RA / RB) + 2 VOUT = (2 * RC / RD) + 2
ROUTING NOTE: Place XW7203 by Pin1 OF L7260.
OMIT
XW7203
SM
2 1
<RA> <RB> <RD> <RC> R7267 R7268 R7269 R7270 15.0K 10K 10K 6.49K
1% 1/16W MF-LF 402
1
OMIT
1% 1/16W MF-LF 402

1
1% 1/16W MF-LF 402

1
1% 1/16W MF-LF 402

1
XW7204
SM
3V3S5_VFB_R7270
2 1
ROUTING NOTE: Place XW7204 by Pin 2 of L7220.
5V_S3_VFB_XW7203
PLACEMENT_NOT=PLACE XW7203 BY PIN 1 OF L7260

57
PLACEMENT_NOT=PLACE XW7204 BY PIN 2 OF L7220
GND_5V3V3S5_SGND
OMIT
XW7205
SM
2 1
ROUTING NOTE: Place XW7205 by C7252.
C
57 8
=PPVIN_S3_5VS3
ROUTING NOTE: Place XW7202 by C7292.
OMIT
PLACEMENT_NOT=PLACE XW7205 BY C7252
XW7202
SM
2 1
C7272
1UF
10% 25V 2 X5R 603-1

PLACEMENT_NOTE=PLACE C7230 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7220
57 8
=PPVIN_S3_5VS3
CRITICAL 1 C7280 68UF
20% 2 16V ELEC C6-SM
5V3V3S5_REG3 5VS3_3V3S5_VREF
=PPVIN_S5_3V3S5
1
EMI request
1
C7232
50V CERM 402
0.001UF 20%
C7281 1UF
CRITICAL
1
C7260
0.1UF 10%
D
CRITICAL
16V X5R 402
2 10V CERM
0.22UF 10%
402
10% 2 25V X5R 603-1
20% 2 16V POLY B1A-SM
16
C7282 39UF-0.027OHM
C7271
4 TONSEL
20% 2 6.3V X5R 603

VREG3 8 VREG5 17 5V3V3S5_REG5
C7270 10UF C7220 0.1UF

10% 16V X5R 402
EMI request
1
CRITICAL C7230 C7241 C7240 0.001UF 1UF 20% 39UF-0.027OHM

1 1
VIN 14 SKIPSEL
VREF
50V CERM 402
10% 2 25V X5R 603-1
Q7260
SIS426DN
PWRPK-12128
2
G S
DIDT=TRUE
5V_S3_VBST
22 VBST1 CRITICAL VBST2 9 21 DRVH1 20 LL1 19 DRVL1 24 VO1 2 VFB1 1 ENTRIP1
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 5V_S3_DRVH MIN_LINE_WIDTH=0.6 MM DIDT=TRUE MIN_NECK_WIDTH=0.2 MM 5V_S3_LL

DIDT=TRUE DIDT=TRUE
U7200
QFN TPS51125
3V3S5_VBST
1
DIDT=TRUE
CRITICAL
DRVH2 10 LL2 11 DRVL2 12 VO2 7 VFB2 5
MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 3V3S5_DRVH MIN_LINE_WIDTH=0.6 MM 3V3S5_LL MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE 1
Q7220
SIZ700DT
POWERPAK-6X3.7
8
PWM FREQ. = 300 KHZ MAX CURRENT = 10A

8
4.7UH-13A-15MOHM
1 2 PCMB104E4R7-SM 1
L7260
5V_S3_DRVL
3V3S5_DRVL
4.7UH-10A
EMI request
1 PCMC063T-SM 2 1
L7220
NO STUFF
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 5V_S3_VO1
DIDT=TRUE
3V3S5V02VO2
6
NO STUFF
CRITICAL =PP5V_S3_REG
VOLTAGE=5V EMI request
R7294
2.2
D
5% 1/16W MF-LF 402
5V_S3_VFB
3V3S5_VFB 3V3S5_ENTRIP NC
4 5
R7295
2.2
5% 1/16W MF-LF 402
CRITICAL =PP3V3_S5_REG
EMI request
1
8
B
VOLTAGE=3.3V MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm
CRITICAL
CRITICAL
1
CRITICAL
Q7261
5V_S3_ENTRIP
ENTRIP2 6 VCLK 18
C7233
0.001UF
C7290 10UF
20% 603
C7291 1
15
25
20% 2 50V CERM 402
2 6.3V X5R
150UF-.025-OHM 20% 6.3V TANT 2 CASE-B2-SM
C7292 1
5V_S3_LL_SNUBBER EMI request NO STUFF

1
SIS426DN
PWRPK-12128
CRITICAL
6.3V TANT 2 CASE-B2-SM
3V3S5_LL_SNUBBER
150UF-.025-OHM
20% 6.3V TANT 2 CASE-B2-SM
G S
R7271
1% 1/16W MF-LF 402
PGOOD 23 EN0 13 GND THRM_PAD
C7294
100PF
5% 50V 402
75K
C7273
10UF 20%
603
R7272
1% 1/16W MF-LF 402
75K
EMI request NO STUFF

1
C7231 C7252
50V CERM 402
0.001UF 1 150UF-.025-OHM 20% 20%
C7250 10UF
20% 603
C7295
100PF
5% 50V 402
2 CERM
2 6.3V X5R
2 6.3V X5R
2 CERM
OMIT
57
GND_5V3V3S5_SGND
Q7221
SSM6N15FEAPE
SOT563
63 36 7
R7273
SMC_PM_G2_EN
1
XW7201 SM
PLACEMENT_NOT=PLACE XW7201 BETWEEN PIN 15 AND PIN 25 OF U7200 5V3V3_REG_EN
100K 2
5% 1/16W MF-LF 402
P5V3V3_PGOOD
63
ROUTING NOTE:
=P5VS3_EN_L
63
IN
Q7221
D
3
Place XW7201 between Pin 15 and Pin 25 of U7200.
SSM6N15FEAPE
SOT563
A
63
=P3V3S5_EN_L 5
IN
A
PAGE TITLE
5V/3.3V SUPPLY
DRAWING NUMBER SIZE
Apple Inc.
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

72 OF 109
SHEET
1.5V/0.75V(DDR3) POWER SUPPLY

D
VOUT = 0.75V * (1 + RA / RB) NO STUFF <RB> 1 2 1 2 1V5S3_VDDQSET R7322 <RA> C7303 20K 0.1% 100PF
1/16W MF 402
26 8
=PPVTT_S3_DDR_BUF
R7321
20.0K
1% 1/16W MF-LF 402
5% 50V CERM 402
C7340
0.033UF
10% 16V X5R 402
20% 2 6.3V X5R 603
C7301 10UF
XW7304
1 2
1V5S3_V5FILT_XW 1
1V5S3_V5FILT
=PP5V_S3_1V5S30V75S0
1 2
OMIT
SM
1UF
C7300
1V5S3_VTTSNS
10% 10V X5R 402-1
5% 1/16W MF-LF 402
4.7
R7307
C7302
20% 6.3V X5R 603
10UF
PLACEMENT_NOTE=PLACE XW7301 BY L7320 OMIT
=PP0V75_S0_REG
8
XW7301 SM
1V5S3_VDDQSNS
1 2
ROUTING NOTE:
Place XW7301 by L7320.
ISNS_1V5_S3_P OUT ISNS_1V5_S3_N OUT

1
47 76
47 76
1V5S3_VBST
DIDT=TRUE
1% 1/16W MF-LF 2 402

64 25
R7310 10.7K
VDDQSET VTTREF VLDOIN VTT V5FILT
VBST V5IN VDDQSNS VTTSNS
5% 1/16W MF-LF 402
R7300 C7309 1 0.1uF
5
DIDT=TRUE
=PPVIN_S5_1V5S30V75S0 CRITICAL CRITICAL 1 C7332 C7331 C7345 1UF

8
1V5S3_VBST_RC
23
24
14
22
15
39UF-0.027OHM
D 4 G
CRITICAL Q7320
CSD58858Q3
3.3X3.3-QFN
10% 2 25V X5R 603-1
39UF-0.027OHM
C7333 0.001UF
20% 50V CERM 402
CRITICAL
=DDRVTT_EN
10 S3 11 S5
PGOOD
13 21 1V5S3_DRVH 20 1V5S3_LL 19 1V5S3_DRVL 4 7 NC 12 NC
CRITICAL
16V 10% X5R 402
CRITICAL
1.0UH-13A-5.6M-OHM SM-IHLP-1
PLACEMENT_NOTE=PLACE C7333 ACROSS Q7320 PWR AND Q7321 GND
S 1 2 3
L7320
1
XW7303
63
=DDRREG_EN
6 COMP SM
TPS51116
QFN
DRVL MODE NC0 NC1 VTTGND
U7300 SYM (1 OF 2)
DRVH LL
DIDT=TRUE MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm DIDT=TRUE
NO STUFF
2 PP1V5_S3_REG_R
2 4
1 3
VOLTAGE=1.5V
=PP1V5_S3_REG CRITICAL
8
OMIT
1V5S3_CS
ROUTING NOTE:
16 CS ROUTING NOTE:
CONNECT CS_GND TO Q7321 PIN1,2.3 USING KEVIN CONNECTION. THRM_PAD CS_GND GND PGND
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm 5
DIDT=TRUE
R7390
2.2 EMI request
5% 1/16W MF-LF 402
R7350
0.001
MF-1 0612 2 1
C7343
330UF
1% PLACE NEXT TO L7320 1W
D 4 G
Place XW7303 by C7308.
CRITICAL Q7321
CSD58858Q3
3.3X3.3-QFN
1V5S3_LL_SNUBBER
C7344 C7342 0.001UF 330UF

20% 50V CERM 402
20% 2 6.3V X5R 603
C7341 10UF
NO STUFF
MAX CURRENT = 13A PWM FREQ. = 400 KHZ
C7307
22UF 20%
C7308
22UF 20%
S 1 2 3
C7390
100PF
5% 402
PLACE CLOSE TO L7320
CRITICAL
25
17
18
2 6.3V X5R-CERM-1 603
2 6.3V X5R-CERM-1 603
2 50V CERM
EMI request OMIT
B
GND_1V5S3_SGND
ROUTING NOTE: PUT 6 VIAS UNDER THE THERMAL PAD
GND_1V5S3_CSGND
2 ROUTING NOTE:
1
DDRREG_PGOOD
R7399 100K
5% 1/16W MF-LF 402 2
B
63
XW7300 SM
OMIT
1 2
=PP3V3_S3_PDCISENS
XW7302 SM
ROUTING NOTE:
Place XW7302 by Q7321.
PLACEMENT_NOT=PLACE XW7300 BETWEEN PIN 3 AND PIN 25 OF U7300 PLACEMENT_NOT=PLACE XW7302 BY Q7321
STATE S0 S3 S5/G3HOT
PM_SLP_S4_L HIGH HIGH LOW
PM_SLP_S3_L HIGH LOW LOW
PP1V5_S3 1.5V 1.5V 0.0V
PP0V75_S0 0.75V 0.0V 0.0V
A
PAGE TITLE
A
1.5V/0.75V DDR3 SUPPLY
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

73 OF 109
SHEET
=PP5V_S0_CPU_IMVP
1 2 1
59 8
=PPVIN_S5_CPU_IMVP
PLACEMENT_NOTE=PLACE C7419 ACROSS PINS 1/2/5/6 OF Q7400 AND PINS 3/4 OF Q7401
PP5V_S0_IMVP6_VDD
C7426
1UF
10% 6.3V CERM 402
R7412
10
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

1
Q7400 IRF6710
S1
CRITICAL
1
1 2 5
CRITICAL
1
C7409
33UF
C7417
33UF
C7418
1UF
10% 25V X5R 603-1
C7419
0.001UF
20% 50V CERM 402
C7435
10UF
20% 6.3V X5R 603
DPRSLPVR
DPRSTP*
PSI*
OPERATION MODE
DIDT=TRUE

LOAD LINE SLOPE = -2.1 MV/A
D
59 8
5% 1/16W MF-LF 402
0 0 1 1
1 1 0 0
1 2
1 0 1 0
IMVP6_BOOT1_RC
DIDT=TRUE
2-PHASE CCM
4
G S
2 1 2
D
8
=PPVIN_S5_CPU_IMVP
PPVIN_S5_IMVP6_VIN
1
1-PHASE CCM 1-PHASE DCM

DIDT=TRUE
R7420
10
C7496
0.01UF
10% 16V CERM 402
CRITICAL (IMVP6_PHASE1)
CRITICAL L7400 0.36UH-20%-40A-0.00075OHM

1 PIMA104E-SM 2
=PPVCORE_S0_CPU_REG
70 21
IN
PM_DPRSLPVR
5% 1/16W MF-LF 402
1-PHASE DCM
PIMA104E-R36MN0R755 DCR=0.75MOHM
1
DIDT=TRUE
=PP3V3_S0_IMVP
PP3V3_S0_IMVP6_3V3
C7430 R7421
10
5% 1/16W MF-LF 402
R7424
1
D
5
CRITICAL
PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7400
C7420
0.001UF
20% 50V CERM 402
0.1uF
10% 16V X5R 402
R7447
2.0K
0
5% 1/16W MF-LF 402 1 20 22 31 2
Q7401
G S
IMVP6_BOOT2_RC
DIDT=TRUE
IRF6795
DIRECTFET-MX 3 4
OMIT
OMIT
59
GND_IMVP6_SGND
5% 1/16W MF-LF 2 402
XW7401
SM
XW7402
SM
1
PPVCORE_S0_CPU_XW
VIN
70 11 70 11 70 11 1 70 11
VDD
PVCC BOOT1
36 26
59 59
DIDT=TRUE
R7425
0
5% 1/16W MF-LF 402 1
C7427
0.1UF
10% 16V 2 X5R 402
C7415
1
0.1UF
10% 16V
IMVP6_PHASE1_XW
CPU_VID<6> CPU_VID<5> CPU_VID<4> CPU_VID<3> CPU_VID<2> CPU_VID<1> CPU_VID<0>
43 42 41 40 39 38 37
VID6
IMVP6_BOOT1 IMVP6_BOOT2
DIDT=TRUE
CRITICAL
VID5 VID4 VID3 VID2 VID1 VID0
U7400
QFN
BOOT2
R7400
10K
1% 1/16W MF-LF 402
C7403
0.22uF
10% 6.3V CERM-X5R 402
R7404
1
5% 1/16W MF-LF 402
X5R 402
ISL9504BCRZ
UGATE1 PHASE1 LGATE1
35 34 32
59
IMVP6_UGATE1 IMVP6_PHASE1 IMVP6_LGATE1 (GND)
R7445
499
70 11 70 11 70 11
59
1% 1/16W MF-LF 2 402
59
70
IN CPU_DPRSTP_L IMVP_DPRSLPVR
70 14 10 10
46 45 2 3
PGND1 33 ISEN1
24
59
DPRSTP* DPRSLPVR PSI* IMON
IMVP6_ISEN1 IMVP6_UGATE2
59 8
(IMVP6_ISEN1)
IN
CPU_PSI_L
IMVP6_IMON OUT 41
UGATE2 PHASE2
27 28 30 29
C
PLACEMENT_NOTE=PLACE C7422 ACROSS PINS 1/2/5/6 OF Q7402 AND PINS 3/4 OF Q7403
59
48
59
IMVP6_PHASE2 IMVP6_LGATE2 (GND)
3V3 CLK_EN* VR_ON PGND2 PGOOD VR_TT* ISEN2 NTC VSUM 19 OCSET 8 VO DROOP
18 16
59 59 59 59
(NC)
FROM SMC
1 2
9 36 25
47 44 1 5 6
LGATE2
59
CRITICAL
=PPVIN_S5_CPU_IMVP CRITICAL CRITICAL

1
IN OUT
IMVP_VR_ON VR_PWRGOOD_DELAY
Q7402
IRF6710 S1
D
C7401
33UF
C7408
33UF
C74111
1UF
10% 25V X5R 603-1
2
C7422
0.001UF
20% 50V CERM 402
1
1 2 5
C7405
0.015uF
10% 16V X7R 402
R7408
147K
1% 1/16W MF-LF 402 1 2
IMVP6_VR_TT IMVP6_NTC
59
23
59
IMVP6_ISEN2 IMVP6_VSUM IMVP6_OCSET
DIDT=TRUE
20% 16V 2 POLY-TANT CASED2E-SM
R7401
3.65K
1% 1/16W MF-LF 402
4 3
IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
7 4
G S
SOFT RBIAS
59
IMVP6_VO
IMVP6_DROOP IMVP6_DFB
1 1 2
NO STUFF
0.36UH-20%-40A-0.00075OHM
(IMVP6_PHASE2)
DIDT=TRUE
L7401
C7416
0.001UF
10% 50V 1 2
CRITICAL
1 PIMA104E-SM
PLACEMENT_NOTE=PLACE C7423 CLOSE TO PIN 2 OF L7401
59
13
VDIFF DFB 17
59
C7406
0.001UF
10% 50V CERM 402
R7413
1 2
59 59 59 59
12 11 10 9
FB2 FB COMP VW VSEN

14
1K
1% 1/16W MF-LF 402
R7418
1K
1% 1/16W MF-LF 402
R7417
5.36K
1% 1/16W MF-LF 402
C7429
180pF
1 5% 50V CERM 402 2
CERM 402
OMIT
1 2 6 7
PIMA104E-R36MN0R755 DCR=0.75MOHM
C7423
0.001UF
20% 50V CERM 402
XW7403
SM
OMIT
RTN 15
R7409
1K
1% 1/16W MF-LF 402 1
C7431
0.001UF 1 2
2
R7416
13.7K
1% 1/16W MF-LF 402
XW7404
1
SM
DIDT=TRUE
D
5
CRITICAL
IMVP6_VSEN
IMVP6_RTN
25
NC GND
21
G S
3 4
IMVP6_PHASE2_XW
IMVP6_VDIFF_RC
Q7403
IRF6795
DIRECTFET-MX
1
1 2 1 2
PPVCORE_S0_CPU_XW_2
R7411
255
1% 1/16W MF-LF 402
TPAD
49
59
20% 50V CERM 402
(IMVP6_VO)
1
R7405
10K
1% 1/16W MF-LF 402
C7404
0.22uF
10% 6.3V CERM-X5R 402
R7407
1
5% 1/16W MF-LF 402
R7430
3.92K
1% 1/16W MF-LF 402
59
(IMVP6_FB)
1
59
B
1
GND_IMVP6_SGND
VOLTAGE=0V
C7432
0.001UF
1 20% 50V CERM 402
NOSTUFF
C7414
470PF
10% 50V CERM 402 1
C7434
0.12UF
10% 10.0V CERM-X5R 402
C7428
0.47UF
10% 6.3V CERM-X5R 402
R7415
10.5K
1% 1/16W MF-LF 402
B
1
IMVP6_VO_R
1
R7443
3.65K
1% 1/16W MF-LF 402
(IMVP6_VW)
C7433
C7413
220PF
1 5% 25V CERM 402
CRITICAL
C7407
0.001UF
10% 50V CERM 402
R7410
6.81K
1% 1/16W MF-LF 402
0.001UF 1 2
20% 50V CERM 402
R7431
10KOHM-5%
0603-LF 2
IMVP6_COMP_RC
2 1
(IMVP6_ISEN2) (IMVP6_VSUM) (IMVP6_VO)
R7414
97.6K
1% 1/16W MF-LF 402
ERT-J1VR103J
(IMVP6_COMP)
1 2 1 1
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.

PLACEMENT_NOTE=PLACE CLOSE TO PIN 21 OF U7400
C7421
0.22uF
10% 6.3V CERM-X5R 402
R7423
0
R7422
0
5% 1/16W MF-LF 402
OMIT
XW7400
SM 1
5% 1/16W MF-LF 2 402
CPU_VCCSENSE_P CPU_VCCSENSE_N
11 70 11 70 59 59 59
MIN_LINE_WIDTH
MIN_NECK_WIDTH 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.25 MM
R
IMVP6 CPU VCORE REGULATOR

A
MIN_LINE_WIDTH
59 59 59 59 59
59 59 59 59 59
MIN_NECK_WIDTH 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM

59 59 59 59 59
MIN_LINE_WIDTH
MIN_NECK_WIDTH 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM
59 59 59 59 59
IMVP6_PHASE1 IMVP6_BOOT1 IMVP6_UGATE1 IMVP6_LGATE1 IMVP6_ISEN1
1.5 MM 0.25 MM 1.5 MM 1.5 MM 0.25 MM
IMVP6_PHASE2 IMVP6_BOOT2 IMVP6_UGATE2 IMVP6_LGATE2 IMVP6_ISEN2
0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM
IMVP6_OCSET IMVP6_VSUM GND_IMVP6_SGND IMVP6_VO IMVP6_DROOP IMVP6_DFB IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
0.25 MM 0.25 MM 0.50 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM
SYNC_MASTER=K24_MLB
PAGE TITLE
IMVP6 CPU VCore Regulator

DRAWING NUMBER SIZE
Apple Inc.
051-7982
REVISION
C.0.0
BRANCH PAGE
59 59
IMVP6_RTN IMVP6_VSEN
0.25 MM 0.25 MM
0.25 MM 0.25 MM
74 OF 109
SHEET
=PPVIN_S0_MCPCORE
PLACEMENT_NOTE=PLACE C7563 ACROSS PIN 5 OF Q7560 AND PINS 1/2/3 OF Q7565
D
R7593
41
R7560
5V_S0_MCPREG_VIN
VOLTAGE=5V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM 1
2.2
5% 1/10W MF-LF 603
=PP5V_S0_MCPREG
CRITICAL
8
CRITICAL
1
D
1
C7563
0.001UF
5
10% 50V X7R 402
C7560
68UF
C7571
68UF
C7561
1UF
10% 25V X5R 603-1
C7590 2.2UF
MCPCORES0_IMON
0
5% 1/16W MF-LF 402
C7550
1UF
1
C7562
1UF
10% 16V X5R 402 (MCPCORES0_UGATE) MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
10% 2 16V X5R 603
R7561
1K
5% 1/16W MF-LF 402
10% 16V X5R 402
VDD
PVCC
CRITICAL Q7560 SIS426DN

G S
PWRPK-12128
16
R7590
21
IN
MCP_VID<0>
0
5% 1/16W MF-LF 402
22
MCPCORES0_RBIAS
U7500
1 2
RBIAS SOFT IMON PGOOD VID0 VID1 VID2 OFFSET0 OFFSET1 VR_ON AF_EN FDE VSEN RTN VW
QFN
VIN UGATE BOOT PHASE
14
GATE_NODE=TRUE DIDT=TRUE
ISL6263D
R7591
1
R7565
18 17 19
C7564
0.22UF 1 2 MCPCORES0_BOOT_R
0.25 MM 0.2 MM DIDT=TRUE CERM-X7R 10V 603 5%
MCPCORES0_SOFT MCPCORES0_IMON_R
63 OUT MCPCORES0_PGOOD MCP_VID0_R MCP_VID1_R MCP_VID2_R MCPCORES0_OS0 MCPCORES0_OS1 =MCPCORES0_EN 63 IN MCPCORES0_FDE
21
IN
MCP_VID<1>
0
5% 1/16W MF-LF 402
MCPCORES0_UGATE MCPCORES0_BOOT
DIDT=TRUE
1
5% 1/10W MF-LF 603
2 28 31 25 26 27 23 24 29 30 32
CRITICAL
R7525
0.001
1% 1W MF 0612 2
MAX CURRENT: 13A (Q7560 Limit)
R7592
21
L7560
0.68UH-16A
1
IN
MCP_VID<2>
0
5% 1/16W MF-LF 402
0.2 MM 0.25 MM
MCPCORES0_PHASE
SWITCH_NODE=TRUE DIDT=TRUE
(MCPCORES0_PHASE) SWITCHNODE
PPMCPCORE_S0_R
2 4
1 3
=PPMCPCORE_S0_REG
8 60
1NO
STUFF
PCMB065T-SM
R7589
1
1
C7566
10UF
20% 4V X5R 603
1 PLACEMENT_NOTE=PLACE R7580 ON THE BOTTOM SIDE PLACEMENT_NOTE=PLACE R7581 ON THE BOTTOM SIDE
NOSTUFF
R7580
20.0K
NOSTUFF
R7581
20.0K
(MCPCORES0_LGATE)
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
CRITICAL Q7565 SIS426DN

G S
1 2 3
2
5% 1/10W MF-LF 2 603
C7569
0.001UF
MCPCORE_SNUBBER
LGATE
21
MCPCORES0_LGATE
GATE_NODE=TRUE DIDT=TRUE
PWRPK-12128
1
10% 50V 2 X7R 402 1
f = 300 kHz CRITICAL

1
C7565
270UF
CRITICAL
1
C7568
270UF
MCPCORES0_VSEN MCPCORES0_RTN
8 9 4
NO STUFF
C7567
10UF
20% 4V X5R 603
C7589
0.001UF
50V 10% X7R 402 2
20% 2 2V TANT CASE-B4-SM
C
PLACEMENT_NOTE=PLACE R7582 ON THE BOTTOM SIDE PLACEMENT_NOTE=PLACE R7583 ON THE BOTTOM SIDE 1
20% 2 2V TANT CASE-B4-SM
MCPCORES0_VW
R7582
20.0K
R7583
20.0K VO MCPCORES0_COMP MCPCORES0_FB MCPCORES0_VDIFF
5 12 3
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
MCPCORES0_VO
(MCPCORES0_VO)
COMP FB VDIFF PGND

20
OCSET ISP ISN ICOMP VSS

15
R7569
MCPCORES0_OCSET MCPCORES0_ISP MCPCORES0_ISN MCPCORES0_ICOMP
1
11.3K
1% 1/16W MF-LF 402
6 7
13 11 10
PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP 60 8 =PPMCPCORE_S0_REG
1
R7573
10K
1% 1/16W MF-LF 402
C7573
47PF
5% 50V CERM 402
THRM_PAD
33 2
R7563
100
1 1% 1/16W MF-LF 402 (MCPCORES0_VSEN)
C7576
0.022UF
10% 16V CERM-X5R 402
R7572
150K
1
R7500
100
1% 1/16W MF-LF 402 2
XW7562
SM
60 8
R7566
MCPCORES0_RSEN_P
1
=PPMCPCORE_S0_REG
20
1% 1/16W MF-LF 402
2 1
1% 1/16W MF-LF 2 402
MCPCORES0_ISP_R
OMIT
XW7561
SM 1 2 (MCPCORES0_ISN) VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM
OMIT
C7570
0.001UF
10% 50V X7R 402 (MCPCORES0_RTN)
GND_MCPCORES0_AGND
XW7563
SM 1 2
R7568
MCPCORES0_RSEN_N
1
20
1% 1/16W MF-LF 402
R7575
47.0K
C7575
47PF
5% 50V CERM 402
OMIT
PLACEMENT_NOTE=PLACE XW7561 CLOSE TO PIN 15 OF U7500
R7571
100
(MCPCORES0_ICOMP)
1% 1/16W MF-LF 2 402 OCP=14.5A
1% 1/16W MF-LF 2 402
B
(MCPCORES0_VW)
C7579 C7580
68PF
1 2
0.001UF
10% 50V X7R 402 2 1
R7576
6.98K
1% 1/16W MF-LF 402
VID<2:0> 000 001 010 011
MCP TARGET +1.05V +1.00V +0.95V +0.90V +0.85V +0.80V +0.75V +0.70V
R7577
1
5% 50V CERM 402-1
C7581
560PF
1 10% 50V CERM 402 2 2
133K
1% 1/16W MF-LF 402
MCPCORES0_COMP_C
(MCPCORES0_COMP)
(MCPCORES0_FB)
R7578
1
C7582
560PF MCPCORES0_VDIF_C
1 10% 50V CERM 402 (MCPCORES0_VDIFF) 2
100 101 110 111
100
1% 1/16W MF-LF 402
R7579
1
2.21K
1% 1/16W MF-LF 402
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP CORE REGULATOR

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

75 OF 109
SHEET
CPUVTT POWER SUPPLY
=PPVIN_S0_CPUVTTS0
PLACEMENT_NOTE=PLACE C7696 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7620
CRITICAL
C7630
33UF
C7695
1UF
10% 25V X5R 603-1
C7696
0.001UF
20% 50V CERM 402
C
5 D 4
8
C
G
CRITICAL Q7620
CSD58858Q3
3.3X3.3-QFN
=PP5V_S0_CPUVTTS0
L7620
2.2UH-8.0A
1 2
=PPCPUVTT_S0_REG
8
S
R7601
301
1 1% 1/16W MF-LF 402 2
CRITICAL
PP5V_S0_CPUVTTS0_V5FILT
10 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
R7603 C7601
1UF
10% 10V X5R 402-1 2 1 1 4
1 2 3
PCMB065T-SM
VOUT = 1.052V 7.2A MAX OUTPUT F = 320 KHZ
200K
C7604
4.7UF
10% 6.3V X5R-CERM 603
1% 1/16W MF-LF 402 2
5 D 4 G
PLACEMENT_NOTE=Place XW7665 next to L7620

2
V5FILT
CRITICAL
V5DRV
2
C7665
10UF
20% 6.3V X5R 603
U7600
TPS51117RGY_QFN14
CRITICAL Q7621
CSD58858Q3
3.3X3.3-QFN
XW7665
SM
C7661
0.001UF
20% 50V CERM 402
2
1
OMIT
SYM 2 QFN
63
IN OUT
=CPUVTTS0_EN CPUVTTS0_PGOOD (=PPCPUVTT_S0_REG) CPUVTTS0_VFB CPUVTTS0_TRIP
EN_PSV PGOOD VOUT VFB TRIP GND

7
TON VBST DRVH LL DRVL THRM_PAD

15
CPUVTTS0_TON
DIDT=TRUE
C7603
0.1UF
10% 50V X7R
CRITICAL
2 1
63
14
CPUVTTS0_VBST
S
2
C7660
330UF
603-1
13
CPUVTTS0_DRVH
GATE_NODE=TRUE
1 2 3
DIDT=TRUE
12
CPUVTTS0_LL
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
11
CPUVTTS0_DRVL
GATE_NODE=TRUE
CPUVTTS0_VSNS
DIDT=TRUE
1
PGND
8
NO STUFF
R7670
8.06K
1% 1/16W MF-LF
C7670
100PF
5% 50V CERM 402
R7604
6.04K
1% 1/16W MF-LF 402
B
2
OMIT
1
XW7600
SM 2
402
<Ra>
(GND)
SM
OMIT
2
XW7601
PLACEMENT_NOT=PLACE XW7600 BETWEEN PIN 7 AND PIN 15 OF U7600

ROUTING NOTE:
R7671
20.0K
1% 1/16W MF-LF

ROUTING NOTE:
Place XW7601 by C7660.

2 402
GND_CPUVTTS0_SGND
<Rb>
Vout = 0.75V * (1 + Ra / Rb)

(CPUVTTS0_VFB) CPUVTTS0_VOUT (=PPCPUVTT_S0_REG)
SYNC_MASTER=K24_MLB
PAGE TITLE
CPU VTT(1.05V) SUPPLY

DRAWING NUMBER SIZE
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SHEET
1.8V S0 SWITCHER
8
=PP3V3_S0_P1V8S0
CRITICAL
C7760
10uF
20% 6.3V X5R 603
VI U7760
TPS62202
4 63
CRITICAL
L7760
10UH-0.55A-330MOHM
PCAA031B-SM
=P1V8S0_EN
FB EN
SOT23-5
MAX CURRENT = 200MA

2
SW 5 GND
2
P1V8S0_SW
DIDT=TRUE
=PP1V8_S0_REG
C7762
10uF
20% 6.3V X5R 603
C
1.05V S0 PLL LDO
LDO_YES
R7743
=PP3V3_S0_MCP_PLL_VLDO
8
100
5% 1/16W MF-LF 402
PP3V3_S0_MCP_PLL_VLDO_BIAS
MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
LDO_NO
1
8
C7740
1UF LDO_YES
10% 6.3V CERM 402
R7745
=PP1V05_S0_MCP_PLL_UF_R
1
0
5% 1/16W MF-LF 402
Vout = 1.05V
4
8 23
CRITICAL BIAS =PP1V5_S0_MCP_PLL_VLDO

8
MAX CURRENT = 0.5A
R7744
PP1V05_S0_MCP_PLL_UF_LDO
1
1 2
IN0 OUT0 IN1 LDO_YES OUT1
9 10
2
0
5% 1/16W MF-LF 402
TPS74701
<Ra> LDO_YES
1.37K
1% 1/16W MF-LF 402 1

DIDT=TRUE
C7741
1UF LDO_YES
1 5
SON
EN
FB
C7742
4.7UF
20% 4V X5R 402
LDO_YES
MCP 1.05V S5 (AUXC) SUPPLY
10% 6.3V CERM 402
P1V05S0_LDO_SS NOSTUFF
U7740
7
SS
PG
R7746
P1V05S0_LDO_FB
CRITICAL
1
8
10% 50V CERM 402
4.42K
0.0022UF
11 6
2
B
C7750
22UF NOSTUFF
1
2 20% 6.3V CERM 805 =PP3V3_S5_P1V05S5
C7743
<Rb>
GND THRML_PAD
1% 1/16W MF-LF 402
LDO_YES
LDO_YES
R7747
VOUT = 0.8V * (1 + RA / RB)

LDO_YES CRITICAL
R7782 0
1
5% 1/16W MF-LF 2 402

PP3V3_S5_P1V05S5_R_SKIP
R7748
1 P1V05S0_PGOOD
VIN
0
5% 1/16W MF-LF 402
U7750
ISL8009B DFN 2
3 4
63
L7770
2.2UH-3.25A
IHLP1616BZ-SM
8 6 5
P1V05S0_LDO_PGOOD
63
IN
=P1V05_S5_EN
EN CRITICAL
POR SKIP
LX VFB RSI
1V05S5_SW
DIDT=TRUE
2 1
=PP1V05_S5_REG
63
P1V05_S5_PGOOD
1V05S5_FB
<Ra>
R7780
25.5K
1% 1/16W MF-LF 402
C7776
47PF
5% 50V CERM 402
Vout = 1.05V
CRITICAL
1
MAX CURRENT = 0.8A FREQ = 1.6MHZ
R7783 0
GND
7
THRM_PAD
9
2 2
C7771
47UF
20% 6.3V X5R 0805
5% 1/16W MF-LF 2 402
<Rb>
1 2
R7781
80.6K
1% 1/16W MF-LF 402
A
VOUT = 0.8V * (1 + RA / RB)
SYNC_MASTER=K24_MLB
PAGE TITLE
MISC POWER SUPPLIES

DRAWING NUMBER SIZE
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SHEET
3.3V 1.05V S5 ENABLE

R7802
100K 63 8
=PP3V42_G3H_PWRCTL
Power Control Signals

1
PM_G2_P3V3S5_EN_L
MAKE_BASE=TRUE
2
5% 1/16W MF-LF 402
=P3V3S5_EN_L
OUT
57
3.3V_S0, 1.8V_S0 ENABLE

State SMC_PM_G2_ENABLE PM_SLP_S4_L PM_SLP_S3_L
MCPDDR, CPUVTT,MCPCORES0 ENABLE 1.5V S0 AND 1.05V S0 ENABLE
NO STUFF
C7802
0.068UF Run (S0)
1 1 1 0
1 1 0 0
1 0 0 0
Q7800
10%
D
57 36 7
SSM3K15FV
SOD-VESM-HF
10V CERM 402
Sleep (S3)
IN
SMC_PM_G2_EN
Soft-Off (S5)
Battery Off (G3Hot)
R7800
100K
5% 1/16W MF-LF 402
R7801
2 5.1K 2
5% 1/16W MF-LF 402
1 PM_G2_P1V05S5_EN
MAKE_BASE=TRUE
=P1V05_S5_EN
OUT
62
C7801
0.47UF
10% 6.3V CERM-X5R 402
R7859
(PM_SLP_S3_L)
67 36 32 21 7
IN
PM_SLP_S3_L
100 2
5%
1/16W MF-LF 402
PM_SLP_S3_L_BUF
MAKE_BASE=TRUE
=P5VS0_EN
OUT OUT
64
R7879
100K
R7880
5% 1/16W MF-LF 402 1
R7881
5% 1/16W MF-LF 402 1
R7882
5% 1/16W MF-LF 402 1
R7883
5% 1/16W MF-LF 402 1
=PBUSVSENS_EN
40
R7884
5% 1/16W MF-LF 402
S3 ENABLE
5% 1/16W MF-LF 402 2
22K
33K
10K
1
5.1K
R7813
68K 63 8
=PP3V42_G3H_PWRCTL
2
5%
1/16W MF-LF 402
Q7813
3
SSM3K15FV
SOD-VESM-HF
PM_SLP_S3_L_INVERT
MAKE_BASE=TRUE
=P5VS3_EN_L
OUT
57
P3V3S0_EN
MAKE_BASE=TRUE
=P3V3S0_EN
OUT OUT OUT OUT OUT
64
NO STUFF
37 36 21 7
IN
PM_SLP_S4_L
MAKE_BASE=TRUE
C7813
0.068UF
10%
P1V8S0_EN
MAKE_BASE=TRUE
=P1V8S0_EN
62
MCPDDR_EN
MAKE_BASE=TRUE
=MCPDDR_EN
64
2
1
10V CERM
1
(PM_S4_STATE_L)
R7810
100K
5% 1/16W MF-LF 402 2
402
CPUVTTS0_EN
MAKE_BASE=TRUE
=CPUVTTS0_EN
61
MCPCORES0_EN
MAKE_BASE=TRUE
=MCPCORES0_EN
60
NO STUFF
C7810 R7811
5.1K
1 1
5% 1/16W MF-LF 402 10%
402 402 402 402 402
0.47UF
2 2
6.3V CERM-X5R 402
C7880
0.47UF
10% 6.3V CERM-X5R
C7881
0.47UF
10% 6.3V
C7882
0.47UF
10% 6.3V
C7883
0.47UF
10% 6.3V
C7884
0.47UF
10% 6.3V CERM-X5R
CERM-X5R
CERM-X5R
CERM-X5R
DDRREG_EN
MAKE_BASE=TRUE
=DDRREG_EN =USB_PWR_EN
OUT OUT
58 35
NO STUFF
C7812 R7812
0
1 1
5% 1/16W MF-LF 402 10% 6.3V CERM-X5R 402
0.47UF
2
VOLTAGE MONITOR
63 8 =PP3V42_G3H_PWRCTL
=P3V3S3_EN
P3V3S3_EN
MAKE_BASE=TRUE
OUT
64 8 =PP3V3_S5_PWRCTL
C7840
1 1
B
6
0.1uF
20% 10V CERM 402
R7840
2 100K
5% 1/16W MF-LF
B
36
VDD
5
402
SENSE CT
U7840 RESET*
SOT23-6
RSMRST_PWRGD
R7895
3
TP_U7840_MR_L
TPS3808G33DBVRG4
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

1
=PP5V_S0_VMON
CT
MR*
0
5%
1/16W
P1V05_S5_PGOOD 62
GND
2
R7870
10K
1% 1/16W MF-LF 402 2
TPS3808 MR* HAS INTERNAL PULLUP
MF-LF 402
OTHER S0 RAILS PGOOD

8 =PP3V3_S0_PWRCTL
C7841
0.001UF
20% 50V CERM
PP3V3_VMON_VDD
402
R7820
2 7 353S2310
10K
1 5% 1/16W MF-LF 402 2
OMIT
VDD
C7870
0.1uF
20% 10V CERM 402
R7871
20.0K
1% 1/16W
U7870
ISL88042IRTEZ
TDFN
8 =PP3V3_S0_VMON 8 8
=PP1V5_S0_VMON
MF-LF 402 2
R7890
57
IN
P5V3V3_PGOOD
3 5 6
V2MON V3MON V4MON
MR* RST*
NC
S0PGOOD_PWROK
5% 1/16W MF-LF 402
=PP1V05_S0_VMON
GND
4
THRM_PAD
9
60
R7892
IN
MCPCORES0_PGOOD
2
TP_DDRREG_PGOOD
Unused PGOOD signal

DDRREG_PGOOD
MAKE_BASE=TRUE
A
V2MON THRESHOLD IS 2.866V V3MON THRESHOLD IS 0.6V V4MON THRESHOLD IS 0.6V
5% 1/16W MF-LF 402
58
A
PAGE TITLE
R7891
61
IN
CPUVTTS0_PGOOD
POWER SEQUENCING
DRAWING NUMBER SIZE
62
5% 1/16W MF-LF 402

P1V05S0_LDO_PGOOD
R7893
1
Apple Inc.
R
051-7982
REVISION
IN
C.0.0
BRANCH PAGE
R7894
1
5% 1/16W MF-LF 402

(S0PGOOD_PWROK)

ALL_SYS_PWRGD
OUT
25 36
5% 1/16W MF-LF 402
78 OF 109
SHEET
7
3.3V S3 FET
CRITICAL
3
1.5V S0 FET
Q7910
FDC638P_G
SM
(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
3.3V S3 FET
=PP3V3_S3_FET
=PP3V3_S5_P3V3S3FET
6
MOSFET
5 4 2
FDC638P P-TYPE 48 mOhm @4.5V
=PP1V5_S3_P1V5S0FET
9
R7912
10K
5%
C7911
0.033UF
10% 16V X5R
CHANNEL RDS(ON)
1 1
CRITICAL
Q7901
D
D
Q7903
SSM3K15FV
SOD-VESM-HF
1/16W MF-LF 402 402 2
ROME
DFN
LOADING
3
0.182 A (EDP)
R7910
47K
P3V3S3_EN_L
1 2
C7910
0.01UF
1 2
D
NC
8 41 6
C7902
0.1UF
20% 10V
P3V3S3_SS
4
2
G SENSE KELVIN S GND

P1V5_S0_KELVIN
5% 1/16W MF-LF 402 10% 16V CERM 402
8 =PP5V_S3_MCPDDRFET
1
R7901
10K
2 5% 1/16W
CERM 402
OUT
MCPDDR_SS
3 7 1 2 3
R7903
100K
1 63
MF-LF 402
Q7971
SSM6N15FEAPE
SOT563
41
P1V5_S0_SENSE =PP1V5_S0_FET
OUT
8
5% 1/16W
MF-LF 402 2
IN
=P3V3S3_EN
R7971
47K
MCPDDR_EN_L
1 5% 2
1 1
C7903
0.068UF
10% 10V
1.5V S0 FET
MOSFET CHANNEL Rome SenseFET N-TYPE 6.3 mOHM @4.5V VGS 5A (EDP)
2 1/16W MF-LF 402
CERM 402
Q7971
SSM6N15FEAPE
SOT563
MCPDDR_EN_L_RC
RDS(ON) LOADING
CRITICAL
3.3V S0 FET
8
=PP3V3_S5_P3V3S0FET
Q7930
FDC606P_G
SOT-6
3.3V S0 FET
=PP3V3_S0_FET
63
IN
=MCPDDR_EN
MOSFET CHANNEL RDS(ON) LOADING
FDC606P P-TYPE 26 MOHM @4.5V 1.431 A (EDP)
C
Q7905
SSM3K15FV
SOD-VESM-HF
100K
5% 1/16W MF-LF
0.033UF
10% 16V 2 X5R 402
R7932
C7931
402 2
R7930
47K
P3V3S0_EN_L
1 2
C7930
0.01UF
P3V3S0_SS
1 2
5% 10% 1/16W MF-LF 402 16V CERM 402
1 63
IN
=P3V3S0_EN
376S0778
CRITICAL
5.0V RT S0 FET
8
=PP5V_S3_P5VRTS0FET
Q7940
TPCP8102
23V1K-SM
=PP5VRT_S0_FET
MCP79 DDRVTT FET

5.0V RT S0 FET
8
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

MOSFET CHANNEL RDS(ON) LOADING TPCP8102 P-TYPE
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP. IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
R7942
47K
5% 1/16W MF-LF
0.033UF
10% 16V 2 X5R 402
C7941
13.5 MOHM @4.5V 0.48 A (EDP)
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
402
B
Q7945
SSM3K15FV
SOD-VESM-HF
R7940
47K
P5V0RTS0_EN_L
1 2
C7940
0.01UF
P5V0RTS0_SS
1 2
WILL EXIT SELF-REFRESH PREMATURELY. MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS LOW THROUGH VTT TERMINATION RESISTORS.
5% 1/16W MF-LF 402 10% 16V CERM 402
1 64 63
R7975
2 8
10 =PPVTT_S0_VTTCLAMP
2
5% 1/10W
IN
=P5VS0_EN
VTTCLAMP_L
90mA max load @ 0.9V 81mW max power
376S0778
MF-LF 603
CRITICAL
5.0V LT S0 FET
8
=PP5V_S3_P5VLTS0FET
Q7948
TPCP8102
23V1K-SM
=PP5VLT_S0_FET
=PP5V_S3_VTTCLAMP
CKT FROM T18
Q7975
5.0V LT S0 FET
8
R7976
100K
5% 1/16W MF-LF 402
SSM6N15FEAPE
SOT563
MOSFET CHANNEL RDS(ON) LOADING
TPCP8102 P-TYPE 13.5 MOHM @4.5V 1.302 A (EDP)
R7943
47K
5% 1/16W MF-LF
C7942
0.033UF
10% 16V X5R 402
VTTCLAMP_EN
402 2
R7944
47K
P5V0LTS0_EN_L
1 2
C7943
0.01UF
P5V0LTS0_SS
1 2
Q7975
SSM6N15FEAPE
SOT563
NO STUFF
C7976
0.001UF
20% 50V CERM
5%
1/16W
10% 16V CERM 402
402 5
Q7947
SSM3K15FV
SOD-VESM-HF
MF-LF 402
SYNC_MASTER=K24_MLB
PAGE TITLE
58 25
IN
=DDRVTT_EN
POWER FETS
DRAWING NUMBER SIZE
1 64 63
Apple Inc.
2
R
051-7982
REVISION
IN
=P5VS0_EN
C.0.0
BRANCH PAGE

79 OF 109
SHEET
CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

18
LCD
CONNECTOR
FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY
CRITICAL
LVDS_IG_PANEL_PWR
1
LVDS CONNECTOR:518S0650
R9014
1K
5% 1/16W MF-LF 2 402
20474-030E-11
F-RT-SM 31
J9000
32
CRITICAL
C9015
0.001UF
C9010
0.001UF
10% 50V X7R 402
FPF1009
1 ON
8
U9000
MFET-2X2
L9004
FERR-120-OHM-1.5A PP3V3_LCDVDD_SW
VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM
1
1 0402-LF 2 CRITICAL
10% 50V X7R 402
1 2
=PP3V3_S5_LCD
2 VIN_1 3 VIN_2
VOUT_1 4 VOUT_2 5 THRM PAD 7
PP3V3_LCDVDD_SW_F
VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM
3 4 5
L9008
1 0402-LF
120-OHM-0.3A-EMI
2 MIN_LINE_WIDTH=0.25 MM
7
GND
1
C9009
0.1UF
10% 16V X5R 402
C9011
0.1UF
C9012
10UF
8
PP3V3_S0_LCD_F
VOLTAGE=3.3V
72 18 7 72 18 7
LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<2>
7 8 9
10% 16V 2 X5R 402
20% 6.3V 2 X5R 603
=PP3V3_S0_LCD
1 1
(LVDS DDC POWER)

72 18 7
10 11 12 13 14 15 16
R9008
100K
5% 1/16W MF-LF 402 2
R9009
100K
5% 1/16W MF-LF 402
72 7 72 7
72 18 7 72 18 7 72 18 7
LVDS I/F
LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P
2
18 7 18 7
LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA
CRITICAL
L9080
90-OHM-200MA AMC2012-SM
SYM_VER-1
NC
68 47 7
17 18 19
PPVOUT_S0_LCDBKLT
72 18
LVDS_IG_A_CLK_N
PLACEMENT_NOTE=PLACE CLOSE TO J9000
C9017 1000PF
LED BKLT I/F
NC
68 7 68 7 68 7 68 7
20 21 22 23 24 25 26 27 28 29 30
72 18
LVDS_IG_A_CLK_P
5% 2 50V C0G-CERM 603
LED_RETURN_6 LED_RETURN_5 LED_RETURN_4 LED_RETURN_3 LED_RETURN_2 LED_RETURN_1
L9050
8
68 7 68 7
=PP5V_S3_CAMERA
PP5V_S3_CAMERA_F
FERR-120-OHM-1.5A
0402-LF
C9016
0.1uF
CAMERA I/F
20% 10V CERM 402
33 34
CRITICAL
L9060
90-OHM DLP0NS
SYM_VER-1
CAMERA
4 73 7
73 20
OUT
USB_CAMERA_P
USB_CAMERA_CONN_P
73 20
OUT
USB_CAMERA_N
2
PLACEMENT_NOTE=PLACE CLOSE TO J9000.
73 7
USB_CAMERA_CONN_N
SYNC_MASTER=K24_MLB
PAGE TITLE
LVDS CONNECTOR
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

90 OF 109
SHEET
3
=MCP_HDMI_TXC_P =MCP_HDMI_TXC_N =MCP_HDMI_TXD_P<0> =MCP_HDMI_TXD_N<0> =MCP_HDMI_TXD_P<1> =MCP_HDMI_TXD_N<1> =MCP_HDMI_TXD_P<2> =MCP_HDMI_TXD_N<2> =MCP_HDMI_HPD =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA
2
DP_ML_P<3>
MAKE_BASE=TRUE
18 18 18 18 18 18 18 18 18
67 72 67 72
MAKE_BASE=TRUE
DP_ML_N<3> DP_ML_P<2>
MAKE_BASE=TRUE
67 72 67 72
MAKE_BASE=TRUE
DP_ML_N<2> DP_ML_P<1>
MAKE_BASE=TRUE
67 72 67 72
MAKE_BASE=TRUE
DP_ML_N<1> DP_ML_P<0> DP_ML_N<0> DP_HPD

67 72 67 72
MAKE_BASE=TRUE
67 66
MAKE_BASE=TRUE
18 18
DP_IG_DDC_CLK DP_IG_DDC_DATA
MAKE_BASE=TRUE
66
DP_AUX_CH_C_N
BI
67 72
R9300
DP_IG_DDC_DATA
66
C9300
0.1UF
1 2 72
33
1 5% 1/16W MF-LF 402 2
DP_AUX_CH_SW_N
BI
Display Port Interoperability spec says that sources or sinks which do both DP and DVI must depend on the external adapter for pull ups on DDC lines (since DP AUX CH has 100K pull up/down on the MLB)..
10% 16V X5R 402
DP_AUX_CH_C_P
BI
67 72
R9301
DP_IG_DDC_CLK
66
C9301
0.1UF
1 2 72
33
1 5% 1/16W MF-LF 402 2
DP_AUX_CH_SW_P
BI
10% 16V X5R 402
Q9300
SSM6N15FEAPE
SOT563
Q9300
SSM6N15FEAPE
SOT563
DP_IG_AUX_CH_P
72 18
BI
DP_IG_AUX_CH_N
72 18
BI
=PP5V_S0_DP_AUX_MUX
8
R9302
100K
5% 1/16W MF-LF 402
R9306
1K
5% 1/16W MF-LF 402
DDC_CA_DET_LS5V_L
B
Q9301
3
B
D
SSM3K15FV
SOD-VESM-HF
DP_CA_DET
67
IN
DP_IG_CA_DET
OUT
18
SYNC_MASTER=K24_MLB
PAGE TITLE
DISPLAYPORT SUPPORT
DRAWING NUMBER SIZE
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SHEET
POR IS PLASTIC MINI DP CONNECTOR BUT METAL PARTS SCHEMATIC AND CAD SUMBOLS HAVE BEEN USED BEACUSE ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES
Port Power Switch

DP_ESD DP_ESD CRITICAL
D
8
CRITICAL
CRITICAL
D
IO NC
4 7
D9410
D9410
RCLAMP0524P
SLP2510P8
U9480
TPS2051B SOT23 =PP3V3_S5_DP_PORT_PWR
PM_SLP_S3_L
L9400
FERR-120-OHM-3A
RCLAMP0524P
SLP2510P8
2
5 4
IN
EN
OUT OC* GND

2
1 3
PP3V3_S0_DPILIM TP_DPPWR_OC_L
1 0603 1
PP3V3_S0_DPPWR
MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V 2 9
63 36 32 21 7
IN
C9400
4.7UF
20% 6.3V X5R-CERM 402
IO NC GND
IO NC
1 10
5 6
IO NC GND
3
CRITICAL
C9480
22UF
20% 6.3V X5R-CERM-1 603
C9481
4.7UF
20% 6.3V X5R-CERM 402
C9485
22UF
20% 6.3V X5R-CERM-1 603
C9486
22UF
20% 6.3V X5R-CERM-1 603
R9420
100K
5% 1/16W MF-LF 402 2
HDMI_CEC
CRITICAL
OMIT
J9400
MINIDSPLYPRT-K83
F-RT-THSM
FL9400
TOP ROW
SM PINS
1 3 5 1 7 9 11 13 1 15 17 19 72 DP_ML_CONN_N<2> 2 3 72 DP_ML_C_N<2> 72 DP_ML_CONN_P<2> 72 72 12-OHM-100MA TCM1210-4SM 72 72
C
FL9403
12-OHM-100MA TCM1210-4SM 4 72 66
SYM_VER-2 2
R9425
1M
5% 1/16W MF-LF 402
BOT ROW
TH PINS
2 4 6
DP_ML_CONN_P<0> DP_ML_CONN_N<0>
SYM_VER-2
4 72 DP_ML_C_P<0>
C
C9410
0.1uF
1 2 10%
DP_ML_P<0>
16V X5R 402
IN
66 72
1 8 72
IN
DP_ML_P<3>
C9414
0.1uF
2 10%
72 DP_ML_C_P<3>
16V X5R 402
10 12 14 16 18
HOT_PLUG_DETECT GND CONFIG1 ML_LANE0P CONFIG2 ML_LANE0N GND GND ML_LANE3P ML_LANE1P ML_LANE3N GND AUX_CHP AUX_CHN DP_PWR ML_LANE1N GND ML_LANE2P ML_LANE2N RETURN
FL9401
12-OHM-100MA TCM1210-4SM
SYM_VER-2
72 DP_ML_C_N<0>
C9411
0.1uF
2 10%
DP_ML_N<0>
16V X5R 402
IN
66 72
4 72 DP_ML_C_P<1>
C9412
0.1uF
2 10%
DP_ML_P<1>
16V X5R 402
IN
66 72
2 3
72 66
IN
DP_ML_N<3>
C9415
0.1uF
2 10%
72 DP_ML_C_N<3>
16V X5R 402
72
FL9402
12-OHM-100MA TCM1210-4SM
SYM_VER-2
72 DP_ML_C_N<1> 4 72 DP_ML_C_P<2>
C9413
0.1uF
2 10%
DP_ML_N<1>
16V X5R 402
IN
66 72
72 66
BI
DP_AUX_CH_C_P
C9416
0.1uF
2 10%
DP_ML_P<2>
16V X5R 402
IN
66 72
72 66
BI
67 8
DP_AUX_CH_C_N =PP3V3_S0_DPCONN
1 1
20
C9417
0.1uF
2 10%
DP_ML_N<2>
16V X5R 402
IN
66 72
DP_ESD CRITICAL
SHIELD PINS
22 21
R9443
100K
5% 1/16W MF-LF 402
D9411 R9421
100K
5% 1/16W MF-LF 402 1
R9442
100K
5% 1/16W MF-LF 402 2
RCLAMP0524P
SLP2510P8
514-0691
66
OUT
DP_CA_DET
6
2
2
IO NC GND
IO NC
1 10
DP_ESD CRITICAL DP_ESD CRITICAL
Q9440
2N7002DW-X-G
SOT-363
D9411
RCLAMP0524P
SLP2510P8
S
1
DP_CA_DET_L_Q
3
D9400
RCLAMP0504F D
SC70-6-1 5 6
B
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm
Q9440
2N7002DW-X-G
SOT-363
S
4
DP_CA_DET_Q DP to DVI/HDMI
1
IO NC GND
IO NC
4 7
R9422
1M
5% 1/16W MF-LF 402 2
Cable Adapter (CA) has 100k pull-up to DP_PWR.
3 4 3
67 8
=PP3V3_S0_DPCONN
1
R9445
10K
5% 1/16W MF-LF 402
R9444
10K
5% 1/16W 2 MF-LF 402
66
OUT
DP_HPD
6 1
MCP79 requires pull down HPD input with 100K if DP_HPD is used.
R9446
100K
5% 1/16W MF-LF 402
Q9441
2N7002DW-X-G
SOT-363
S
1
DP_HPD_L_Q
3
Q9441
2N7002DW-X-G
SOT-363
S
4
DP_HPD_Q DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).
2
SYNC_MASTER=K24_MLB
PAGE TITLE
R9423
100K
5% 1/16W MF-LF 402
DisplayPort Connector
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SHEET
CRITICAL
PLACEMENT_NOTE=PLACE NEAR L9710 CRITICAL

R9700
0.020
1% 0.25W MF-LF 805
69
L9710
10UH-2.1A
1 2 IHLP2020BZ11-SM 1
CRITICAL
D9710
SOD-123
1 3
2 4
PLACEMENT_NOTE=PLACE CLOSE TO L9710
PPVIN_BKL CRITICAL
PLACEMENT_NOTE=PLACE CLOSE TO L9710
PPVOUT_S0_LCDBKLT_SW
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=50V SWITCH_NODE=TRUE
PLACEMENT_NOTE=PLACE C9717 CLOSE TO D9710 PIN 2 & XW9701
PPVOUT_S0_LCDBKLT
1 C9713
0.1UF
10% 25V X5R 402
CRITICAL
RB160M-40
1
NOSTUFF CRITICAL
1
7 47 65
C9710
10UF
10% 25V X5R 805
R9730
10
5% 1/16W MF-LF 402
2
76 47
DIDT=TRUE
C9715
4.7UF
20% 50V X7R-CERM 1206
C9716
2.2UF
10% 50V X7R 1206
C9717
1000PF
10% 100V X7R 603
OUT ISNS_LCDBKLT_P
PLACEMENT_NOTEs:
68
f = 600kHz
2 68
OMIT
2 2
XW9701
SM
GND_LCDBKLT_PGND
76 47
LCDBKLT_VIN (C9710-C9711)
MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM 20 1
GND_LCDBKLT_PGND
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 MM
OUT ISNS_LCDBKLT_N
VIN
1
WF: C9711 AND C9717 NOT IN REF SCHEMATIC. SWA SWB VOUT
4 3 24
1
C9711
1UF
10% 25V X5R 603-1
PP2V5_S0_LCDBKLT
VDC1
PLACEMENT_NOTE=PLACE CLOSE TO U9700 PIN 1
5% 50V 2 C0G-CERM 603
C9727 1000PF
PP5V5_S0_LCDBKLT
23
VDC2 CRITICAL
NOSTUFF
NOSTUFF
1
C9721
100PF
5% 50V CERM 402
C9723
100PF
5% 50V CERM 402
NOSTUFF
PLACEMENT_NOTEs: PLACE NEAR U9700 (C9721-C9726)
C9725
100PF
5% 50V CERM 402
C9700
2.2UF
20% 10V X5R-CERM 402
C9701
2.2UF
20% 10V X5R-CERM 402
R9715
1M
1 2
U9700
MC34845
LLP
OVP = Vovp * (1 + Ra/Rb) VOVP = 6.9V +/- 0.35V OVP

22
1% 1/16W MF-LF 402
NOSTUFF
2
(SGND)
R9725
69 18
LCDBKLT_OVP
<Ra>
C9722
100PF
5% 50V CERM 402
NOSTUFF
C9724
100PF
5% 50V CERM 402
NOSTUFF
C9726
100PF
5% 50V CERM 402
IN
LVDS_IG_BKL_PWM
LVDS_IG_BKL_PWM_R
16 18
5% 1/16W MF-LF 402
PWM WAKE EN COMP ISET
2 1
R9717
10.2
1% 1/16W MF-LF 402 2
CH1 CH2 CH3 CH4 CH5 CH6
BKL_MC_CH1
LED_RETURN_1 R9718
10.2
1 1% 1/16W MF-LF 402 2
IN
7 65
BKL_MC_CH2
LED_RETURN_2 R9719
1
LCDBKLT_COMP
22K
5% 1/16W MF-LF
17 15
BKL_MC_CH3 R9720
10.2
1 1% 1/16W MF-LF 402 2
10.2
1% 1/16W MF-LF 402
2
IN
7 65
LED_RETURN_3
R9726
LCDBKLT_ISET
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 10 BKL_MC_CH4 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 11 BKL_MC_CH5 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 12 BKL_MC_CH6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 14
IN
7 65
LED_RETURN_4
IN
7 65
C9705
0.0022UF
CERM 402 10% 50V
R9721
10.2
1 1% 1/16W MF-LF 402 2
2 402
R9710
7.68K
LED_RETURN_5 R9722
10.2
1 1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 2 402
IN
7 65
LED_RETURN_6
IN
7 65
LCDBKLT_COMP_RC
1
<Riset> FAIL PGNDA PGNDB GND
LCDBKLT_FAIL
R9705
10K
C9706
56PF
5% 50V CERM 402
13
19
21
25
1% 1/16W MF-LF 2 402
R9702 1
THRM
R9716
243K
PAD
NOSTUFF
5% 1/16W MF-LF 402
1% 1/16W MF-LF 402 2 2
OMIT
XW9700
SM 1 2
GND_LCDBKLT_SGND ISET = 153mA / <Riset>

<Rb>
PLACEMENT_NOT=PLACE XW9700 FAR FROM THE NOISY
PINS 3 AND 4
13.3 Inch Panel (9 LEDs per string)

TARGET: ISET = 20MA, ACTUAL: ISET = 19.9MA, OVP = 35V OVP = 35.2V
SYNC_MASTER=VEMURI_K19I
PAGE TITLE
LCD Backlight Driver (MC34845)

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SHEET
CRITICAL
Q9806
FDC638APZ_SBMS001
SSOT6-HF
PPBUS S0 LCDBkLT FET

MOSFET CHANNEL
2
F9800
2AMP-32V
FDC638APZ P-TYPE 43 mOhm @4.5V 0.4 A (EDP)
IN
=PPBUS_S0_LCDBKLT
PPBUS_S0_LCDBKLT_FUSED
RDS(ON) LOADING
0402-HF
VOLTAGE=12.6V
R9808
301K
1%
C9802
0.1UF
10%
1/16W MF-LF 402
16V
2
X5R 402
PPBUS_S0_LCDBKLT_EN_DIV
R9809
147K
1% 1/16W MF-LF 402
PPBUS_S0_LCDBKLT_EN_L
Q9807
SSM6N15FEAPE
SOT563
4
MIN_LINE_WIDTH=0.4 mm
69 18
IN
LVDS_IG_BKL_ON
OUT
68
BKLT_EN_L
MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V
Q9807
SSM6N15FEAPE
SOT563
C
25
C
1
IN
BKLT_PLT_RST_L
LVDS_IG_BKL_ON LVDS_IG_BKL_PWM
18 69 18 68
R9840
1K
5% 1/16W MF-LF 2 402
R9841
1K
5% 1/16W MF-LF
402
MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS
SYNC_MASTER=K24_MLB
PAGE TITLE
LCD Backlight Support

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SHEET
8
FSB (Front-Side Bus) Constraints
PHYSICAL_RULE_SET
FSB_50S
7
LAYER
*
6
TABLE_PHYSICAL_RULE_HEAD
5
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
TABLE_PHYSICAL_RULE_ITEM
4
CPU / FSB Net Properties
NET_TYPE PHYSICAL SPACING
ALLOW ROUTE ON LAYER?

=50_OHM_SE
MINIMUM LINE WIDTH

=50_OHM_SE
MINIMUM NECK WIDTH

=50_OHM_SE
MAXIMUM NECK LENGTH

=50_OHM_SE
DIFFPAIR PRIMARY GAP

=STANDARD
=STANDARD
FSB_DATA_GROUP0
FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S
FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB
FSB_D_L<15..0> FSB_DINV_L<0> FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_D_L<31..16> FSB_DINV_L<1> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_D_L<47..32> FSB_DINV_L<2> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> FSB_D_L<63..48> FSB_DINV_L<3> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> FSB_A_L<16..3> FSB_REQ_L<4..0> FSB_ADSTB_L<0> FSB_A_L<35..17> FSB_ADSTB_L<1> FSB_ADS_L FSB_BREQ0_L FSB_BREQ1_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L<2..0> FSB_TRDY_L CPU_A20M_L CPU_BSEL<2..0> CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L
10 14 10 14 10 14 10 14
FSB_DSTB_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
FSB_DATA_GROUP0 FSB_DSTB0
TABLE_SPACING_RULE_HEAD
FSB_DSTB0
SPACING_RULE_SET
FSB_DATA
LAYER
*
LINE-TO-LINE SPACING
=2x_DIELECTRIC
WEIGHT
TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET
FSB_DATA
LAYER
TOP,BOTTOM
=4x_DIELECTRIC
WEIGHT
FSB_DATA_GROUP1
10 14 10 14 10 14 10 14
?
?
FSB 4X Signal Groups
FSB_DATA_GROUP1 FSB_DSTB1 FSB_DSTB1
FSB_DSTB
=3x_DIELECTRIC
?
FSB_DSTB
TOP,BOTTOM
=5x_DIELECTRIC
?
FSB_ADDR
=STANDARD
?
FSB_ADDR
TOP,BOTTOM
=3x_DIELECTRIC
?
FSB_DATA_GROUP2 FSB_DATA_GROUP2 FSB_DSTB2 FSB_DSTB2
10 14 10 14 10 14 10 14
FSB_ADSTB
=2x_DIELECTRIC
?
FSB_ADSTB
TOP,BOTTOM
=4x_DIELECTRIC
?
FSB_1X
=STANDARD
FSB_1X
TOP,BOTTOM
=3x_DIELECTRIC
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB_DATA_GROUP3 FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB
10 14 10 14 10 14 10 14
FSB 4X signals / groups shown in signal table on right.

FSB_DATA_GROUP3
Signals within each 4x group should be matched within 5 ps of strobe.

FSB_DSTB3
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
FSB_DSTB3
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s. DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs. FSB 2X signals / groups shown in signal table on right. Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps. Signals FSB 2X
FSB_ADDR_GROUP0 FSB_ADDR_GROUP0 FSB_ADSTB0 FSB_50S FSB_50S FSB_50S FSB_ADDR FSB_ADDR FSB_ADSTB
10 14 10 14 10 14
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#. FSB 1X signals shown in signal table on right. Signals within each 1x group should be matched to CPU clock, +0/-1000 mils. Design Guide recommends each strobe/signal group is routed on the same layer.
FSB_ADDR_GROUP1 FSB_ADSTB1
FSB_50S FSB_50S
FSB_ADDR FSB_ADSTB
10 14 10 14
FSB_1X FSB_BREQ0_L FSB_BREQ1_L
FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S
FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X
10 14 10 14 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 14 10 13 14 10 14 10 14
Intel Design Guide recommends FSB signals be routed only on internal layers.
FSB_1X
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
FSB 1X Signals
FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X
CPU Signal Constraints

PHYSICAL_RULE_SET
CPU_50S
LAYER
*

=50_OHM_SE
MINIMUM LINE WIDTH

=50_OHM_SE
MINIMUM NECK WIDTH

=50_OHM_SE
MAXIMUM NECK LENGTH

=50_OHM_SE

=STANDARD
DIFFPAIR NECK GAP

FSB_1X FSB_CPURST_L
=STANDARD
FSB_1X
CPU_27P4S
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
FSB_1X
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
CPU_ASYNC CPU_BSEL
CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S MCP_50S MCP_50S MCP_50S MCP_50S
CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP
10 14 9 10 10 14 10 14 10 14 10 14 10 14 10 14 37 10 13 14 10 14 10 14 10 14 37 10 14 10 14 10 14 59 10 14 14 14 14 14
SPACING_RULE_SET
CPU_AGTL
LAYER
*
=STANDARD
WEIGHT
SPACING_RULE_SET
CPU_AGTL
LAYER
TOP,BOTTOM
=2x_DIELECTRIC
WEIGHT
CPU_FERR_L CPU_ASYNC
?
?
CPU_INIT_L
CPU_8MIL
8 MIL
?
CPU_ASYNC_R CPU_ASYNC_R
CPU_COMP
25 MIL
?
CPU_PROCHOT_L
CPU_GTLREF
25 MIL
?
SR DG recommends at least 25 mils, >50 mils preferred
CPU_PWRGD CPU_ASYNC CPU_ASYNC
CPU_ITP
=2:1_SPACING
?
CPU_VCCSENSE
25 MIL
PM_THRMTRIP_L FSB_CPUSLP_L
Most CPU signals with impedance requirements are 55-ohm single-ended.

CPU_FROM_SB
Some signals require 27.4-ohm single-ended impedance.

CPU_DPRSTP_L
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
CPU_ASYNC MCP_CPU_COMP MCP_CPU_COMP
MCP FSB COMP Signal Constraints

MCP_CPU_COMP MCP_CPU_COMP
PHYSICAL_RULE_SET
MCP_50S
LAYER
*

=50_OHM_SE
MINIMUM LINE WIDTH

=50_OHM_SE
MINIMUM NECK WIDTH

=50_OHM_SE
MAXIMUM NECK LENGTH

=50_OHM_SE

=STANDARD
DIFFPAIR NECK GAP

FSB_CLK_CPU
CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D
CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB
10 14 10 14 13 14 13 14 14 14
=STANDARD
FSB_CLK_CPU FSB_CLK_ITP
B
SPACING_RULE_SET
MCP_FSB_COMP
LAYER
*
8 MIL
WEIGHT
FSB_CLK_ITP FSB_CLK_MCP FSB_CLK_MCP
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

CPU_IERR_L CPU_50S
10
FSB Clock Constraints

PM_DPRSLPVR
CPU_50S CPU_50S
CPU_AGTL CPU_AGTL
PM_DPRSLPVR IMVP_DPRSLPVR CPU_GTLREF CPU_COMP<3> CPU_COMP<2> CPU_COMP<1> CPU_COMP<0> XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L<4..0> XDP_BPM_L<5> XDP_CPURST_L CPU_VID<6..0> IMVP6_VID<6..0> CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N
21 59 59
PHYSICAL_RULE_SET
CLK_FSB_100D
LAYER
*

=100_OHM_DIFF
(See above)
CPU_GTLREF CPU_COMP CPU_COMP
MINIMUM LINE WIDTH

=100_OHM_DIFF
MINIMUM NECK WIDTH

=100_OHM_DIFF
MAXIMUM NECK LENGTH

=100_OHM_DIFF

=100_OHM_DIFF
DIFFPAIR NECK GAP

CPU_50S CPU_50S CPU_27P4S CPU_50S CPU_27P4S
CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP
10 26 10 10 10 10
=100_OHM_DIFF
SPACING_RULE_SET
CLK_FSB
LAYER
*
=3x_DIELECTRIC
WEIGHT
SPACING_RULE_SET
CLK_FSB
LAYER
TOP,BOTTOM
=4x_DIELECTRIC
WEIGHT
CPU_COMP CPU_COMP
?
XDP_TDI CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP
10 13 10 13 10 13 10 13 10 13 10 13 10 13 13

XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L5
(FSB_CPURST_L)
CPU_50S CPU_50S CPU_VCCSENSE CPU_VCCSENSE CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S
CPU_8MIL CPU_8MIL CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE
11 59
11 59 11 59
SYNC_MASTER=K24_MLB
PAGE TITLE
(CPU_VCCSENSE) (CPU_VCCSENSE)
CPU/FSB Constraints
DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

100 OF 109
SHEET
8
Memory Bus Constraints
PHYSICAL_RULE_SET
MEM_40S
7
LAYER
*
6
5
DIFFPAIR NECK GAP
4
Memory Net Properties

=40_OHM_SE
MINIMUM LINE WIDTH

=40_OHM_SE
MINIMUM NECK WIDTH

=40_OHM_SE
MAXIMUM NECK LENGTH

=40_OHM_SE

=STANDARD
=STANDARD
MEM_A_CLK
MEM_70D_VDD MEM_70D_VDD
MEM_CLK MEM_CLK
MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0> MEM_A_CKE<3..0> MEM_A_CS_L<3..0> MEM_A_ODT<3..0> MEM_A_A<14..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56> MEM_A_DM<0> MEM_A_DM<1> MEM_A_DM<2> MEM_A_DM<3> MEM_A_DM<4> MEM_A_DM<5> MEM_A_DM<6> MEM_A_DM<7> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0> MEM_B_CKE<3..0> MEM_B_CS_L<3..0> MEM_B_ODT<3..0> MEM_B_A<14..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56> MEM_B_DM<0> MEM_B_DM<1> MEM_B_DM<2> MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7> MCP_MEM_COMP_VDD MCP_MEM_COMP_GND
15 27 15 27
MEM_40S_VDD
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
MEM_A_CLK
MEM_70D
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_A_CNTL MEM_A_CNTL
MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD
MEM_CTRL MEM_CTRL MEM_CTRL
15 27 15 27 15 27
MEM_70D_VDD
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_A_CNTL
MEM_A_CMD
MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD
MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD
15 27 15 27 15 27 15 27 15 27
SPACING_RULE_SET
LAYER
*
=4:1_SPACING
WEIGHT
MEM_A_CMD
MEM_CLK2MEM
?
MEM_A_CMD MEM_A_CMD
MEM_CTRL2CTRL
=2:1_SPACING
?
MEM_A_CMD
MEM_CTRL2MEM
=2.5:1_SPACING
?
MEM_A_DQ_BYTE0
MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27
MEM_CMD2CMD
=1.5:1_SPACING
?
MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3

MEM_CMD2MEM
=3:1_SPACING
MEM_DATA2DATA
=1.5:1_SPACING
?
MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5
MEM_DATA2MEM
=3:1_SPACING
?
MEM_A_DQ_BYTE6
MEM_DQS2MEM
=3:1_SPACING
?
MEM_A_DQ_BYTE7
MEM_2OTHER
25 MIL
15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27
Memory Bus Spacing Group Assignments

TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
MEM_CLK
NET_SPACING_TYPE2
MEM_CLK
AREA_TYPE
*
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
MEM_CMD
NET_SPACING_TYPE2
MEM_CLK
AREA_TYPE
*
SPACING_RULE_SET
MEM_CLK2MEM
MEM_CMD2MEM
MEM_A_DQ_BYTE6
MEM_CLK
MEM_CTRL
MEM_CLK2MEM
MEM_CMD
MEM_CTRL
MEM_CMD2MEM
MEM_A_DQ_BYTE7
MEM_CLK
MEM_CMD
MEM_CLK2MEM
MEM_CMD
MEM_CMD
MEM_CMD2CMD
MEM_A_DQS0 MEM_A_DQS0
MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D
MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS
15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27 15 27
MEM_CLK
MEM_DATA
MEM_CLK2MEM
MEM_CMD
MEM_DATA
MEM_CMD2MEM
MEM_A_DQS1
MEM_CLK
MEM_DQS
MEM_CLK2MEM
MEM_CMD
MEM_DQS
MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
MEM_A_DQS2
NET_SPACING_TYPE1
MEM_CTRL
NET_SPACING_TYPE2
MEM_CLK
AREA_TYPE
*
SPACING_RULE_SET
NET_SPACING_TYPE1
MEM_DATA
NET_SPACING_TYPE2
MEM_CLK
AREA_TYPE
*
SPACING_RULE_SET
MEM_A_DQS3
MEM_CTRL2MEM
MEM_DATA2MEM
MEM_CTRL
MEM_CTRL
MEM_CTRL2CTRL
MEM_DATA
MEM_CTRL
MEM_DATA2MEM
MEM_A_DQS4
MEM_CTRL
MEM_CMD
MEM_CTRL2MEM
MEM_DATA
MEM_CMD
MEM_DATA2MEM
MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6
MEM_CTRL
MEM_DATA
MEM_CTRL2MEM
MEM_DATA
MEM_DATA
MEM_DATA2DATA
MEM_CTRL
MEM_DQS
MEM_CTRL2MEM
MEM_DATA
MEM_DQS
MEM_DATA2MEM
MEM_A_DQS7
NET_SPACING_TYPE1
MEM_DQS
NET_SPACING_TYPE2
MEM_CLK
AREA_TYPE
*
SPACING_RULE_SET
NET_SPACING_TYPE1
MEM_CLK
NET_SPACING_TYPE2
*
AREA_TYPE
*
SPACING_RULE_SET
MEM_B_CLK
MEM_70D_VDD MEM_70D_VDD
MEM_CLK MEM_CLK
15 28 15 28
MEM_DQS2MEM
MEM_2OTHER
MEM_B_CLK
MEM_DQS
MEM_CTRL
MEM_DQS2MEM
MEM_CTRL
MEM_2OTHER
MEM_B_CNTL
MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD
MEM_CTRL MEM_CTRL MEM_CTRL
15 28 15 28 15 28
MEM_DQS
MEM_CMD
MEM_DQS2MEM
MEM_CMD
MEM_2OTHER
MEM_B_CNTL MEM_B_CNTL
MEM_DQS
MEM_DATA
MEM_DQS2MEM
MEM_DATA
MEM_2OTHER
MEM_B_CMD
MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD
MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD
15 28 15 28 15 28 15 28 15 28
MEM_DQS
MEM_DQS
MEM_DQS2MEM
MEM_DQS
MEM_2OTHER
MEM_B_CMD
Need to support MEM_*-style wildcards!
MEM_B_CMD MEM_B_CMD MEM_B_CMD
DDR2:
DQ signals should be matched within 20 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
MEM_B_DQ_BYTE0
15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28
All DQS pairs should be matched within 100 ps of clocks.

MEM_B_DQ_BYTE1
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
MEM_B_DQ_BYTE2
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

MEM_B_DQ_BYTE3
All memory signals maximum length is 1.005 ps.
CLK minimum length is 594 ps (lengths include substrate).

MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
DDR3:
DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
MEM_B_DQ_BYTE0
15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28
No DQS to clock matching requirement.

MEM_B_DQ_BYTE1
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
MEM_B_DQ_BYTE2
A/BA/cmd signals should be matched within 5 ps of CLK pairs.

MEM_B_DQ_BYTE3
All memory signals maximum length is 1.005 ps.
CLK minimum length is 594 ps (lengths include substrate).

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
MCP MEM COMP Signal Constraints

MEM_B_DQS0 MEM_B_DQS0
MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D
MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS
15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28
PHYSICAL_RULE_SET
MCP_MEM_COMP
LAYER
*

Y
MINIMUM LINE WIDTH

7 MIL
MINIMUM NECK WIDTH

7 MIL
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
DIFFPAIR NECK GAP

=STANDARD
SPACING_RULE_SET
MCP_MEM_COMP
LAYER
*
8 MIL
WEIGHT
?
MEM_B_DQS4
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7
SYNC_MASTER=K24_MLB
PAGE TITLE
Memory Constraints
DRAWING NUMBER SIZE
MCP_MEM_COMP MCP_MEM_COMP
16 16
Apple Inc.
R
051-7982
REVISION
C.0.0
BRANCH PAGE

101 OF 109
SHEET
8
PCI-Express
PHYSICAL_RULE_SET
PCIE_90D
7
LAYER
*
6
5
4
NET_TYPE PHYSICAL SPACING PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE
3
PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N
30 30 17 30 17 30 17 30 17 30

=90_OHM_DIFF
MINIMUM LINE WIDTH

=90_OHM_DIFF
MINIMUM NECK WIDTH

=90_OHM_DIFF
MAXIMUM NECK LENGTH

=90_OHM_DIFF

=90_OHM_DIFF
DIFFPAIR NECK GAP

=90_OHM_DIFF
PCIE_90D PCIE_MINI_R2D PCIE_90D PCIE_90D PCIE_MINI_D2R PCIE_90D PCIE_90D
CLK_PCIE_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
PCIE
LAYER
*
=3X_DIELECTRIC
WEIGHT
SPACING_RULE_SET
PCIE
LAYER
TOP,BOTTOM
=4X_DIELECTRIC
WEIGHT
?
?
PCIE_90D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE
PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N

9 17 9 17 9 17 9 17
CLK_PCIE
20 MIL
?
PCIE_90D PCIE_FW_R2D PCIE_90D PCIE_90D
MCP_PEX_COMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4
PCIE_FW_D2R
PCIE_90D PCIE_90D PCIE_90D PCIE_90D
MCP_PE1_REFCLK
CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D
CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE
PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N
17 30 17 30 7 30 7 30
MCP_PE4_REFCLK
CLK_PCIE_100D CLK_PCIE_100D
CLK_PCIE CLK_PCIE
PCIE_CLK100M_FC_P PCIE_CLK100M_FC_N CONN_PCIE_MINI_R2D_P CONN_PCIE_MINI_R2D_N CONN_PCIE_MINI_D2R_P CONN_PCIE_MINI_D2R_N

7 30 7 30
PCIE_90D PCIE_90D PCIE_90D
PCIE PCIE
PCIE PCIE_90D PCIE
7 30 7 30
MCP_PEX_CLK_COMP
MCP_PEX_COMP
MCP_PEX_CLK_COMP
17
Digital Video Signal Constraints

C
MINIMUM NECK WIDTH
=100_OHM_DIFF
PHYSICAL_RULE_SET
DP_100D
LAYER
*

=100_OHM_DIFF
MINIMUM LINE WIDTH

=100_OHM_DIFF
MAXIMUM NECK LENGTH

=100_OHM_DIFF

=100_OHM_DIFF
DIFFPAIR NECK GAP

=100_OHM_DIFF
LVDS_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TMDS_IG_TXC TMDS_IG_TXC
DP_100D DP_100D DP_100D DP_100D
DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P<2..0> TMDS_IG_TXD_N<2..0> DP_ML_P<3..0> DP_ML_C_P<3..0> DP_ML_N<3..0> DP_ML_C_N<3..0> DP_IG_AUX_CH_P DP_IG_AUX_CH_N DP_AUX_CH_SW_P DP_AUX_CH_SW_N DP_AUX_CH_C_P DP_AUX_CH_C_N MCP_HDMI_RSET MCP_HDMI_VPROBE
66 67 67 66 67 67 18 66 18 66 66 66 66 67 66 67
MCP_DV_COMP
20 MIL
20 MIL
=STANDARD
=STANDARD
=STANDARD
TMDS_IG_TXD TMDS_IG_TXD
SPACING_RULE_SET
DISPLAYPORT
LAYER
*
=3x_DIELECTRIC
WEIGHT
SPACING_RULE_SET
DISPLAYPORT
LAYER
TOP,BOTTOM
=4x_DIELECTRIC
WEIGHT
DP_ML
DP_100D DP_100D
DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
?
?
DP_ML
DP_100D DP_100D
LVDS
=3x_DIELECTRIC
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
LVDS intra-pair matching should be 5 mils.
Pairs should be within 100 mils of clock length. Inter-pair matching should be within 150 ps. No relationship to other signals.
DP_AUX_CH
DP_100D DP_100D DP_100D DP_100D DP_100D DP_100D
DisplayPort/TMDS intra-pair matching should be 5 ps. DIsplayPort AUX CH intra-pair matching should be 5 ps. Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
SATA Interface Constraints

MCP_HDMI_RSET
MCP_DV_COMP MCP_DV_COMP
18 24 18 24
PHYSICAL_RULE_SET
SATA_100D
LAYER
*

=100_OHM_DIFF
MINIMUM LINE WIDTH

=100_OHM_DIFF
MINIMUM NECK WIDTH

=100_OHM_DIFF
MAXIMUM NECK LENGTH

=100_OHM_DIFF

=100_OHM_DIFF
DIFFPAIR NECK GAP

MCP_HDMI_VPROBE
=100_OHM_DIFF
LVDS_IG_A_CLK
LVDS_100D LVDS_100D
LVDS LVDS LVDS LVDS LVDS LVDS
LVDS_IG_A_CLK_P LVDS_IG_A_CLK_F_P LVDS_IG_A_CLK_N LVDS_IG_A_CLK_F_N LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_N<2..0>
18 65 7 65 18 65 7 65 7 18 65 7 18 65
SATA_90D_HDD
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
LVDS_IG_A_CLK LVDS_100D LVDS_100D
SPACING_RULE_SET
SATA
LAYER
*
=4x_DIELECTRIC
WEIGHT
SPACING_RULE_SET
SATA
LAYER
TOP,BOTTOM
=3x_DIELECTRIC
WEIGHT
LVDS_IG_A_DATA LVDS_IG_A_DATA
LVDS_100D LVDS_100D
?
SATA_TERMP
8 MIL
?
I183 I182 DP_ML DP_100D DP_100D DISPLAYPORT DISPLAYPORT
DP_ML_CONN_P<3..0> DP_ML_CONN_N<3..0>
67 67
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
MCP_DV_COMP
18 24 18 24
SATA_HDD_R2D
SATA_90D_HDD SATA_90D_HDD SATA_90D_HDD SATA_90D_HDD SATA_90D_HDD SATA_90D_HDD
SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N MCP_SATA_TERMP
20 34 20 34 7 34 7 34 34 34 20 34 20 34 7 34 7 34 34 34 20 34 20 34 7 34 7 34 34 34 20 34 20 34 7 34 7 34 34 34
R
SATA_HDD_D2R
SATA_90D_HDD SATA_90D_HDD SATA_90D_HDD SATA_90D_HDD SATA_90D_HDD SATA_90D_HDD
SATA_ODD_R2D
SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP Constraints 1
DRAWING NUMBER SIZE
SATA_ODD_D2R
SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D
Apple Inc.
051-7982
REVISION
C.0.0
BRANCH PAGE
102 OF 109
SHEET
MCP_SATA_TERMP
SATA_TERMP
20
8
PCI Bus Constraints
PHYSICAL_RULE_SET
PCI_55S
7
LAYER
*
6
5
DIFFPAIR NECK GAP
4

=55_OHM_SE
MINIMUM LINE WIDTH

=55_OHM_SE
MINIMUM NECK WIDTH

=55_OHM_SE
MAXIMUM NECK LENGTH

=55_OHM_SE

=STANDARD
=STANDARD
MCP_DEBUG
PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S
PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI
MCP_DEBUG<7..0> PCI_AD<23..8> PCI_AD<24> PCI_AD<31..25> PCI_PAR PCI_C_BE_L<3..0> PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L PCI_CLK33M_MCP_R PCI_CLK33M_MCP LPC_AD<3..0> LPC_FRAME_L LPC_RESET_L LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N CONN_USB_EXTA_P CONN_USB_EXTA_N
13 19
CLK_PCI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PCI_AD PCI_AD24
PCI_AD
SPACING_RULE_SET
PCI
LAYER
*
=STANDARD
WEIGHT
PCI_AD
?
PCI_C_BE_L PCI_CNTL
CLK_PCI
8 MIL
?
PCI_CNTL
PCI_CNTL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

PCI_CNTL PCI_CNTL PCI_CNTL
D
19
LPC Bus Constraints

PHYSICAL_RULE_SET
LPC_55S
LAYER
*

=55_OHM_SE
MINIMUM LINE WIDTH

=55_OHM_SE
MINIMUM NECK WIDTH

=55_OHM_SE
MAXIMUM NECK LENGTH

=55_OHM_SE

=STANDARD
DIFFPAIR NECK GAP

PCI_CNTL PCI_REQ0_L
=STANDARD
PCI_GNT0_L
CLK_LPC_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PCI_REQ1_L PCI_GNT1_L
19
PCI_INTW_L
SPACING_RULE_SET
LPC
LAYER
*
6 MIL
WEIGHT
PCI_INTX_L
?
PCI_INTY_L PCI_INTZ_L
CLK_LPC
8 MIL
?
MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI_55S CLK_PCI CLK_PCI
19 19

LPC_AD LPC_FRAME_L
USB 2.0 Interface Constraints

PHYSICAL_RULE_SET
MCP_USB_RBIAS
LPC_55S LPC_55S LPC_55S
LPC LPC LPC
19 36 38 19 36 38 19 25
LAYER
*

=STANDARD
MINIMUM LINE WIDTH

8 MIL
MINIMUM NECK WIDTH

8 MIL
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
DIFFPAIR NECK GAP

LPC_RESET_L
=STANDARD
MCP_LPC_CLK0
CLK_LPC_55S CLK_LPC_55S
CLK_LPC CLK_LPC CLK_LPC
19 25 25 36 25 38
USB_90D
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
CLK_LPC_55S
USB_EXTA
USB_90D USB_90D
USB USB USB USB USB USB
20 35 20 35 35 35 35 35
SPACING_RULE_SET
USB
LAYER
*
=2x_DIELECTRIC
WEIGHT
SPACING_RULE_SET
USB
LAYER
TOP,BOTTOM
=4x_DIELECTRIC
WEIGHT
USB_90D USB_90D
USB_90D USB_90D
SMBus Interface Constraints

PHYSICAL_RULE_SET
SMB_55S
LAYER
*

=55_OHM_SE
MINIMUM LINE WIDTH

=55_OHM_SE
MINIMUM NECK WIDTH

=55_OHM_SE
MAXIMUM NECK LENGTH

=55_OHM_SE

=STANDARD
DIFFPAIR NECK GAP

=STANDARD
USB_CAMERA USB_90D USB_90D USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB
USB_CAMERA_P USB_CAMERA_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N CONN_USB2_BT_P CONN_USB2_BT_N USB_TPAD_P USB_TPAD_N USB_TPAD_R_P USB_TPAD_R_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N CONN_USB_EXTB_P CONN_USB_EXTB_N USB_CARDREADER_P USB_CARDREADER_N
20 65 20 65 7 65 7 65 20 30 20 30 7 30 7 30 20 44 20 44 44 44 9 20 9 20 20 35 20 35 35 35 9 20 9 20
SPACING_RULE_SET
SMB
LAYER
*
=2x_DIELECTRIC
WEIGHT
USB_90D
?
USB_BT
USB_90D USB_90D USB_90D USB_90D
HD Audio Interface Constraints

USB_90D USB_TPAD USB_90D USB_90D

PHYSICAL_RULE_SET
HDA_55S
LAYER
*

=55_OHM_SE
MINIMUM LINE WIDTH

=55_OHM_SE
MINIMUM NECK WIDTH

=55_OHM_SE
MAXIMUM NECK LENGTH

=55_OHM_SE

=STANDARD
DIFFPAIR NECK GAP

=STANDARD
USB_90D USB_90D
USB_IR
USB_90D USB_90D
SPACING_RULE_SET
HDA
LAYER
*
=2x_DIELECTRIC
WEIGHT
?
USB_EXTB
USB_90D USB_90D
MCP_HDA_COMP
8 MIL
?
USB_90D USB_90D

USB_SD USB_90D USB_90D
SIO Signal Constraints

PHYSICAL_RULE_SET
CLK_SLOW_55S
LAYER
*

=55_OHM_SE
MINIMUM LINE WIDTH

=55_OHM_SE
MINIMUM NECK WIDTH

=55_OHM_SE
MAXIMUM NECK LENGTH

=55_OHM_SE

=STANDARD
DIFFPAIR NECK GAP

=STANDARD
MCP_USB_RBIAS
MCP_USB_RBIAS
MCP_USB_RBIAS_GND SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_PULLDN_COMP PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK SPI_CLK_R SPI_CLK SPI_ALT_CLK SPI_MOSI_R SPI_MOSI SPI_ALT_MOSI SPI_MISO SPI_MISO_R SPI_ALT_MISO SPI_CS0_R_L SPI_CS0_L
20
SMBUS_MCP_0_CLK
SMB_55S SMB_55S SMB_55S SMB_55S
SMB SMB SMB SMB
13 21 39 13 21 39 21 39 21 39
SPACING_RULE_SET
CLK_SLOW
LAYER
*
8 MIL
WEIGHT
SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA
HDA_BIT_CLK
HDA_55S HDA_55S
HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA
21 49 21 21 49 21 21 21 49 21 49
SPI Interface Constraints

HDA_SYNC
HDA_55S HDA_55S
PHYSICAL_RULE_SET
SPI_55S
LAYER
*

=55_OHM_SE
MINIMUM LINE WIDTH

=55_OHM_SE
MINIMUM NECK WIDTH

=55_OHM_SE
MAXIMUM NECK LENGTH

=55_OHM_SE

=STANDARD
DIFFPAIR NECK GAP

HDA_RST_L
HDA_55S HDA_55S
=STANDARD
HDA_SDIN0
HDA_55S HDA_55S
SPACING_RULE_SET
SPI
LAYER
*
8 MIL
WEIGHT
HDA_SDOUT
HDA_55S HDA_55S
21 49 21
MCP_HDA_PULLDN_COMP
MCP_HDA_COMP
21

MCP_SUS_CLK CLK_SLOW_55S CLK_SLOW_55S CLK_SLOW CLK_SLOW
21 25 25 36
SPI_CLK
SPI_55S SPI_55S
SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI
21 38 48 48 38 21 38 48 48 38 21 38 48 48 38
R
SPI_55S SPI_MOSI SPI_55S SPI_55S SPI_55S SPI_MISO SPI_55S SPI_55S SPI_55S SPI_CS0 SPI_55S SPI_55S
SYNC_MASTER=K24_MLB
PAGE TITLE
MCP Constraints 2
DRAWING NUMBER SIZE
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REVISION
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SPI_55S SPI_55S
SPI SPI
SPI_CS1_R_L SPI_CS1_R_L_USE_MLB
103 OF 109
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8
MCP RGMII (Ethernet) Constraints
PHYSICAL_RULE_SET
MCP_MII_COMP
7
LAYER
*
6
5
DIFFPAIR NECK GAP
4

=STANDARD
MINIMUM LINE WIDTH

7.5 MIL
MINIMUM NECK WIDTH

7.5 MIL
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
=STANDARD
MCP_MII_COMP
MCP_MII_COMP MCP_MII_COMP
MCP_MII_COMP_VDD MCP_MII_COMP_GND MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1 ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R<3..0> ENET_RXD<0> ENET_RXD<3..1> ENET_RX_CTRL ENET_RXCTL_R ENET_CLK125M_TXCLK_R ENET_CLK125M_TXCLK ENET_TXD<0> ENET_TXD<3..1> ENET_TX_CTRL ENET_RESET_L ENET_MDI_P<3..0> ENET_MDI_N<3..0> ENET_MDI_TRAN_P<3..0> ENET_MDI_TRAN_N<3..0>
18 18
ENET_MII_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
MCP_MII_COMP
MCP_CLK25M_BUF0
ENET_MII_55S ENET_MII_55S
MCP_BUF0_CLK MCP_BUF0_CLK
18 32 31 32
SPACING_RULE_SET
MCP_BUF0_CLK
LAYER
*
=3:1_SPACING
WEIGHT
?
ENET_INTR_L ENET_MDIO
ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S
ENET_MII ENET_MII ENET_MII ENET_MII
18 31 18 31
ENET_MII
12 MIL
?
ENET_MDC
ENET_PWRDWN_L
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

ENET_MII_55S ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII
31 18 31 31 18 31 18 31 18 31 31
88E1116R (Ethernet PHY) Constraints

ENET_RXCLK
ENET_MII_55S ENET_MII_55S
PHYSICAL_RULE_SET
ENET_MDI_100D
LAYER
*

=100_OHM_DIFF
MINIMUM LINE WIDTH

=100_OHM_DIFF
MINIMUM NECK WIDTH

=100_OHM_DIFF
MAXIMUM NECK LENGTH

=100_OHM_DIFF

=100_OHM_DIFF
DIFFPAIR NECK GAP

ENET_RXD
ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S
=100_OHM_DIFF
ENET_RXD_STRAP ENET_RXD
SPACING_RULE_SET
ENET_MDI
LAYER
*
25 MIL
WEIGHT
ENET_MII_55S
ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII
31 18 31 18 31 18 31 18 31
?
ENET_TXCLK ENET_TXD0 ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S

ENET_TXD ENET_TXD
ENET_MII_55S
ENET_MII
18 31
ENET_MDI
ENET_MDI_100D ENET_MDI_100D ENET_MDI_100D ENET_MDI_100D
ENET_MDI ENET_MDI ENET_MDI ENET_MDI
31 33 31 33 33 33
SYNC_MASTER=K24_MLB
PAGE TITLE
Ethernet Constraints
DRAWING NUMBER SIZE
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R
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REVISION
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PHYSICAL_RULE_SET
1TO1_DIFFPAIR
7
LAYER
*
6
5
DIFFPAIR NECK GAP
4
SMC SMBus Net Properties

=STANDARD
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

0.1 MM
0.1 MM
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
7 39 7 39 39 39 39 39 7 39 7 39 39 39
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
SMBus Charger Net Properties

NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
CHGR_CSI
1TO1_DIFFPAIR 1TO1_DIFFPAIR
CHGR_CSI_P CHGR_CSI_N CHGR_CSO_P CHGR_CSO_N
CHGR_CSO
1TO1_DIFFPAIR 1TO1_DIFFPAIR
SYNC_MASTER=K24_MLB
PAGE TITLE
SMC Constraints
DRAWING NUMBER SIZE
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PHYSICAL_RULE_SET
DIFFPAIR
7
LAYER
*
6
5
DIFFPAIR NECK GAP
4
K84 SENSOR NET PROPERTIES

=STANDARD
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

0.1 MM
0.1 MM
DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR
CHGR_CSO_R_P CHGR_CSO_R_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N ISNS_CPUVTT_P ISNS_CPUVTT_N ISNS_HDD_P ISNS_HDD_N ISNS_HDD_R_P ISNS_HDD_R_N MCPTHMSNS_D2_P MCPTHMSNS_D2_N MCP_THMDIODE_P MCP_THMDIODE_N ISNS_ODD_P ISNS_ODD_N ISNS_ODD_R_P ISNS_ODD_R_N ISNS_AIRPORT_P ISNS_AIRPORT_N ISNS_AIRPORT_R_P ISNS_AIRPORT_R_N ISNS_1V5_S3_P ISNS_1V5_S3_N ISNS_1V5_S3_R_P ISNS_1V5_S3_R_N ISNS_LCDBKLT_P ISNS_LCDBKLT_N
56 56 42 42 10 42 10 42 41 41 34 47 34 47 47 47 42 42 21 42 21 42 34 47 34 47 47 47 30 47 30 47 47 47 47 58 47 58 47 47 47 68 47 68
DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR
SYNC_MASTER=K24_MLB
PAGE TITLE
K84 SPECIAL CONSTRAINTS

DRAWING NUMBER SIZE
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8
BOARD LAYERS
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
7
BOARD AREAS
NO_TYPE,BGA_P1MM
6
TABLE_BOARD_INFO
5
BOARD UNITS (MIL or MM)
MM
4
3
2
AREA_TYPE
BGA_P1MM
1
TABLE_PHYSICAL_ASSIGNMENT_HEAD
K84 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

ALLEGRO VERSION
15.5.1
SPACING_RULE_SET
DEFAULT
LAYER
*
0.1 MM
WEIGHT
NET_SPACING_TYPE1
*
NET_SPACING_TYPE2
*
SPACING_RULE_SET
NET_PHYSICAL_TYPE
MEM_40S
AREA_TYPE
BGA_P1MM
PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_ITEM
?
BGA_P1MM
STANDARD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
PHYSICAL_RULE_SET
DEFAULT
LAYER
*

Y
STANDARD
=DEFAULT
?
MEM_CLK
BGA_P1MM
BGA_P2MM
MEM_40S_VDD
BGA_P1MM
STANDARD
MINIMUM LINE WIDTH

=50_OHM_SE
MINIMUM NECK WIDTH

0.100MM
MAXIMUM NECK LENGTH

30 MM

0 MM
DIFFPAIR NECK GAP

BGA_P1MM
=DEFAULT
?
CLK_FSB
BGA_P1MM
BGA_P2MM
0 MM
BGA_P2MM
=DEFAULT
?
CLK_LPC
BGA_P1MM
BGA_P2MM
STANDARD
=DEFAULT
=DEFAULT
12.7 MM
=DEFAULT
=DEFAULT BGA_P3MM
=DEFAULT
CLK_PCI
BGA_P1MM
BGA_P2MM
PHYSICAL_RULE_SET
55_OHM_SE
LAYER
TOP,BOTTOM

Y
MINIMUM LINE WIDTH

0.090 MM
MINIMUM NECK WIDTH

0.090 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

TABLE_SPACING_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM
CLK_PCIE
BGA_P1MM
BGA_P2MM
SPACING_RULE_SET
1.5:1_SPACING
LAYER
*
0.15 MM
WEIGHT
CLK_SLOW
BGA_P1MM
BGA_P2MM
? FSB_DSTB
55_OHM_SE
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD 2:1_SPACING
FSB_DSTB
BGA_P1MM
BGA_P3MM
0.2 MM
?
PHYSICAL_RULE_SET
50_OHM_SE
LAYER
TOP,BOTTOM

Y
MINIMUM LINE WIDTH

0.115 MM
MINIMUM NECK WIDTH

0.115 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

2.5:1_SPACING
0.25 MM
?
3:1_SPACING
0.3 MM
?
50_OHM_SE
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
4:1_SPACING
0.4 MM
PHYSICAL_RULE_SET
40_OHM_SE
LAYER
TOP,BOTTOM

Y
MINIMUM LINE WIDTH

0.165 MM
MINIMUM NECK WIDTH

0.100 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SPACING_RULE_SET
2X_DIELECTRIC
LAYER
TOP,BOTTOM
0.140 MM
WEIGHT
?
40_OHM_SE
0.126 MM
0.100 MM
=STANDARD
=STANDARD
=STANDARD
3X_DIELECTRIC
TOP,BOTTOM
0.210 MM
?
4X_DIELECTRIC
TOP,BOTTOM
0.280 MM
?
PHYSICAL_RULE_SET
27P4_OHM_SE
LAYER
TOP,BOTTOM

Y
MINIMUM LINE WIDTH

0.310 MM
MINIMUM NECK WIDTH

0.310 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

5X_DIELECTRIC
TOP,BOTTOM
0.350 MM
?
2X_DIELECTRIC
0.126 MM
?
27P4_OHM_SE
0.222 MM
0.222 MM
=STANDARD
=STANDARD
=STANDARD 3X_DIELECTRIC
*
0.189 MM
?
4X_DIELECTRIC
0.252 MM
?
PHYSICAL_RULE_SET
70_OHM_DIFF
LAYER
*

N
5X_DIELECTRIC
0.315 MM
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
DIFFPAIR NECK GAP

=STANDARD
70_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
0.151 MM
0.100 MM
=STANDARD
0.224 MM
0.224 MM
70_OHM_DIFF
TOP,BOTTOM
0.185 MM
0.100 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
90_OHM_DIFF
LAYER
*

N
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
DIFFPAIR NECK GAP

=STANDARD
90_OHM_DIFF
0.095 MM
0.095 MM
0.234 MM
0.234 MM
90_OHM_DIFF
TOP,BOTTOM
0.112 MM
0.112 MM
0.220 MM
0.220 MM
PHYSICAL_RULE_SET
100_OHM_DIFF
LAYER
*

N
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
DIFFPAIR NECK GAP

=STANDARD
100_OHM_DIFF
0.075 MM
0.075 MM
0.244 MM
0.244 MM
100_OHM_DIFF
TOP,BOTTOM
0.091 MM
0.091 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
100_OHM_DIFF_HDD
LAYER
*

N
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
DIFFPAIR NECK GAP

=STANDARD
100_OHM_DIFF_HDD
0.083 MM
0.083 MM
0.400 MM
0.400 MM
100_OHM_DIFF_HDD
TOP,BOTTOM
0.095 MM
0.095 MM
0.400 MM
0.400 MM
PHYSICAL_RULE_SET
LAYER
*

N
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

=STANDARD
DIFFPAIR NECK GAP

110_OHM_DIFF
=STANDARD
110_OHM_DIFF
0.075 MM
0.075 MM
0.330 MM
0.330 MM
110_OHM_DIFF
TOP,BOTTOM
0.077 MM
0.077 MM
0.330 MM
0.330 MM
PHYSICAL_RULE_SET
1:1_DIFFPAIR
LAYER
*

Y
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

0.1 MM
DIFFPAIR NECK GAP

0.1 MM
SYNC_MASTER=K24_MLB
PAGE TITLE
K84 RULE DEFINITIONS

DRAWING NUMBER SIZE
Apple Inc.
R
051-7982
REVISION
C.0.0
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8

K84 MLB SCHEMATIC

Memory Constraints MCP Constraints 1

System Block Diagram

Power Block Diagram

LPC+SPI Debug Connector K84 SMBUS CONNECTIONS

Ethernet Constraints SMC Constraints

K24_MLB 04/06/2009 K24_MLB 01/19/2009

Current Sensing Thermal Sensors

K84 SPECIAL CONSTRAINTS

K84 RULE DEFINITIONS

K24_MLB 02/25/2009 K24_MLB 03/04/2009

CPU Power & Ground

DEBUG SENSORS AND ADC SPI ROM

K19_IMLB 02/15/2009 K24_MLB 06/09/2009

eXtended Debug Port(MiniXDP)

MCP CPU Interface

AUDIO: CODEC/REGULATOR AUDIO: LINE INPUT FILTER

AUDIO 06/09/2009 AUDIO 06/09/2009

MCP Memory Interface

MCP Memory Misc

AUDIO: HEADPHONE FILTER

MCP PCIe Interfaces

AUDI0: SPEAKER AMP AUDIO: JACK

AUDIO 06/09/2009 AUDIO 06/09/2009

MCP Ethernet & Graphics

MCP PCI & LPC

AUDIO: JACK TRANSLATORS

MCP SATA & USB

DC-In & Battery Connectors PBUS Supply/Battery Charger

K24_MLB 02/05/2009 K24_MLB

MCP HDA & MISC

MCP Power & Ground

MCP Standard Decoupling

1.5V/0.75V DDR3 SUPPLY

MCP Graphics Support

IMVP6 CPU VCore Regulator MCP CORE REGULATOR

K24_MLB 02/15/2009 K24_MLB 02/04/2009

FSB/DDR3 Vref Margining

CPU VTT(1.05V) SUPPLY

DDR3 SO-DIMM Connector A

MISC POWER SUPPLIES POWER SEQUENCING

K24_MLB 02/15/2009 K24_MLB 02/15/2009

DDR3 SO-DIMM Connector B

X16 WIRELESS CONNECTOR

LVDS CONNECTOR DISPLAYPORT SUPPORT

K24_MLB 04/06/2009 K24_MLB 04/06/2009

Ethernet PHY (RTL8211CL)

Ethernet & AirPort Support

LCD Backlight Driver (MC34845) LCD Backlight Support

VEMURI_K19I 04/06/2009 K24_MLB 04/06/2009

External USB Connectors

NOTICE OF PROPRIETARY PROPERTY:

INTEL CPU CORE 2 DUO

DC-DC POWER SUPPLIES

64-Bit 1067 MHZ

FSB INTERFACE MEMORY DDR3 1067MHZ

CPU & MCP THERMAL SENSORS

SUDDEN MOTION SENSOR

SPI Boot ROM

CURRENT & VOLTAGE SENSORS

FAN CONN AND CONTROL

LPC Conn Port80,serial

TRACKPAD/ CAMERA KEYBOARD