All digital PLL for RF transmitter

Liangge Xu, Jukka-Pekka Pöyhtäri, Saska Lindfors

Electronic Circuit Design Laboratory
Helsinki University of Technology

CROPS Workshop, Trondheim 19.-20. 9. 2006

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 Outline

 Introduction
 All digital PLL (ADPLL)
 Key building blocks
 Gain normalization block
 Digitally-controlled oscillator (DCO)
 Time-to-digital converter (TDC)
 Loop filter
 Implementation results
 Conclusions

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 Introduction

 Traditional RF transmitters are based on charge-pump PLL’s

 analog intensive circuit technology and design flow

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 All digital PLL (ADPLL)

 All digital PLL (ADPLL) as a new solution for RF transmitters

 Architecture first proposed by TI
 All building blocks have digital interfaces
 loop circuitry implemented in a fully digital manner
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All digital PLL (ADPLL)

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 All digital PLL (ADPLL)
 PLL transverse three modes of
operation during settling
 PVT-calibration mode : to calibrate
large frequency uncertainty due to
process-voltage-temperature (PVT)
variations

 Acquisition mode : to acquire the

requested operational channel

 Tracking mode : to track the

frequency reference and perform
data modulation

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 All digital PLL (ADPLL)
 Two-point modulation employed for data modulation
 Truly wide-band modulation

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Gain normalization block

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 Gain normalization block

 Normalized DCO has unity gain in terms of reference

frequency
 DCO gain continuously tracked and calibrated during
modulation phase with a simple hardware implemented
LMS algorithm

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Digitally controlled oscillator (DCO)

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 Digitally controlled oscillator (DCO)

 A digital equivalent of highly

linear VCO with wide
dynamic frequency range
 Feasible dynamic range
>800MHz @2.4GHz center
frequency

 DCO as a system includes a

DCO ASIC cell with the
tightly coupled peripheral
digital circuitry

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 Digitally controlled oscillator (DCO)

 DCO core is a differential LC tank oscillator

 Digital control realized by switching capacitance devices

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 Digitally controlled oscillator (DCO)

 DCO core implementation

 PVT bank uses switched
fringe capacitors
 Acquisition bank and tracking
bank use MOS varactors
 Cross-coupled NMOS gain
stage as negative resistance
 Digital control for both
frequency tuning and
current biasing

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 DCO interface logic
 Dynamic element matching (DEM) to improve linearity in
digital-to-frequency conversion

 Sigma-delta modulation to enhance frequency resolution

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DCO interface logic

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Time-to-digital converter (TDC)

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 Time-to-digital converter (TDC)

TI architecture
Timing critical paths Our architecture
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Time-to-digital converter (TDC)

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 Time-to-digital converter (TDC)
 The TDC is to give the fractional part of a fixed-point
representation of the DCO output frequency

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Time-to-digital converter (TDC)

TI architecture Architecture we use

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Loop filter

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 Loop filter
 Digital Low-pass filter with configurable two branches
 Unconditional stable 4th order cascade-form IIR filter as the main
branch
 Integral accumulator branch to further suppress the DCO flicker noise

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 Implementation results
Input to DCO PVT bank
 PLL total settling time about 15us 155
150

with 26MHz reference clock 145

dp
140
 about 1us used in PVT mode 135

 about 4us used in ACQ mode 130

0 100 200 300 400 500 600

 about 10us for tracking mode Input to DCO acquisition bank
settling 134

132

 Initial synthesis results (excluding 130

da
DCO and TDC core) using 65nm
128

technology
126
0 100 200 300 400 500 600

Input to DCO tracking bank

 Cell area : approx. 0.05 mm2 138
136
 Cell count : approx. 10,000 134

dt (dti+dtf)
 Total dynamic power : approx. 17mW 132
130

Cell leakage power : approx. 0.18mW 128

126
0 100 200 300 400 500 600
CKR clock cycle

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 Implementation results
 TDC core implementation results (after first layout)
 Area ~0.001mm², power consumption ~2mW, time resolution ~18-20
ps

 DCO core implementation

results (after first layout)
 Occupied area :
200umX320um
 Frequency tuning range :
approx. 2.3~2.6GHz
 Phase noise :
127dBc @ 1MHz relative
frequency with 6mA
biasing current

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 Implementation results

DCO
core layout

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 Conclusions
 An ADPLL architecture has been presented
 Our implementation status
 Initial RTL synthesis for the digital logic
 Initial layout for the DCO core
 Initial layout for the TDC core
 Next step in implementation
 More iterations of RTL synthesis for further optimization
 Layout of the digital logic
 Optimization of TDC and DCO core layout

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 References
[1] R. B. Staszewski et al., “A first digitally controlled oscillator in a deep-submicron
CMOS process for multi-GHz wireless applications, ” IEEE 2003
[2] R. B. Staszewski et al., “All-digital TX frequency synthesizer and discrete-time
receiver for Bluetooth radio in 130-nm CMOS,” IEEE 2004
[3] R. B. Staszewski et al., “All-digital PLL and transmitter for mobile phones,” IEEE
2005
[4] R. B. Staszewski et al., “All-digital PLL and GSM/EDGE transmitter in 90nm
CMOS,” IEEE 2005

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