Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Field Programmable Gate Arrays (FPGA)

Presentation at the Seminar Embedded System Architecture at the University of Innsbruck

Christian Baumann

January 14, 2010

Christian Baumann

Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Introduction FPGA structures Basic structure Modern FPGAs

Xilinx Virtex-6 family

Conguring FPGAs An FPGA implementation

Christian Baumann

Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

FPGAs and ASICs

Field-Programmable Gate Arrays (FPGAs) are pre-fabricated silicon devices that can be electrically programmed to become almost any kind of digital circuit or system [2]. Application Specic Integrated Circuits (ASIC) are designed for specic application using CAD tools and fabricated at a foundry. Advantages of FPGAs:
Conguring a FPGA using a hardware description language (HDL) is faster than developing an ASIC. It is possible to recongure an FPGA.

Disadvantages of FPGAs:
The same application needs more space (transistors) on chip and the application runs slower on a FPGA as modern as the ASIC counterpart.
Christian Baumann Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

FPGAs and ASICs

FPGAs are increasingly applied to high performance embedded systems.

Due to the increase of transistor density FPGA were getting more powerful over the years. The development of ASICs was getting slower and more expensive.

Christian Baumann

Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Basic structure Modern FPGAs

Basic building blocks

CLB The Congurable logic blocks are were the user specic functions are calculated. IOB The Input/Output block make it possible to connect the FPGA to the other elements of the application. Interconnect Interconnect is essential for writing between CLB and from IOBs to CLBs.

Christian Baumann

Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Basic structure Modern FPGAs

CLB

Figure: Control logic block [1]

Christian Baumann Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Basic structure Modern FPGAs

Interconnect

Figure: Programmable interconnect [1]

Christian Baumann Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Basic structure Modern FPGAs

IOB

Figure: Input/Output block [1]

Christian Baumann Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Basic structure Modern FPGAs

Modern FPGAs

Memories. Logic blocks for arithmetic calculations: e.g. multiplication Digital signal processors (DSP) Microprocessors Soft cores directly build on the FPGA fabric.

Christian Baumann

Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Basic structure Modern FPGAs

Xilinx Virtex-6 family

3 sub-families:
Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial connectivity Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity

CLBs possess a LUT which can be congured as one 6-input LUT or two 5-input LUTs. Between 156 and 1064 dual-port block RAMs, each storing 36 Kbytes. Many dedicated, full-custom, low-power DSP slices Between 8 and 72 gigabit transceiver circuits. Integrated interface block for PCI Express technology
Christian Baumann Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Basic structure Modern FPGAs

XC6VHX5651

Logic cells 566784

CLB slices 88560

DSP48E1 slices 864

Total memory 32Mb

Table: XC6VHX5651 features

Christian Baumann

Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Conguring FPGAs
Hardware description language (HDL)
Most common approach to congure a FPGA. VHDL, Verilog Several block of hardware running in parallel are described The wires for data movement have to be explicitly written on the FPGA Synthesis tools translate the code into bit stream, which is downloaded to the FPGA

High level language

SystemC is a C++ library that allows to specify and simulate hardware processes using a C++ syntax. Handel-C is an extended subset of ANSI C that allows developer to specify their designs with C. With Accelchip it is possible to generate VHDL or Verilog code block for common MATLAB DSP functions.
Christian Baumann Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Conguring FPGAs

Library-based solution
Parameterized macros to generate code for common blocks such as arithmetic functions or specialized memories The output of the macros is HDL code that can be included in the developers synthesis process.

Christian Baumann

Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

An FPGA implementation of a exible, parallel image processing architecture [3]

Vision system such as vehicle detection and security systems. After acquisition of the image, a signicant amount of computation is require in the pre-processing phase before the features are extracted and classied. Computation contain ne-grained parallelism Implemented on a Xilinx Virtex-2 FPGA

Christian Baumann

Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Image pre-processor

Figure: Image Pre-Processor

Christian Baumann

Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Pre-processing element

Figure: Pre-processing element

Christian Baumann Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Complete vision system

Figure: Complete vision system

Christian Baumann Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Implementation
Celoxica RC1000-PP board with a Xilinx Virtex FPGA. 256x256-pixel sensor connected to the board via external I/O The board communicates with the host via a PCI bus Clock frequency: 50 MHz Performance optimization compared with a software implementation executed on a PC (processor clock frequency 266 MHz):
FPGA: 125 Frames/s PC: 50 Frames/s Optimization mainly due to the parallelism of the architecture

Christian Baumann

Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

References
M. Michael Vai David R. Martinez, Robert A. Bond. High Performance Embedded Computing Handbook. CRC Press, 2008. Jonathan Rose Ian Kuon, Russel Tessier. Fpga architecture: Survey and challenges. Foundations and Trends in Electronic Design Automation, 2007. Peter Lee Stephanie McBader. An fpga implementation of a exible, parallel image processing architecture suitable for embedded vision system. IEEE, 2003.
Christian Baumann Field Programmable Gate Arrays (FPGA)

Outline Introduction FPGA structures Conguring FPGAs An FPGA implementation

Questions?

Thank you for your attention. Questions?

Christian Baumann

Field Programmable Gate Arrays (FPGA)