MANCHESTER METROPOLITAN UNIVERSITY

BSc. (Hons) Applied Computing

A Simple Simulator for a Basic

Microprocessor
Author:
Marek Repak

Supervisor:
Mohammad Hammoudeh

No part of this project has been submitted in support of an application for

any other degree or qualification at this or any other institute of learning.
Apart from those parts of the project containing citations to the work of
others, this project is my own unaided work.
Signed: _____________________

Abstract
Microprocessor are generally very complicated integrated circuit chips which are difficult subject to teach. It is an
important topic in computer architectures as it is the fundamental part of every computer system. Possibility of large
calculations in a small amount of time, programming capabilities and the potential to communicate with other devices
has increased the scale of applications the microprocessor has been used in. At the present time every intelligent
electronic device such as a mobile phone or a navigation system does contain some kind of microprocessor. As a result
of this every computer science student should know the general architecture of microprocessor and how it manages
and processes data, and controls other parts of the system. Many methods for teaching microprocessors have been
proposed, one important method is simulation. Cambridge Advanced Learner's Dictionary [2008] defines a
simulation as
a model of a set of problems of events that can be used
to teach someone how to do something, or the process of
making such a model
However, pure theoretical teaching of the subject does not fully clarifies what the student is expected to understand,
and this is the time when simulation comes in, to bridge the gap between the theory and the real word. One of the
most valuable feature of simulation is that students have an opportunity to apply their theoretical knowledge in a safe
realistic environment. Microprocessor simulation reveals real situations of inner microprocessor processes. The
advantage of simulation is that user has a capability to graphically illustrate the whole process and display the internal
state at any time of the execution. Additionally, instructions can be executed step-by-step method which stops the
execution after each instruction, thus students have an opportunity to identify the changes that have been made after
each step.

Acknowledgements
People who have contributed to this project and I would like to thanks are:

Dr. Mohammed Hammoudeh, for his supervision of this project, and providing me with guidance and
suggestions throughout.

Sarah Rogers, for proofreading the report and for providing me with useful feedback.

Contents
1

Introduction
1.1
1.2
1.3
1.4
1.5

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Literature Review
2.1
2.2
2.3
2.4
2.5

2.6
2.7
2.8

What is Microprocessor? . . . .
What is Simulation? . . . . . .
Why use Simulation? . . . . . .
Simulation in Educational Context
Methodology . . . . . . . . .

Introduction . . . . . . . . . . . . . . .
Simulation in Education. . . . . . . . . .
Conclusion . . . . . . . . . . . . . . .
Introduction to Microprocessor Architecture
Microprocessor 6502 . . . . . . . . . . .
2.5.1
Arithmetic Logic Unit Architecture.
2.5.2
Add Operation Design . . . . . .
2.5.3
Register Architecture . . . . . . .
2.5.4
3-bit Register Design . . . . . . .
2.5.5
Control And Timing . . . . . . .
2.5.6
Clock Generator Design . . . . .
2.5.7
Memory Architecture . . . . . .
Compiler Architecture . . . . . . . . . .
Instruction Set Architecture . . . . . . . .
Review of Existing Simulators . . . . . . .
2.8.1
GNUSim8085 . . . . . . . . . .
2.8.2
Gsim85 . . . . . . . . . . . . .
2.8.3
Microprocessor Simulator 5 . . . .
2.8.4
Emu8086 . . . . . . . . . . . .
2.8.5
Microprocessor 8085 Simulator 3 .
2.8.6
Conclusion . . . . . . . . . . .

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Design and Analysis

3.1
3.2
3.4
3.5

3.6

Introduction . . . . . . . . . . . . . .
Iterative & Incremental Model . . . . . .
Simulator Design . . . . . . . . . . . .
Microprocessor Design . . . . . . . . .
3.5.1
Control and Timing . . . . . .
3.5.2
Register Design . . . . . . . .
3.5.3
Instruction Set Design . . . . .
3.5.4
External Memory Design . . . .
3.5.5
Memory Stack Design . . . . .
3.5.6
Arithmetic Logic Unit Design . .
Assembly Language Syntax and Compiler .
3.6.1
Assembly Language Syntax. . . .

1
1
2
2
3

5
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39

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57

3.7

3.5.2
Compiler Design . . . . . . . . . .
Graphical User Interface . . . . . . . . . .
3.7.1
Main Menu Layout . . . . . . . . .
3.7.2
Status Panel and Memory Map Layout

Implementation
4.1 Simulator operation. . . . . . . . . . .
4.2 Timing Implementation. . . . . . . . .
4.2.1
Clock Rate . . . . . . . . . .
4.2.2
Clock Thread . . . . . . . . .
4.2.3
Thread Implementation. . . . .
4.3 Register Implementation . . . . . . . .
4.4 Number Base Conversions . . . . . . .
4.5 Memory Implementation . . . . . . . .
4.6 Stack Implementation . . . . . . . . .
4.7 Arithmetic Logic Unit Implementation . .
4.8 Microprocessor Implementation . . . . .
4.8.1
Instruction Execution . . . . .
4.8.2
Register Transfer Operation . . .
4.8.3
Arithmetic Operation . . . . . .
4.8.4
Control Flow Instruction . . . .
4.9 Graphical User Interface Implementation .
4.9.1
GTK+ Toolkit . . . . . . . . .
4.9.2
Glade . . . . . . . . . . . . .
4.9.3
gtkmm and Glade . . . . . . .
4.9.4
Signals . . . . . . . . . . . .
4.9.5
Invoking Compiler . . . . . . .
4.9.6
Simulation. . . . . . . . . . .
4.10 Compiler . . . . . . . . . . . . . . .

Software Testing
5.1

5.2

5.3
6

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58
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First Simulation . . . . . . . . . . . .
5.1.1
Data Transfer Instructions. . . .
5.1.2
Arithmetic and Logic Operations.
5.1.3
Register Overflow . . . . . . .
5.1.4
Overflow Detection . . . . . .
5.1.5
Control Flow Instructions . . . .
5.1.6
Engaging Memory . . . . . . .
Simulation Analysis. . . . . . . . . . .
5.2.1
Speed Analysis . . . . . . . . .
5.2.2
Clock Rate Analysis . . . . . .
Reverse Code Engineering . . . . . . .

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Evaluation
6.1
6.2

6.3

Aims and Objectives . . . . .

Feedback . . . . . . . . . .
6.2.1 Feedback Form . . . .
6.2.2 Evaluation on Feedback .
Further Work . . . . . . . .

85
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89
90
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93
94
94
97
104
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109
111
112
112
113

Appendices
A

Terms of Reference
A.1 Project Background.
A.2 Aims . . . . . . .
A.3 Objectives . . . . .
A.4 Project Deliverables

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115
115
116
116
117

Instruction Set

118

Solutions

126

D Feedback
128
D.1 Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
D.2 Sample Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
E

Requirements
C.1 Tools . . . . . . .
C.2 Libraries . . . . .
C.2.1 Running Simulation
C.2.2 Gtkmm . . . . . .
C.2.3 Libglademm . . . .
C.2.4 Boost . . . . . . .

Installation
133
D.1 Source Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
D.2 Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

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131
131
131
131
131
132
132

G CD Contents
134
G.1 Project Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
G.2 micp-sim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
G.3 Assembly Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
References

135

iv

List of Figures
1.1

Computer based system depicting the flow of information . . . . . . . . . . . . . . . . . . .

2.1
2.2
2.3
2.4
2.5
2.6

User interface of interactive animation software . . . . . . . . . . . . . . . . . . . . . . . .

Internal architecture of MOS Technology 6502 microprocessor . . . . . . . . . . . . . . . . .
3-bit ALU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Truth table determining the operation for ALU . . . . . . . . . . . . . . . . . . . . . . . .
Block scheme of add block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Truth table of 3-bit adder. A, B and C are the input variables. Inputs are mapped into Carry and Sum
output variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic gates performing addition. None of the inputs is on and correctly none of the outputs is flashing .
Karnaugh Map with 4 variables and minimalised groups . . . . . . . . . . . . . . . . . . . . .
Karnaugh map of SUM and CARRY output variables . . . . . . . . . . . . . . . . . . . . . .
Minimalised model of logic gates performing addition. Two input variables (B and C) and correctly
only Carry is set to 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addition function engaging EXOR, AND and OR gates. All three input variables are set and both Carry
and Sum are correcly indicating logical 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding two 3-bit numbers (1 + 3 = 4) by using integrated circuits . . . . . . . . . . . . . . . . .
6-bit adder. 5 inputs are set 1 and only one input (D) is switched off. 1 + 1 + 1 + 1 + 1 equals 5 which is
in binary 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block diagram of an 8-bit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flip-flop transition diagram. First bit is the Input variable, second bit denotes the Write protection bit
and the last bit is the Clock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Truth table of register based on the transition diagram. . . . . . . . . . . . . . . . . . . . . .
Karnaugh map for Qn state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A simple flip-flop holding 1 bit of information. The current state is 1 (state flashing). Input and Clock is
set to 0 and only Load bit is set 1. The state will change as soon as clock bit has occurred at the input . .
3-bit register. 3 Input bits defines the value to be stored in the register . . . . . . . . . . . . . . .
Clock signal with frequency 2Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Astable multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulated astable flip-flop (multivibrator) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output signal produced by astable flipflop (node 10) . . . . . . . . . . . . . . . . . . . . . .
A simple current amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normalised output signal (node 14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparison of the output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block diagram of a memory unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block diagram of a memory and associated registers . . . . . . . . . . . . . . . . . . . . . . .
Block diagram of compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction execution cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Different ISA approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GNUSim8085 User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction keypad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User interface of Gsim85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gsim85 Keypad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MS5 user interface with memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8
11
12
12
13

2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
2.27
2.28
2.29
2.30
2.31
2.32
2.33
2.34
2.35
2.36

13
14
14
15
15
16
16
17
17
18
18
19
19
20
21
21
22
22
23
23
24
24
25
26
27
28
29
30
31
31
32

2.37
2.38
2.39
2.40

Additional devices implemented in the simulator (animations)

Simulation of stepped motor in Emu8085 . . . . . . . . .
Screenshot of Microprocessor Simulator 3 . . . . . . . . .
Timing diagram of ADD M instruction . . . . . . . . . .

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33
34
36
37

3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27

Iterative & Incremental development model . . . . . .

High-level operation of the simulator . . . . . . . . .
Loading instructions into memory . . . . . . . . . .
Procedure of loading instruction into memory . . . . .
Instruction execution flow chart . . . . . . . . . . .
Block diagram of the microprocessor . . . . . . . . .
8-bit register diagram . . . . . . . . . . . . . . . .
16-bit register diagram . . . . . . . . . . . . . . .
Instruction design . . . . . . . . . . . . . . . . .
Interval defining the set of available addresses . . . . .
Memory architecture . . . . . . . . . . . . . . . .
Memory architecture in cubic expressed in cubic form . .
Memory write operation . . . . . . . . . . . . . . .
Memory read operation . . . . . . . . . . . . . . .
Fundamental architecture of a stack . . . . . . . . . .
Stack design . . . . . . . . . . . . . . . . . . . .
Stack push operation . . . . . . . . . . . . . . . .
Stack pop operation . . . . . . . . . . . . . . . . .
Evaluation of expression A + B + C . . . . . . . . . .
Evaluation of expression A B + C D E . . . . . .
Arithmetic logic unit architecture . . . . . . . . . . .
Flowchart of subtraction procedure . . . . . . . . . .
First compiler run procedure . . . . . . . . . . . . .
Second compiler's run and machine code generation . .
User interface design layout . . . . . . . . . . . . .
Main menu options . . . . . . . . . . . . . . . . .
Register, Stack and Memory map interface layout design .

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40
41
41
42
43
44
45
46
46
49
49
49
50
51
51
52
53
53
54
54
55
56
59
60
61
62
62

4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15

High-level operation of the simulator . . . . .

Instruction execution procedure . . . . . . .
Clock generator, description of the signal . . .
Simulation processes depicting the clock thread.
Clock class diagram . . . . . . . . . . . . .
Register class diagram . . . . . . . . . . . .
Memory class diagram. . . . . . . . . . . .
Read operation procedure . . . . . . . . . .
Write operation procedure . . . . . . . . . .
Stack memory diagram . . . . . . . . . . .
ALU class diagram . . . . . . . . . . . . .
Microprocessor class diagram . . . . . . . .
Glade user interface . . . . . . . . . . . . .
Content of XML file produced by Glade . . . .
Compiler output shown in the text box widget .

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64
65
65
66
67
68
70
70
71
72
73
74
79
79
81

5.1

Content of first.as file. The script load register AH with value 45 dec, register B with value 30dec. Then it
adds register AL and AH, and subtracts the value B from register AL . . . . . . . . . . . . . . . 85
Compilation command fist.as file contains the assembly source code to be translated into binary
form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.2

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vi

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5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20

6.1

Content of the first.bc file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Example 2 results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Example 2 results. Notice AL register contains 66 . . . . . . . . . . . . . . . . . . . . . . . 89
Stack approach solving the expression. Notice the address 0x00 in the stack and the content of AL
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Bit substitution. Bits 0 up to 8 represent the register. The first row is an empty register. The second
row tries to insert number 300 and the last row shows the actual value stored . . . . . . . . . . . 90
The left image shows the content of B register(6 dec) and the image on the right hand side the carry bit
set to 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
B correctly stores 5 iterations as the register C was loaded with decimal value 5 . . . . . . . . . . 92
AL register stores the sum of B value that is performed in each iteration. AH register is used to store
the number of iterations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
The higher 8 bits contain value 0Dh and the lower 8 bits the transferred value 50h . . . . . . . . . 93
The address location 0x1000 stores ABCD and the address 0x0001 stores EF00 . . . . . . . . . . 94
The graph shows the relation between the frequency and duration of simulation of Sample 1 . . . . 99
The graph shows the reached delays at all frequencies by Sample 1. . . . . . . . . . . . . . . . 99
The graph shows the relation between the frequency and duration of simulation of Sample 2 . . . . 101
The graph shows the reached delays at all frequencies from by Sample 2 . . . . . . . . . . . . . 101
The graph shows the relation between the frequency and duration of simulation of Sample 3 . . . . 103
The graph shows the reached delays at all frequencies by Sample 3 . . . . . . . . . . . . . . . . 103
Error progression for all samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Screenshot showing the state of memory after the simulation. The interested locations inside the red
box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
MICP-SIM user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

vii

List of Tables
2-1
2-2

Computer architecture and Organisation curriculum . . . . . . . . . . . . . . . . . . . . . . 9

Summary of reviewed simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5-1
5-2
5-3
5-4
5-5
5-6

Timing statistics if simulated script (using registers) . . . . . . . .

Timing statistics of simulated script (using stack) . . . . . . . . .
S1, S2 and S3 are assembly scripts and only contain NOP instructions
Sample 1 measured values . . . . . . . . . . . . . . . . . . . .
Sample 2 measured values . . . . . . . . . . . . . . . . . . . .
Sample 3 measured values . . . . . . . . . . . . . . . . . . . .

viii

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95
96
97
98
100
102