Basics of Low Power Circuit and Logic Design

Basics of Low Power Circuit and Logic Design
Anantha Chandrakasan Massachusetts Institute of Technology
High Performance Processors

Microprocessor Power
(source ISSCC) 30 Power (Watt)
20
10
0 75
80
85 Year
90
95
Anantha Chandrakasan 1997
Portable Devices
Required Portable Functions
s
Radio transceiver Modem Voice I/O Pen Input Text/Graphics Processing Text/Graphics display Video decompression Full-motion video display
Battery (40+ lbs)
How to get 8 hours of operation ???

Basics of Low Power Circuit and Logic Design Anantha Chandrakasan 1997 3
Battery Trends
Nominal Capacity (Watt-hours / lb) 50 40 Ni-Metal Hydride 30 20 Nickel-Cadmium 10 0 Rechargable Lithium
65
70
75
80 Year
85
90
95
(from Jon Eager, Gates Inc. , S. Watanabe, Sony Inc.)

Where Does Power Go in CMOS?
Dynamic or switching currents

Charging and discharging parasitic capacitors
Short-circuit or direct-path currents

Direct path between supply rails during switching
Leakage currents
Reverse bias diode leakage Sub-threshold conduction
Static currents
Dynamic Power of a CMOS Gate

Vdd E0->1 = CLVdd2 PMOS NETWORK isupply
A1 AN
Vout NMOS NETWORK
CL
Vdd T T E 0 1 = P ( t )dt = V dd i supply ( t )dt = V dd C L dV out = C L V dd 2 0 0 0 T T Vdd 1 2 E cap = P cap ( t )dt = V out i cap ( t )dt = C L V out dV out = -- C V dd 2 L 0 0 0
Modication for Circuits with Reduced Swing

Vdd Vdd Vdd -Vt CL
E 0 1 = C L V dd ( V dd V t )
Can exploit reduced swing to lower power (e.g., reduced bit-line swing in memory)
Physical Capacitance of an Inverter

50.0
Capacitance, fF
40.0
Cjunction + Cgate
30.0
Cjunction
20.0
10.0
Cgate
0.0 0.8
1.0
1.2
1.4
1.6
1.8
2.0
VDD
Important to account for capacitive non-linearities in power estimation

Node Capacitance is a Function of Voltage

110
Switched Capacitance, fF
100 90 80
LCLR
TSPCR 70 60 50 0.8 C2MOS
0.9
1.0
1.1
1.2
1.3
1.4
1.5
VDD, V
Node Transition Activity and Power

Consider switching a CMOS gate for N clock cycles
E N = C L V dd 2 n ( N ) EN : the energy consumed for N clock cycles n(N): the number of 0->1 transition in N clock cycles EN 2 n(N ) P avg = lim -------- f clk = lim ------------ C V dd f clk N N N N L 0 1 = n(N ) lim -----------N N
P avg = 0 1 C V dd 2 f clk L
10
Factors Affecting Transition Activity, 0->1

Static component (does not account for timing)
Type of Logic Function (NOR vs. XOR) Type of Logic Style (Static vs. Dynamic) Signal Statistics Inter-signal Correlations
Dynamic or timing dependent component

Circuit Topology Signal Statistics and Correlations
11
Type of Logic Function: NOR vs. XOR

Example: Static 2 Input NOR Gate Assume: p(A=1) = 1/2 p(B=1) = 1/2 Then: p(Out=1) = 1/4 p(01) = p(Out=0).p(Out=1) = 3/4 1/4 = 3/16
A 0 0 1 1
B 0 1 0 1
Out 1 0 0 0
Truth Table of a 2 input NOR gate
0->1 = 3/16
12
Type of Logic Function: NOR vs. XOR

Example: Static 2 Input XOR Gate Assume: p(A=1) = 1/2 p(B=1) = 1/2 Then: p(Out=1) = 1/2 p(01) = p(Out=0).p(Out=1) = 1/2 1/2 = 1/4
A 0 0 1 1
B 0 1 0 1
Out 0 1 1 0
Truth Table of a 2 input XOR gate
0->1 = 1/4
13
Type of Logic Style: Static vs. Dynamic

Vdd A CLK Vdd
A CL CLK
CL
Power is only dissipated when Out=0!

STATIC NOR DYNAMIC NOR
0->1 = 3/16
N0 3 0 1 = ------- = -N 4 2
Anantha Chandrakasan 1997 14
Another Logic Style: Dynamic DCVSL

Vdd OUTB IN INB I Vdd
OUT
Guaranteed transition for every operation! 0->1 = 1
15
Inuence of Signal Statistics on 0->1
p0->1
B
0.2 2 P0->1 0.1 .1 0 0
1 0.8 0.6 PB 0.4 0.4 PA 0.6 0.2 0.8 10
CL
0.2
pb
pa
p1 = (1-pa) (1-pb)
p0->1 = p0 p1 = (1-(1-pa) (1-pb)) (1-pa) (1-pb)
0->1 is a strong function of signal statistics

Inter-signal Correlations
A B C Z B (b) Logic circuit with reconvergent fanout pZ = p(C=1|B=1) p(B=1) p0->1 = 0 A C Z
(a) Logic circuit without reconvergent fanout p0->1 = (1- pa pb) pa pb = 3/16
Need to use conditional probabilities to model inter-signal correlations! CAD tools required for such analysis
Dynamic or Glitching Activity in CMOS
Cin
Add0 S0
Add1 S1
Add2 S2
Add14 S14
Add15 S15
Sum Output Voltage, Volts
4.0
4 S15
6 2.0 Cin 5 S1 0.0 0 5 10 2 3 S10
Time, ns
0->1 can be > 1 due to glitching!

Glitch Reduction Using Balanced Paths

F A1 A2 A3 A4 A5 A6 A7
A0
Ripple
A0 A1 A2 A3 A4 A5 A6 A7
Lookahead
19
Comparison of Adder Topologies

Power-Delay-Product-1 16 bit Ripple Carry Carry Lookahead Carry Bypass Carry Select Conditional Sum 3.09 10.0 5.45 4.44 3.82 32 bit 0.81 3.54 2.39 2.08 1.23 64 bit 0.27 1.76 0.99 1.00 0.42
Logic Transition Histogram
from [Callaway92] (VLSI Signal Processing, V)
20
Glitching at the Datapath Level

A A B C D B
+ +
Tree vs. Chain
C D
+ +
+
(A + B) + C + D
(A + B) + (C + D)
Inputs Normalized # of Transitions

Tree Chain
4 8
1 1
1.45 2.5
Can be reduced by reducing the logic depth and balancing signal paths
Short-circuit Component of Power

Vdd
Vin CL
Vout
0.15
IVDD (mA)
0.10
0.05
0.0
1.0
2.0 3.0 Vin (V)
4.0
5.0
22
Short-Circuit Current vs. Load Capacitance
from [Veendrick84] (IEEE Journal of Solid-State Circuits, August 1984)
23
Minimizing Short-circuit Power

0.5 0.4 E / E(tRin=0) 0.3 0.2 0.1 0.0 0.0 0.5 1.0 tRin/tRout Vdd = 3V 1.5 2.0 Device Sizes: W/LP = 7.2m/1.2m W/LN = 2.4m/1.2m Vdd = 5V
Keep the input and output rise/fall times the same (< 10% of Total Consumption)
from [Veendrick84] (IEEE Journal of Solid-State Circuits, August 1984)
If Vdd < Vtn + |Vtp| then short-circuit power can be eliminated!

Reverse Biased Diode Leakage

GATE
p+
p+ N
Reverse Leakage Current +
V - dd
IDL = JS A
JS = 1-5pA/m2 for a 1.2m CMOS technology Js double with every 9oC increase in temperature
Subthreshold Leakage Component

10-2 10-3 10-4 10-5 10-6
ID, A
VT = 0.1V
VT = 0.4 V VGS + -
VDS=1V ID
10-7 10-8 10-9
10-10 10-11 10-12 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VGS, V
Leakage control is critical for low-voltage operation

Static Power
Vdd
Istat Vout CL
Vin=5V
Pstatic = p(In=1).Vdd . Istat
Not a function of switching frequency
27
Ultra Low Power System Design

System Algorithm Architecture Circuit/Logic Technology
Design partitioning, Power Down Complexity, Concurrency, Locality, Regularity, Data representation Concurrency, Instruction set selection, Signal correlations, Data Representation Transistor Sizing, Logic optimization, Activity Driven Power Down, low-swing logic, adiabatic switching Threshold Reduction, Advanced packaging
Lower Supply Voltage and Switched Capacitance

Signal Processing Attributes

Throughput constrained computing
- 30ms refresh rate requirement for video - Optimize power supply voltages
Time-varying computational requirements

- Adaptive signal processing techniques
Knowledge of signal statistics

Transition Probability
4000
water all year
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 5 10 15
Speech Data
2000
Sign-extension
-2000
-4000
Time
Bit Number
Energy Efciency Metric: Fixed Throughput

Example: Video Compression
P = ( (NiCiVdd2)) fsample
Energy/Sample
fsample is xed
For this mode (most DSP applications), minimizing energy/sample is both Energy and Power Efcient
30
Energy Efciency Metric: Max Throughput

Process Queue
from [Burd95] (HICSS 95)
Energy/operation Power ETR ------------------------------------ = -----------------------------------Throughput Throughput 2

A lower ETR (higher efciency) indicates lower energy for constant throughput, or higher throughput for constant energy
Other metrics such as E x D,

see [Horowitz94], (1994 Symposium on Low-power Electronics)
Supply Voltage Scaling

7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0
NORMALIZED DELAY
multiplier clock generator
2.0m technology
Td =
CL Vdd I
I ~ (Vdd - Vt)2
ring oscillator microcoded DSP chip adder adder (SPICE) 2.0 4.0 6.0
Td(Vdd=1.5) Td(Vdd=5)
(1.5) (5 - 0.7)2 (5) (1.5 - 0.7)2
Vdd (volts)
Lowering Vdd reduces energy but increases delays

Technology Based Voltage Scaling
Vdd
Vin Vout Vout CL 0.9Vdd VDSAT 0.1Vdd

Fall Time:
2
V in
1 +
V 1 const. dd -1
time
from [Kakumu90] (IEEE Tran. on Electron Devices)
Power Supply Voltage: V dd (V)
Exploit velocity saturated sub-micron devices to lower voltage without signicant loss in device speed Technology based Optimal Vdd: 2.43V for 0.3m CMOS
Supply Voltage Scaling Using VT Reduction

1.5 1.25 1.0
tpd=420pS
tpd=645pS tpd=840pS
VDD,V
0.75 0.5 0.25 0.0 0.05 0.15 0.25
0.35
0.45
VT, V
Threshold voltage reduction enables voltage scaling without performance loss

Optimizing Continuous Mode Circuits

1.25
tpd=420pS
1.00
VDD=1.02V VDD=0.55V
VDD=1.4V
Energy (pJ)
0.75
VDD=1V VDD=0.67V
0.50 0.25 0.0 0.05
VDD=0.34V
tpd=840pS
0.15
0.25 VT (V)
0.35
0.45
Optimum VDD/VT point trades-off switching and leakage power and is a strong function of activity
also see [Burr94]
Limits of Supply Voltage Scaling

CMOS Inverter Transfer Curves
Vout 0.7 0.6 Output Voltage (V) 0.5 0.4 0.3 0.2 0.1 0.1 0 0.2 0.2 0.3 0.4 0.5 0.6 0.7 Vin 0.6 0.5 0.4 0.3 0.2 0.15 Experiment Calculation
0.7 V = Vs
Input Voltage (V)
Vsmin 2-4 kT / q
from [Swanson72] (IEEE JSSC, April 1972)
Burst Mode or Event DrivenComputation

BLOCKED (waiting for hardware events and client requests) Tblocked Off RUNNING (doing actual computation) Trunning On
Trace 1 Trace Length (sec) Toff (sec) Ton (sec) Toff/(Toff+Ton) 5182.48 5047.47 135.01 0.9739
Trace 2 26859.9 26427.4 432.5 0.9839
Trace 3 995.16 960.82 34.34 0.9655
For an X-server application, processor spends most of the time in the blocked or off state.
from [Srivastava95] (IEEE Trans. on VLSI Systems)
Techniques for Burst Mode Computation

SLEEP
High VT
Multiple VT Technology
Low VT
(Disable high VT devices during idle periods)

e.g., [Sakata93] (Symposium on VLSI Circuits), [Mutoh93] (International ASIC Conference)
SLEEP
High VT
High VT transistor sizing issues Preserving state requires extra transistors

Latch Design in MTCMOS
SLEEP
High VT
SLEEP
High VT
SLEEP
High VT
CLK
SLEEP
High VT
From S. Mutoh, et. al. JSSC, August 1995

Techniques for Burst Mode Computation

VDD
+ VP > 0
ON
standby
Vin
Vout
standby
ON
Substrate Bias Controlled Variable VT Devices (Increase VT during idle periods)

from [Seta95] (ISSCC 1995)
+ - VN < 0
Needs large body factors - large well capacitances Triple well process needed
40
SOI with Active Substrate (SOIAS)

tfox tsi tbox
n+
p SiO2 p+
n+
p+
n SiO2 n+
p+
Loverlap
i-poly
SiO2
Silicon Substrate
Backgate Control Enables Dynamically Varying Threshold Voltages

from [Yang95]
NMOS Device Characteristics

10
-2
Vt=0.448 V (Vgb=0.0 V) Vt=0.184 V (Vgb=3 V)
10-3 10-4 10-5
0.03
1.8x
Leff=0.44 um tsi=4.5 nm tfox=9 nm tbox=100 nm VDS=1.0 V 0.02
Id (mA/um)
10
-7
10-8 10-9 10-10 10-11 10-12 10-13
~ 4 Dec
0.01
0 -0.2 0 0.2 0.4 0.6 0.8 1
Vgf (V)
Id (mA/um)
10-6
Ring Oscillator Characteristics

Ring Oscillator Frequency (MHz) 12 Varied VTN only VTP= - 0.2V 10
Varied VTP only VTN = 0.512V
6 0.0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 Backgate Controlled Variable |V T| (V)
Processor speed is adjustable on demand
43
Architectural Model & Activity Parameters for SOIAS

Add15
Add1 Circuit Node Transition Activity
a b
0.4 4 P0->1 0.2 .2
x
0 0
1 0.8 0.6 PB 0.4 0.4 PA 0.6 0.2 0.8
0
CLK ADD CLK BACKGATE
0.2
pb
pa
10
10
CLK ADD
ADD ON
ADD OFF
ADD ON
fga = Module Activity Factor

CLK BACKGATE
LOW VT
HIGH VT
LOW VT
bga = Backgate Switching Activity

Generic Architecture Model for All Technologies
Technology Multiple Threshold Technology Substrate Bias Control Silicon On Insulator Active Substrate
Leakage Control Mechanism (hence affecting bga) Switching the High VT devices ON/OFF Controlling the Substrate Voltages Switching the Backgate Voltage
Hierarchy of Prolers and Statistical Models Required for Virtual Prototyping

Energy Estimation Models for SOI and SOIAS

fga = Module Activity Factor bga = Backgate Switching Activity = Node Transition Activity Factor
ESOI = fga CfgVdd2 + Ileak_lowVT Vdd Tcycle ESOIAS = fga CfgVdd2 + fga Ileak_lowVT Vdd Tcycle + (1-fga)Ileak_highVT Vdd Tcycle
+ bgaCbgVbg2
46
Architectural Proling to Determine fga and bga

Table 1. SPEC benchmark espresso
Number Total Instructions Additions Shifts Multiplications 900158847 543616709 57000715 172883 Number Total Instructions Total Additions Total Shifts Multiplications 1737729538 661236960 52224367 7088 Number Total Instructions Additions Shifts Multiplications 2125 1250 186 3 fga 0.6039 0.0633 0.0002 fga 0.6023 0.0087 0.0000 fga 0.5882 0.0875 0.0014 bga 0.1954 0.0541 0.0002 bga 0.2233 0.0086 0.0000 bga 0.2635 0.0753 0.0014
47
Table 2. SPEC benchmark Li
Table 3. Data Encryption (IDEA)
SOI vs. SOIAS Technology Evaluation
0.5 0.0
Adder Shifter
o * *
Mult. .
log(ESOIAS/ESOI)
1
-0.5 -1.0
. o * *
1.5 2 2.5
3.5
log
or)
0.5
(b ac
log(fron
t-gate ac2 1.5 tivity fac t
2.5
3 3.5
kga te
ac
tiv ity
fac
tor
48
Transistor Sizing for Low-Power

Lower Capacitance Small W/Ls Higher Voltage
Large W/Ls Higher Capacitance Lower Voltage
Larger sized devices are useful only when interconnect dominated Minimum sized devices are usually optimal for low-power
49
Transistor Sizing for Fixed Throughput

I W/L CMIN Cg = W/L CMIN
CMIN = Minimum sized gate (W/L=1)

CP = Cwiring + CDF
W /L after sizing
= CP / (K CMIN)
10
NORMALIZED ENERGY
HIGH PERFORMANCE
W/L >> CP / (K CMIN)
7 5 4 3 2 1.5 1.0 0.7 0.5 1 3

W/L
=0 = 0.5 =1 adder = 1.5 =2 10
LOW POWER
W/L = 2 CP / (K CMIN) (if CP K CMIN) ELSE W/L = 1
from [Chandrakasan92] (IEEE JSSC, 1992)

50
Capacitance Breakdown
MODULE LEVEL
MODULE ADDER (Conventional Static) ADDER (Carry Select) TSPC COUNTER LOG SHIFTER (8 bit shift by 4) COMPARATOR GATE 30% 37% 32% 15% 33% DIFFUSION 45% 31% 26% 42% 38% INTERCONNECT 25% 32% 36% 43% 29%
DATAPATH LEVEL
MODULE ADDER CHAIN ( 7 adders ) WAVE DIGITAL FILTER ADDRESS GENERATION (STD CELL) VIDEO SYNC GENERATOR (STD CELL) GATE 38% 31% 56% 45% DIFFUSION 38% 29% 24% 25% INTERCONNECT 24% 40% 20% 30%
51
Choice of Logic Style

B
VDD A B C B A A B A B A A B B A B C B B A Sum A B A B VDD B
VDD A P P B A B GEN
VDD
A
B A
C
P
CIN B VDD GEN SUM CIN CIN PROP
GND VDD P CIN GEN COUT P
CIN P
GND A B C
COUT CIN GEN GEN
Cout
CIN
P GND
GND
CONVENTIONAL CMOS Adder

B VDD PRE VDD VDD PRE VDD A A CO CIN B B A CIN B CIN B A CIN A CIN CIN A COSUM B B B B C C SUM
OPTIMIZED static Adder

B A CC A A
B B
A A
Sum
Sum
Cout
Cout
DCVSL Adder
CPL Adder
Choice of Logic Style

200 150
Standard Cell
8-bit adders in 2.0m
POWER-DELAY PRODUCT (pJ)
100 70 50 30 20 15 10 7 5 3 10 30
Optimized Static DCVSL
CSA Conventional Static CPL - LOW Vt
Decreasing Vdd
100
DELAY (ns)
Power-delay product improves as voltage decreases. The best logic style minimizes power-delay for a given delay constraint.
Reducing the Energy/Operation at a Fixed Vdd

Vdd (=1.5V) M1 M2 o 6/2 3/9 o V(out) M5 < 4/2 M4 9/2 7/2 M3 > Ceff = 5pF o Vout Volts 1.5 1.0 0.5 0 0 20 40 60 t (ns) 80 100 v(line) v() v(out) v(out)
Heavily Loaded Bit-line
Signal Amplification
Vin
Reduced Signal Swing Example: FIFO Memory
Power Reduction Over Rail-to-Rail Swing = Vdd/(Vdd-Vt)
54
Reducing the Energy/Operation at a Fixed Vdd

R
tr
ADIABATIC CHARGING
E = (RC/tr)CV2
(for tr >> RC)
Applying slow input slopes reduces E below CV2 Useful for driving large capacitors (Buffers) Power reduction > 4 for pad drivers (1 MHz) ISI
Example: Stepwise Adiabatic Driver

VN N
V2 V1
RC charging steps
CL from [Svensson94] (IEEE Symposium on Low Power Design, 1994)
1 0
Vi = (i/N) V
2 1 -- C L V dd V dd V dd 2 E step = Q V avg = C L ---------- ---------- = --------------------------------N 2N 2 N 2 1 -- C L V dd E conventional 2 E total = N --------------------------------- = -----------------------------------------2 N N
Activity Driven Logic Level Power Down

A[N-1] B[N-1]
MSB REG CLK
MSB COMPARATOR A>B
COMBINATIONAL LOGIC BLOCK CLK REG
A[N-2:0]
REG for bits 0->N-2
COMPARATOR A>B for bits 0->N-2 CONDITIONALLY SWITCHED
MODIFIED REGISTER B[N-2:0]
REG for bits 0->N-2
GATED_CLK from [Alidina94] (1994 International Workshop on Low-power Design)
50% reduction possible for random inputs

Activity Reduction in Shift Registers

N Length Shift Register
Data In fCLK
Data Out
Pserial = NCreg V2 fclk

N/2 Length Shift Register
Data In
Data Out
fCLK/2
Pparallel= 2 x (N/2 Creg V2 fclk/2) + Poverhead

Shift Register Power for Various Lengths

1.0 Normalized Power Dissipation 0.8 0.6 0.4 64-bit 0.2 0.0 0 8 16 Degree of Parallelism 24 128-bit 256-bit 32 32-bit
59
Summary
Power dissipation is a prime design constraint for portable systems Low Power design requires optimization at all Levels Sources of power dissipation have been analyzed Technology, circuit, and logic design techniques have been described
60
References
[Alidina94] M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, Precomputation-Based Sequential Logic Optimization for Low Power, 1994 International Workshop on Low-power Design, pp. 57-62, April 1994. [Burd95] T. Burd, R. Brodersen, Energy Efcient CMOS Microprocessor Design, Proceedings of the 28th Annual HICSS Conference, Vol. I, pp. 288-297 Jan. 1995. [Burr94] J. Burr, J. Shott, A 200mV Self-Testing Encoder/Decoder using Stanford Ultra-low Power CMOS, IEEE ISSCC, pp. 84-85, 1994. [Callaway92] T. Callaway and E. Swartzlander, Jr., Optimizing Arithmetic Elements for Signal Processing, VLSI Signal Processing V, pp. 91-100, IEEE Special Publications, 1992. [Chandrakasan92] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, Low-power Digital CMOS Design, IEEE Journal of Solid State Circuits, pp. 473-484, April 1992. [Horowitz94] M. Horowitz, T. Indermaur, R. Gonzalez, Low-Power Digital Design, Proceedings of the Symposium on Low Power Electronics, 1994. [Kakumu90] M. Kakumu and M Kinugawa, Power-Supply Voltage Impact on Circuit Performance for Half and Lower Submicrometer CMOS LSI, IEEE Transactions on Electron Devices, Vol 37, No. 8, pp. 1902-1908, August 1990. [Mutoh93] S. Mutoh, T. Douseki. Y. Matsuya, T. Aoki, and J. Yamada, 1-V High-speed Digital Circuit Technology with 0.5m Multi Threshold CMOS, IEEE Int. ASIC Conf., pp. 186-189, 1993. [Sakata93] T. Sakata, M. Horiguchi, K. Itoh, Subthreshold-Current Reduction Circuits for Multi-GIGABIT DRAMs, 1993 Symposium on VLSI Circuits, pp. 45-46. [Seta95] K. Seta, H. Hara, T. Kuroda, M. Kakumu, T. Sakurai, 50% Active-Power Saving Without Speed Degradation Using Standby Power Reduction (SPR) Circuit, IEEE ISSCC 95, pp. 318-319. [Srivastava95] M. Srivastava, A.P. Chandrakasan, R. Brodersen, Predictive System Shutdown and Other Architectural Techniques for Energy Efcient Programmable Computation, to appear in the IEEE Trans. on VLSI Systems, March 1996. [Svensson94] L.J. Svensson and J.G. Koller, Driving a capacitive load without dissipating fCV2, IEEE Symposium on Low Power Design, pp. 100101, 1994. [Yang95] I. Yang, C. Vieri, A. P. Chandrakasan, D. Antoniadis, "Back Gated CMOS on SOIAS for Dynamic Threshold Control," 1995 IEEE International Electron Devices Meeting, December 1995. [Veendrick84] H.J.M. Veendrick, Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits, IEEE Journal of Solid-State Circuits, Vol. SC-19, pp. 468-473, August 1984.

Basics of Low Power Circuit and Logic Design

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Basics of Low Power Circuit and Logic Design

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Basics of Low Power Circuit and Logic Design

Anantha Chandrakasan Massachusetts Institute of Technology

High Performance Processors