TEMA 7

Tecnologa y fabricacin de CIs

G. Fabricacin de dispositivos: Etapa CMOS

http://jas.eng.buffalo.edu/education/fab/invFab/index.html http://www.usna.edu/EE/ee452/LectureNotes/02-_CMOS_Process_Steps/08_Simple_CMOS_Fab.ppt#3 1

Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa inversora CMOS

mjmm@usal.es

Inversor (NOT)

Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa inversora CMOS
The following discussion will concentrate on the wellestablished CMOS fabrication technology, which requires that both n-channel (nMOS) and p-channel (pMOS) transistors be built on the same chip substrate. To accommodate both nMOS and pMOS devices, special regions must be created in which the semiconductor type is opposite to the substrate type. These regions are called wells or tubs. A p-well is created in an n-type substrate or, alternatively, an n- well is created in a p-type substrate. In the simple n-well CMOS fabrication technology, the nMOS transistor is created in the p-type substrate, and the pMOS transistor is created in the n-well, which is built-in into the p-type substrate.

Oxide Isolation G -VSS p+ S n+

n-MOSFET

G D n+ D p+ n-well
p-MOSFET

S p+

+VDD n+
3

mjmm@usal.es

Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa inversora CMOS
The simplified process sequence for the fabrication of CMOS integrated circuits on a p- type silicon substrate is shown.

Starts with the creation of the n-well regions for pMOS transistors, by impurity implantation into the substrate. A thick oxide is grown surrounding the nMOS and pMOS regions. The thin gate oxide is grown on the surface by thermal oxidation. Polysilicon of the gate is deposited. Creation of n+ and p+ regions (source, drain and channel-stop implants) Together with a self-aligning of the gate. Finally the metallization is created (creation of metal interconnects).

Metallization Oxide Isolation G -VSS p+ S n+

n-MOSFET

G D n+ D p+ n-well
p-MOSFET

S p+

+VDD n+
4

mjmm@usal.es

Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa inversora CMOS
1. Substrate.

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

2. The first step is to form the SiO2 layer(0.5 - 1um thick) by thermal oxidation.

Etapa 1: crecimiento de la capa de xido nativo.

The oxidation temperature is generally in the range of 900 - 1200 degree C, and the typical gas flow rate is about 1cm/s. The method of producing an oxide layer consists of heating a silicon wafer in an oxidizing atmosphere. The wafer boat is slowly inserted into a fused silica tube wrapped in an electrical heating mantle. The temperature of the wafers gradually rises as Oxygen gas blowing through the tube passes over the surface of wafers. And oxygen molecules can actually diffuse through the oxide layer to reach the underlying silicon. There, oxygen and silicon react, and the layer of oxide gradually grows thicker. mjmm@usal.es
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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

3. Following oxidation, several drops of positive Photoresist are dropped on the wafer.

Etapa 2: Apertura de la ventana del transistor P-MOS

Primer proceso fotolitogrfico

Following oxidation, several drops of positive Photoresist(e.g. Shipley S1818) are dropped on the wafer. The wafer is spun at about 3000rpm to be uniformly spread out. After the spinning step, the wafer is given a pre-exposure baking (80 - 100 degree C) to remove the solvent from the PR film and improve adhesion to the substrate.
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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

4. Proceso de implantacin inica y difusin del pozo N.

Etapa 3: formacin del pozo N del transistor P-MOS

After the oxide etch, ion implantation deposits a controlled dose of phosphorus through the etched window. A prolonged high-temperature drive creates a deep lightly doped N-type region called, N-Well.

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

5. Crecimiento de la capa de xido de campo.

Etapa 4: xido de campo

Idntica a la primera etapa.

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

6. Define the active area (Drain and Source regions) by photolithography.

Etapa 5: Definicin de SyD

Segundo proceso fotolitogrfico

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

7. Crecimiento de una delgada capa de oxido nativo: OXIDO DE PUERTA.

Etapa 6: Crecimiento de una delgada capa de xido de puerta

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

8. Creacin de los contactos de puerta: Deposicin de Poli-Silicio.

Etapa 7: Contactos de puerta de Poly-Si

Polysilicon Deposition:
A patterned poly layer is produced by first depositing polsilicon across the wafer. The wafer is then coated with photoresist, patterned, and etched to selectively remove the polysilicon.

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

8. Litografa del Poly-Si de los contactos de puerta

Etapa 8: Litografa de Poly-Si de puerta

Tercer proceso fotolitogrfico

Polysilicon Deposition:
A patterned poly layer is produced by first depositing polsilicon across the wafer. The wafer is then coated with photoresist, patterned, and etched to selectively remove the polysilicon.

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

9. Creacin de Litografa para Implantacin de Arsnico de regiones n+.

Etapa 9: Litografa para definir las regiones n+

Cuarto proceso fotolitogrfico

The arsenic implant begins with the application of photoresist to the wafer, followed by patterning using the NSD mask.

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

10. Creacin de fuente y drenador tipo n+ mediante Implantacin de Arsnico.

Etapa 10: Implantacin inica de las regiones n+

Shalllow, heavily doped N-type regions are then formed by implanting arsenic through the exposed gate oxide. Proceso de AUTOALINEADO: The polysilicon gate blocks this implant from the regions directly underneath the gate and therefore minimizes the gate/source and gate/drain overlap capacitances. Once the implant has been completed, the photoresist residue is stripped from the wafer. mjmm@usal.es
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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

11. Proceso litogrfico para definir las regiones p+ de fuente y drenador

Etapa 11: Litografa para definir las regiones p+

Quinto proceso fotolitogrfico

The boron implant begins with the application of a second photoresist layer patterned using the PSD mask.

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

12. Crear las regiones p+ de fuente y drenador mediante implante de boro.

Etapa 12: Implantacin de las regiones p+

A shallow, heavily doped P-type region is formed by implanting boron through the exposed gate oxide. As with the NSD implant, the PSD implant self-aligns to the polysilicon and the PMOS transistors also exhibit minimal overlap capacitance. Following the PSD implant, photoresist is again stripped from the wafer.
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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

13. Crecimiento de xido de pasivacin: Proteccin del dispositivo.

Etapa 13: Oxidacin

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

14. Proceso fotolitogrfico para la creacin de las vas de metalizaciones de fuente y drenador.

Etapa 14: Litografa para definir vias de metalizaciones de SyD

Sexto proceso fotolitogrfico

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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

15. Deposicin de las Interconexiones de aluminio.

Etapa 14: Deposicin de aluminio

A thin film of refractory metal sputtered over the wafer precedes a much thicker layer of copper-doped aluminum. The metallized wafer is coated with photoresist and patterned, using the metal mask. A suitable etchant then removes unwanted metal to form the interconnection pattern.
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Tema 7. Tecnologa y Fabricacin de CIs II. Fabricacin de una etapa CMOS

16. Finalizacin.

Etapa 15: Litografa para dividir metalizaciones de G, S y D

Septimo proceso fotolitogrfico

Tras el ltimo paso litogrfico se termina el proceso de fabricacin. Se muestra la conexiones de tierra, polarizacin, la unin de los terminales de puerta (terminal Vi de la etpa inversora) y el terminal de salida V0. Se muestra tambin la vista superior (layout del circuito).
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