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CS/OCT 2009/ITT430

UNIVERSITI TEKNOLOGI MARA FINAL EXAMINATION

COURSE COURSE CODE EXAMINATION TIME

MICROPROCESSOR ITT430 OCTOBER 2009 3 HOURS

INSTRUCTIONS TO CANDIDATES 1. This question paper consists of three (3) parts : PART A (25 Questions) PART B (25 Questions) PART C (6 Question) Answer ALL questions from all three (3) parts : i) ii) iii) 3. Answer PART A in the Objective Answer Sheet Answer PART B in the True/False Answer Sheet. Answer PART C in the Answer Booklet. Start each answer on a new page

2.

Do not bring any material into the examination room unless permission is given by the invigilator. Please check to make sure that this examination pack consists of: i) ii) iii) iv) the Question Paper an Answer Booklet - provided by the Faculty A True/False Answer Sheet - provided by the Faculty an Objective Answer Sheet - provided by the Faculty

4.

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO


This examination paper consists of 12 printed pages
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PART A (25 marks)

For each of the following questions, choose ONE (1) suitable answer and mark the answer on the Objective Answer Sheet provided.

1.

What is the value of the double word stored in memory starting at address 0B004 if the contents of memory locations 0B00516, 0B00616, OB00716, and 0B00816 are 3216, 3416, 3616, and 3816 respectively? Is it an aligned or misaligned double word? A. B. C. D. 3234363816 and aligned double word 3234363816 and misaligned double word 3836343216 and aligned double word 3836343216 and misaligned double word

2.

In the 8088/8086 microprocessor, the length of memory address space is A. B. C. D. 16Kbytes 32Kbytes 64Kbyt.es 1Mbyte

3.

The addressing mode used to update the content of a segment register is A. B. C. D. Register Operand Addressing Mode Immediate Operand Addressing Mode Direct Addressing Mode Register Indirect Addressing Mode

4.

The number of bus cycle required for writing a word at memory address 012AAie of an 8088-based microcomputer is A. B. C. D. 1 2 3 4

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5.

Which of the following statements are TRUE? I II III The 8088 and 8086 microprocessors have the ability to address up to IMbyte of memory via their 20-bit address buses. The 8088 and 8086 microprocessors have a-16 bit data bus. The 8088 can operate at 5MHz and 8MHz and 8086 can operate at 5MHz, 8MHzand 10MHz. I and II I and III II and III I, II and III

A. B. C. D.

6.

In a maximum-mode 8088 microcomputer, the signal lines of S4S3for accessing the stack segment is A. B. 00 01

C.
D.

10
11

7.

Initially, the content of AX = 011 OH and CX = 011 OH. After the execution of "MUL CL", the content of the registers are A. B. C. D. AX AX AX AX = 0110HandCX = 0110HandCX = 0110HandCX = 0100HandCX = 0010H = 0110H = 0100H = 0110H

8.

The content of BX after executing the following instructions in the MOV BX, 8A3BH MOV CL, 3 STC SAR BX, CL

DEBUG

trace is

A. B. C. D.

1147H 2147H 8147H F147H

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9.

The interrupt service routine specified by CSo:IPo is A. B. C. D. NMI. Breakpoint. Single Step. Divide Error.

10.

The bus status code of S2SXS0 = 101 represents a bus activity of A. B. C. D. Read I/O Port. Write I/O Port. Read Memory. Write Memory

11.

The flag register bit that determines whether the address for the string operation is incremented or decremented is A. B. C. D. TF DF VF SF

12.

Which of the following statements is NOT TRUE about the minimum-mode and maximum-mode of the 8088 system? A. B. C. D. In the minimum-mode, the 8088 directly produce the control signals for the interfacing to memory and I/O devices. In the maximum-mode, the 8088 control signals are encoded in the status lines and need to be decoded externally. In the minimum-mode, the 8088 produce signals for supporting multiprocessing systems. The logic level of input MN/MX determines the mode of operation. A logic 1 sets the 8088 system in minimum-mode and a logic 0 sets it in maximummode.

13.

The term nonvolatile memory means A. B. C. D. When the power supply for the memory device is turned off, its data contents are not lost. When the power supply for the memory device is turned off, its data contents are lost. Data contents of nonvolatile memory are electrically entered by users. Data contents of nonvolatile memory can be erased by exposing it to ultraviolet light. CONFIDENTIAL

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14.

In processing the interrupts, a stack is needed because, A. B. C. D. there is no other place to store interrupt instructions. during an interrupt routine, microprocessor registers may be needed. the ret instruction is followed by the address to be returned to. during an interrupt, the microprocessor may need to store the instructions for the subroutine.

15.

The location of nonmaskable interrupt (NMI) in the interrupt vector table is A. B. C. D. IPi is stored at 04ie and CSi is stored at 06ie IP2 is stored at O816 and CS2 is stored at OA16 IP3 is stored at OCie and CS3 is stored at OEie IP4 is stored at 10ie and CS4 is stored at 12ie

16.

The state of the flag register after executing the following instructions is
MOV DX, SUB DX, 95EBH 34F5H

A. B. C. D.

NV UP NV UP NV UP NV UP

El El El El

PL NZ NA PO CY NG NZ NA PO NC PL NZ NA PE NC NG NZ AC PO CY

17.

The concept of continually checking the I/O devices, via program looping, is A. B. C. D. poll mapping. device polling. device looping. device mapping.

18.

The process which peripheral devices use to communicate with memory without going through the microprocessor is called A. B. C. D. DMA. MPU. Polling. Mapping.

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19.

The following instruction sequence is needed to


MOV DX, 8 0 0 4 H MOV AL, [DATA] OUT DX, AL

A. B. C. D.

output the contents of memory output the contents of memory output the contents of memory output the contents of memory

address address address address

DATA to DATA to DATA to DATA to

port 0. port 2. port 4. port 8.

20.

The control word to configure the 82C55A such that all ports are input ports and set up for mode 0 operation is A. B. C. D. 98H. 99H. 9AH. 9BH.

21.

Which statement is TRUE of Random Access Read/Write Memory? A. B. C. D. It consists of SRAM and DRAM. The DRAM needs to be refreshed at regular interval of time in order to restore the data. SRAM data remains valid as long as power supply is not turn off. All of the above.

22.

The key differences between NMI and the other external hardware initiated interrupts are I II III A. B. C. D. NMI is not masked out by IF. NMI is initiated from the NMI input instead of from the INTR input. NMI input is edge-triggered instead of level sensitive. I and II I and III II and III I, II and III

23.

When the memory address output on the bus is 0041216, the 82C55A parallel I/O port accessed is A. B. C. Port A of PPI 1. Port B of PPI 1. Port A of PPI 2.
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D. Port B of PPI 2. Hak Cipta Universiti Teknologi MARA

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24.

Which of the following modes of DMA operation can be selected for the DMA channels? 1 II III A. B. C. D. Demand Mode Block Mode Cascade Mode 1 and II 1 and III II and III 1, II and III

25.

The correct way to access the stack is A. B. C. D. MOV AX, [SP]+20 MOV AX, [SP][SI] MOV AX, [BP+DI] MOV AX, [SP+SI]

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P A R T B (25 marks) Answer ALL questions. For each of the following questions, answer either TRUE or FALSE and mark your answer on the TRUE/FALSE Answer Sheet provided.

1. 2.

PUSH and POP instructions are used to store and retrieve data from stack. The flag register SF bit is set as a result of the last arithmetic operation being negative. RAS and CAS are associated with the DRAM and SRAM devices. Assuming that AX = ABCD16 and CX = 120416, the new content of AX after executing the instruction ROR AX, CL is AX = BCDA16. The two separate internal processing units within the 8088/8086 microprocessor are Execution Unit (EU) and Bus Interface Unit (BIU). In based addressing mode, the effective address is obtained from the contents of either BX or BP registers. In a LOOPZ instruction, the instruction will decrement register CX and jumps to the label only if ZF flag is set. In RCR (rotate right through carry), as the bits of the destination are shifted to the right into CF, the empty bits are filled with the sign bit. The IP and CS registers have their contents changed during the intrasegment jump. Registers of Pentium microprocessor can be accessed either as 8 bits, 16 bits or 32 bits in length. The source operand in instruction "MOV AH, [BX][SI] + 2234H" uses indexed addressing mode. If the standard UART clock-frequency for PCs equals 1,843,200 cycles-per-second and each data-bit consumes 8 clock-cycles, then the fastest serial bit-rate for these PCs is 115,200 bps. X86 processors offer four levels of privilege for memory access which are used to help the programmer when writing operation system software and software for a multi-user and multitasking environment. When 8086 reads a word from address 12340H, the logic levels of BHEL, MWRC, MRDC and A0L of the memory interface circuitry are 0, 0, 0 and 1 respectively. CONFIDENTIAL

3. 4.

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9. 10.

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15.

If the inputs to a 74F138 decoder are G ^ l , G ^ O , G 2 B=0, and CBA=110 for the I/O address decoding, then the output P4 will be activated. The I/O chip select circuitry encodes the I/O address from the LSI peripheral devices, such as the DMA controller, interrupt controller, programmable interval timer, and PPI controller. The advantage of storing data in the internal registers instead of memory during processing is that they can be accessed much faster. The 8288 Bus Controller is used to provide control signals for the 8088/8086 when it is operating in minimum mode. Treating a peripheral device like a memory location is referred to as memory mapping. In an 8086-base microcomputer, the logic level of Ao and BHE are 1 and 0 respectively, to enable a byte of data being written to I/O address A0001H. When direct memory access (DMA) is working, the CPU is sitting idle. The 82C37A has two priority schemes: fixed priority and polling that can be selected under software control. Port C2 is set when the value 0516 is written to the control register of an 82C55A is set for mode 2 operation. If the ASCII representation for character "N" is 4EH then the ASCII representation for character "Y" is 58H. INTR and NMI signals are common to both the minimum mode and maximummode of the 8088 system.

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CS/OCT 2009/ITT430

PART C (50 MARKS)

Answer ALL questions.

QUESTION 1 Encode (in hexadecimal) the following instructions using the information given in Table 1 and Table 2. Assume that the opcode for the MOV, XCHG and ADD operations are 100010, 1000011 and 000000 respectively.

a)

MOV AX, [SI] + 1234H;


(4 marks)

b)

XCHG DX, [SI] ;


(2 marks)

C)

ADD [BX]+12H ,

DX;

(3 marks) REG 000 001 010 011 100 101 110 111 W=1 AX AL CX CL DL DX BX BL AH SP BP CH DH SI Dl BH Table 1: Register Field Encoding

w=o

MOD=l 1 R/M w=o 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH

EFFECTIVE ADDRESS CALCULATION W=l MOD=10 MOD=00 MOD=01 R/M (BX)+(SI)+D16 AX (BX)+(SI)+D8 000 (BX)+(SI) CX 001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16 DX 010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16 BX 011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D16 SP 100 (SI) (SI)+D8 (SI)+D16 BP 101 (DI) (DI)+D8 (DI)+D16 SI 110 Dir. address (BP)+D8 (BP)+D16 DI 111 (BX) (BX)+D8 (BX)+D16 7 able 2: Ftegister/P Memory Encod ing Field

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CS/OCT 2009/ITT430

QUESTION 2 A subroutine is a special segment of program that can be called for execution from any point in a program. a) Define the TWO (2) instructions used for subroutine handling. (4 marks) b) Describe the operation performed when intrasegment call is initiated. (3 marks) c) Name FOUR (4) types of operands of the subroutine instruction. Give ONE (1) example for each operand presented. (4 marks)

QUESTION 3 a) Name ONE (1) key difference between the unconditional jump instruction and conditional jump instruction. Give ONE (1) example for each jump instruction. (4 marks) b) Describe the operation performed by the following sequence of instructions. i) POPF (2 marks) ii) PUSHF (2 marks)

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QUESTION 4

The 8088 and 8086 microcomputers can employ two different types of input/output methods. These implementations differ in the way the I/O ports are mapped into the 8088/8086's address space. a) Define and illustrate the TWO (2) methods of I/O. (4 marks) b) Give ONE (1) advantage for each of the I/O implementations. (2 marks) c) Give ONE (1) disadvantage for each of the I/O implementations. (2 marks)

QUESTION 5 Write equivalent instruction sequence using string instruction for each of the following: a) MOVAL,[SI] MOV [Dl], AL INC SI INCDI (3 marks) b) MOV AX, [Dl] CMP AX, [SI] DEC SI DECDI (4 marks)

QUESTION 6 Develop a sequence of instructions that copy 16 words of data stored in memory starting at address 1234H and paste the result in the memory location 4321H. (7 marks)

END OF QUESTION PAPER


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