CMOS Objective Questions

What is meant by the rise time of a waveform?

The time taken for the waveform to increase from 10% to 90% of the height of a step. The time taken for the waveform to decrease from 90% to 10% of the height of a step. The time delay from when the input step changes by 50% to when the output step changes by 50%. The time taken for the waveform to increase from 0% to 90% of the height of a step.

What is the cause of storage time in a bipolar transistor?

The inertia of the majority charge carriers.

The 'memory effect' of the device.

The time taken to remove excess charge stored in the base region as a result of saturation. The inertia of the minority charge carriers.

What is meant by the fan-out of a logic gate?

The number of other gates that can be connected to the gate's output. The amount of cooling required by the gate. The physical distance between the output pins on the device. The number of other gates that can be connected to one of the gate's inputs.

Which of the following statements is incorrect?

CMOS circuitry is more difficult to fabricate than NMOS or PMOS as it required devices of both polarities. CMOS gates have very good noise immunity that is typically 10% of the supply voltage. When a CMOS gate is static it has negligible power consumption.

CMOS gates have logic levels close to the supply rails.

Which of the following statements is incorrect?

TTL devices have logic levels of about 3.4 V and 0.2 V.

Standard TTL devices have a propagation delay that is dominated by the storage time of the bipolar transistors used. TTL logic normally operates from a single 5 V supply.

TTL logic has very low power consumption and is therefore widely used in highly integrated components.

Which of the following statements is incorrect?

ECL is widely used in high-speed applications. ECL is one of the fastest forms of electronic logic. ECL has high power consumption. ECL suffers from low noise immunity.

What type of logic gate is shown here?

A two-input TTL AND gate. A two-input TTL NOR gate. A two-input TTL OR gate. A two-input TTL NAND gate.

What should be done with an unused TTL input that is required to be at logical 1?
It should be connected directly to the positive supply rail. It should be connected directly to the zero volt supply rail. It should be left disconnected. It should be tied to the positive supply rail through an appropriate resistor.

What type of logic gate is shown here?

A two-input CMOS AND gate. A two-input CMOS OR gate. A two-input CMOS NAND gate. A two-input CMOS NOR gate.

What distinguishes CMOS logic gates that have the letter 'T' within their part numbers (for example 74HCT00)?
They are suitable for terahertz operation. They are constructed using a Teflon substrate. They are very high-speed devices. They use the supply voltages and logic levels of TTL gates.