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Micro controller Based System Design Module 1

VARIOUS LOGIC FAMILIES The IC digital logic families are classified as 1) 2) 3) 4) 5) 6) 7) 8) 9) Resistor transistor logic (RTL) Diode transistor logic (DTL) Direct coupled transistor logic (DCTL) High threshold logic (HTL) Integrated injection logic (I2L) Transistor transistor logic (TTL) Emitter coupled logic (ECL) Metal oxide semiconductor (MOS) Complementary metal-oxide semiconductor (CMOS)

RTL Basic Gate The Basic Circuit of the RTL digital logic family is the NOR gate shown in fig 1.1

FIGURE 1.1 Each input is associated with one resistor and one transistor. The collectors of the transistors are tied together at the output. The voltage levels for the circuit are 0.2V for the low-level and 1 to 3.6V for the high level. If any input of RTL gate is high, the corresponding transistor is driven into saturation. This causes the output to be low, regardless of the states of other transistors. If all inputs are low at 0.2V, all transistors are cut off because VBE < 0.6V this causes the output to be high. The power dissipation of the RTL gate is about 12mw and the propagation delay averages 25ns.

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DTL Basic Gate The basic circuit in the DTL digital logic family is the NAND gate shown in fig 1.2.

FIGURE 1.2

Each input is associated with one diode. The diodes and the 5K resistor forms an AND gate. The transistor serves as a current amplifier while inverting the digital signal. If any input of the gate is low at 0.2V, the corresponding input diode conducts current through VCC and the 5K resister into the inputs node. The voltage at point P equal to 0.9V (ie input voltage 0.2V+ diode drop 0.7V). In order for the transistor to start conducting the voltage at point P must overcome 1.8V (ie one VBE drop in Q1 plus two diode drops). Since the voltage at P is 0.9V by the input conducting diode, the transistor is cut off and the output voltage is high at 5V. If all inputs of the gate are high, the transistor is driven into the saturation region. With the transistor saturated, the output drops to VCE of 0.2V which is the low level. The power dissipation of a DTL gate is about 12mw and the propagation delay averages 30ns. I2L It is reasonably good speeds and low power requirement Base of T1 and emitter of Q1 common Emitter of T1 and base of Q1 is common T1 is called a current injection transistor if the input to 0 then the current of T1 flows through the input switch to GND. There will be no current to Q1. When the Input switch open the current injected to Q1.refer fig1.3

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Extremely high density compare to TTL ( 10 times ) LSI functions Fabrication easier, Low power Good speed HTL A variant of DTL called high threshold logic circuits incorporated Zener diodes to create large difference between 0 to 1 levels. Normally it operates on 15 V in Industry application. The high difference is intended to minimize the noise effect. Integrated Injection logic (I2L) The main advantage of I2L is the high packing density of gates that can be achieved in a given area of semiconductor chip. This allows more circuits to be placed in the chip to form complex digital functions. This family is mostly used for LSI functions.

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The I2L basic gate is similar in operation to the RTL gate, with few major differences. (1) The base resistor used in the RTL gate is removed in the I2L gate. (2) The collector resistor used in the RTL gate is replaced by a PNP transistor that acts as a load for the I2L gate. (3) The I2L transistors use multiple collectors instead of the individual transistors employed in RTL. The schematic diagram of the basic I2L is shown fig1.4

Figure1.4

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It has an NPN transistor Q1, with multiple collectors for the outputs. The basic circuit has a PNP transistor, TI, connected to supply voltage VBB.

Transistor Transistor Logic (TTL) The original basic TTL gate was a slight improvement over the DTL gate. There are many various of the TTL basic gate and they are 1. 2. 3. 4. 5. 6. Standard TTL Low power TTL High speed TTL Schottky TTL Low power schottky TTL Advanced Low power Schottky TTL

Figure 1.5 The standard TTL gate was the first version in the TTL family. This basic gate was then constructed with different resistor values to produce gates with lower dissipation or higher speed. In the low-power TTL gate the resistor values are higher than the standard gate to reduce the power dissipation, but the propagation delay is increased. In the high-speed TTL gate, resistor values are lowered to reduce the propagation delay, but the power dissipation is increased. The schottky TTL removes the Storage time of transistors by preventing them from going into saturation. This version increases the speed of operation without an excessive

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increase in power dissipation. The low-power schottky TTL version sacrifices some speed for reduced power dissipation. All TTL versions are available in SSI packages and in more complex forms as MSI and LSI functions. TTL gates in all versions come in 3 different types of output configurations. 1) 2) 3) Open-collector output Totem-pole output Three state (or tri state) output

Emitter Coupled logic (ECL) ECL is a non saturated digital logic family since transistors do not saturate, it is possible to achieve propagation delays of 2ns and even below Ins. This family has the lowest propagation delay and is used mostly in systems requiring vary high speed operation. Its noise immunity and power dissipation, however, are the worst of all the logic families available. The noise margin is about 0.3V and not as good as in the TTL gate. High fan-out is possible in the ECL gate because of the high input impedance of the differential amplifier and low output impedance of the emitter-follower. Because of the extreme high speed of the signals, external wives act like transmission lines.

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Figure 1.6 ( ECL GATE) Metal Oxide Semiconductor (MOS) The basic structure of the MOS transistor is shown in fig 1.7

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Figure 1.7

Figure 1.8 Figure 1.9

There are 4 basic types of Mos structures the channel

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can be a p-and n-type, depending on whether the majority carriers are holes or electrons. The mode of operation can be enhancement or depletion, depending an the state of the channel region at zero gate voltage. If the channel is initially doped tightly with p-type impurity (diffused channel), a conducting channel exists at zero gate voltage and the device is said to operate in the depletion mode. If the region beneath the gate is left initially uncharged, a channel must be induced by the gate field before current can flowthus, the channel current is enhanced by the gate voltage and such a device is said to operate in the enhancement mode. One advantage of the MOS device is that it can be used not only as a transistor, but as a resistor as well. A resistor is obtained from the MOS by permanently biasing the gate terminal for conduction. The ratio of the source-drain voltage to the channel current determines the value of the resistance. Complementary MOS (CMOS) CMOS circuits take advantage of the fact that both n-channel and p-channel devices can be fabricated on the same substrate CMOS circuits consist of both types of MOS devices interconnected to form logic functions. The basic circuit is the inverter, which consists of one pchannel transistor and one n-channel transistor. THE Figure 1.11 of inverter is shown below when the input is low, both gates at zero potentials. The input is at -VOD relative to the source of the p-channel device and at OV relative to the source of n-channel device the result is that the p-channel device is turned ON and the n-channel device is turned OFF. Therefore the output voltage is high When input is high, the p-channel device is OFF and n-channel device is ON therefore output is low. In either logic state, one MOS transistor is On while the other is OFF. Because one transistor is always turned OFF, the dc power dissipation of the CMOS circuit is extremely low, usually on the order of IO nw. The CMOS nor gate Shown below.

PMOS\NMOS\CMOS NOR GATE IS SHOWN Figure1.10

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FIG1.10

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CMOS INVERTOR Figure 1.11

Comparision of major logic families

Logic parameter Basic gate Fan out Power Dissipated Per gate,MW Noise immunity Propagation Delay per Gate, ns RTL NOR 5 12 nominal DTL NAND 8 8-12 Good HTL NAND 10 55 excellent TTL NAND 20-40 12-22 C10mw Very good 12-6 (10 nsw) ECL OR-NOR 25 40-55 Good MOS NAND 20 0.2-10 nominal CMOS NOR or NAND 50 Iuv static Imwat 100KHZ Very good 105

12

30

90

4-1

300

ALS-4nscc,1mw,20 1) AS-1.5nscc,8.5mw,50 2) LSTTL 10nscc,2mw,20 3) S-3nscc,19mw,50 REFERENCES

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1) Digital Logic and computer Design -M Morris Mano 2) Integrated Electronics -Jacob Millmam and Christos-C. Halkias 3) Digital fundamentals FLOYD

PROGRAMMABLE LOGIC DEVICES [PLDS] The logic devices in which the logic function is programmed by the user and, in some cases, can be reprogrammed many times are called as programmable Logic devices. One advantage of PLDS over fixed function logic devices is that many more logic circuits can be stuffed into a much smaller area with PLDS. A second advantage is that, with certain PLDS, Logic designs can be readily changed without rewriting or replacing components. A PLD design can be implemented faster than one using fixed-function ICS. TYPES OF PLDS The 3 major types of programmable logic are 1. SPLD [Simple programmable Logic Device] 2. CPLD [complex PLD] and 3. FPGA [Field programmable Gate Array] 1. SPLD :-

They are the least complex form of SPLDS. They are the first type of programmable logic available. A few categories of SPLD are ----a. b. c. d. PAL (Programmable array logic) GAL (generic array logic) PLA (Programmable logic Array) PROM (Programmable read only memory)

2. CPLD :-

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CPLDS have a much higher capacity than CPLDS, permitting more complex logic circuits to be programmed into them. A typical CPLD is the equivalent of 2 to 64 SPLDS. The development of these devices followed SPLD as basic and advanced in technology permitted higher-density chips to be implemented. [Typically 44-160 pin packages]. 3. FPGA :They are different from SPLDS and CPLDS in their internal organization and have the greatest logic capacity. It consists of an array of any where from 64 to thousands of logic gate groups that are some times called logic blocks. FPGAS are classified into 2 category as Course grained [have large logic blocks] Fine grained [have much smaller logic blocks Programmable Arrays :All PLDS consist of programmable Arrays. A programmable arrays is essentially a grid of conductors that form rows and columns with a fusible link at each cross point. Arrays can be either fixed or programmable. The OR array It consists of an array of OR gates connected to a programmable matrix with fusible links at each cross point of a row and column as shown in fig 1.12

PALs and PLAs

Example Continued
A B C

All possible connections are available before programming

F0

F1

F2

F3

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PALs and PLAs

Difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA): PAL concept -- implemented by Monolithic Memories constrained topology of the OR Array I.e., the OR array cannot be fully programmed.

A given column of the OR array has access to only a subset of the possible product terms

PLA concept generalized topologies in AND and OR planes

Figure 1.12

The array can be programmed by blowing fuses to eliminate selected variable from the output functions, as illustrated above. For each input to an OR gate, only one fuse is left intact in order to connect the desired variable to the gate input. Once a fuse is blown it cannot be connected. The AND array It consists of AND gates connected to a programmable matrix with fusible links at each rows & columns. Another method of programming PLD is the anti fuse, which is opposite of the fuse. Here instead of burning fusible link a normally open contact is shorted by melting the anti fuse material to form a connection. Any way the OR array , AND array with fusible links or with anti fuse is one-time programmable. SPLDS

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1. PROM It consists of a set of fixed [non programmable] AND gates connected as a decoder and a programmable OR array as shown below.

PROM is used primarily as an addressable memory and not as a logic device, because of limitations imposed by the fixed AND gates 2. Programmable Logic Array (PLA) :It consists of a programmable AND array and a programmable OR array. It was developed to overcome some of the limitations of PROM. It is also called as FPLA [field programmable logic array] because the user in the field, not the manufactures, programs it.

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PALs and PLAs

Alternative representation for high fan-in structures

Short-hand notation so that all the wires need not be drawn!

A B

C D

AB AB CD CD

Notation for implementing F0 = A B + A' B' F1 = C D' + C' D

AB+AB CD + CD

Figure 1.15

Programmable Array logic (PAL) :_

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PLA has some disadvantages like longer delays due to the additional fusible links (because of two programmable arrays) and more circuit complexity. PAL is developed to over come these disadvantages. It consists of a programmable AND array and a fixed OR array with of logic. As shown fig 1.16.

Eg:- the simplified diagram of a programmed PAL is shown below.

PALs and PLAs

A B C
ABC A B

Design Example

Multiple functions of A, B, C F1 = A B C F2 = A + B + C F3 = A B C F4 = A + B + C F5 = A xor B xor C F6 = A xnor B xnor C

C A B C ABC ABC ABC ABC ABC ABC ABC

F1

F2

F3

F4 F5

F6

Figure 1.17 A typical PAL has 8 or more i/ps to its AND array and upto 8 o/ps from its o/p logic.ie nx8. Some PALS provide combined i/o pin that can be programmed an either o/or i/-. PAL Output combination logic

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There are three basic types of combinational o/p logic with tri state outputs and the associated OR gate. 1. Combinational output This o/p is used for an SOP function and is usually available as active low or active high o/p

Figure 1.18, Figure 1.18.A, Figure 1.9 (active low). Active high would be shown without the bubble on the tri state gate symbol. 2.Combinational I/o This o/p is used when the o/p fn. must feed back to be an i/p to the array or be used to make the I/o pin an i/p only.

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3.Programmable polarity o/p This o/p is used to selecting either the o/p fn. Or its complement by programming the XOR gate. The fuse on X-OR i/p is blown open for inversion.

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PAL USING FLIP FLOPS It contains two matrices namely product term generator matrix and sop generator matrix. With clocked f/fs in feed back path. Since AND matrix contain 1000 to 20,000 swimming nodes great logical complexity will be there. Feed back loop must be clocked carefully. Clocked f/f must be connected into all f/f paths from SOP matrix to product matrix. The reset of f/f initialize the logic can be controlled. Figure is shown above.1.20

GENERIC ARRAY LOGIC [GAL] It consists of a reprogrammable AND array and a fixed OR array with programmable o/p Logic Similar to pal array logic .refer the figure no 1.16 The structure of GAL allows any SOP expression with a defined no: of variables to be implemented. The basic structure of GAL is shown below. Instead of fuse in PAL, we use E2 CMOS cell at each cross point.

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Un programmed GAL Each row is connected to i/p AND gate each column is connected to an i/p variable or its complement of programming applied to the AND gates. Standard GAL Numbering GAL 16 V 8 16 :- no: of inputs V :- Variable output configuration 8 :- no: of outputs GAL 16V8 16input & 8 output high performance E2 MOS generic array logic. The propagation in delay is 3.5ns max and it can operate max of 250MHZ. The power consumption in less by 50 to 75% compare to bipolar and used active pull ups in all pins. Feature 100% field programmable -Re configurable Logic -Re programmable cells

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-High speed electrical erasure -100 erase/write cycles -20 years data retention -50% to 75% less power than Bi polar -8 OUTPUTS and 16 inputs device -OLMC configurable as combinational OP/or IP -OLMC also configurable as registered O/P -Emulates 20 PIN/PAL devices with full compatibility of fuse, map, function, and parametric -OUTPUT is programmable APPLICATION -High speed graphics processing -DMA control -Standard logic, high speed application -State machine control

-GAL 22VIO The block schematic is shown in figure 1.23 above -22 Inputs 10 outputs DEVICE Feature -10 outputs Logic Micro cells -PRE load and power on reset of registers -High performance E2CMOS Technology -4ns max propagation delay

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-250MHZ frequency of operation -Active pull up on all pins -Comparable with standard 22VIO BIPOLAR devices but only consume less power -50% to 75% power reduction compare to Bi polar -20 years of Data re tension -100 erase/write cycle -max flexibility in logic designs -Reconfigurable logic -Reprogrammable OLMC High speed erasure < 100m.Sec APPLICATION -DMA CONTROL -Standard logic speed up grade -High speed graphics processing -State machine control

PLA -Consists of program able AND array and programmable OR Array -output not program -cannot be reprogrammed AND ARRAY -uses fuse link for connectionCapacity is less One time programmable OTP No output logic

PAL It has programmable AND array and fixed OR array with O/P logic Output not program It can not be programmed Uses TTL or ECL technology Moderate capacity One time programmable OTP No programmable output logic

GAL It has reprogrammable AND array and fixed OR array and programmable output logic Output programmable Can be reprogrammed Uses E2CMOS technology Moderate capacity Many time reprogrammable Programmable

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Combination O/P Combinational I/P-O/P Programmable polarity

Combinational mode with 1. ADactive low 2. active high registered mode with 3. active low 4. active high

Output logic Macro cells (OLMC) OLMC contains programmable logic circuits that can be configured either (1) (2) for a combinational O/P or I/P for a registered O/P

OLMC combinational mode configuration are automatically set by programming. Each OLMC can be programmed for either as active-HIGH or an active low O/P. Also each OLMC can be programmed as an input. A basic logic diagram for GAL 22VIO OLMC is

hown below

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The logic consists of a flip flop and two multiplexer the 1-of-4 MUX connects are of its four input lines to the tri stable O/P buffer based on the states of two select inputs, S0 & SI The inputs to the 1-of-4 MUX are OR gate O/P The complement of the OR-gate O/P The flip flop O/P The complement of the flip flop output The 1-of-2 MUX consist either The O/P of-the-tri state buffer (2) The flip flop back through a buffer to the AND array based on the state of S1 The four OLMC configuration are Combinational mode with active-LOW O/P Combinational mode with active HIGH O/P Registered mode with active LOW O/P Registered mode with active-High O/P Combinational mode In this mode figure 1.24 have the following condition So=0 & S1=1 this is combinational mode active LOW O/P The 1-of-4 MUX selects OR gate O/P. The O/P polarity is active-LOW because of the inversion of the tri slate O/P buffer. S1=1, So=1-Combinational mode active HIGH O/P

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The 1-of-4 MUX selects the complement of OR gate. The O/P is active-high because of the double inversion (complement of the OR & tri state inversion) The OLMC can be configured as an O/P or an I/P by controlling the tri state O/P buffer Flip flop are not used. The above is output with active LOW Next input of this flip flop and 1-of-4 MUX are not used for combinational I\O 1 1 of 2 MUX S1= 1 Input from the buffer.

2 1 of 2 MUX S1= 0 input from Q* of FF. Registered Mode Registered mode with active HIGH O/P Registered mode with active LOW O/P In this mode the figure 1.24 will have the following conditions S=0 S1=0 selects the FF Q output to 1-of-4 MUX and output will be low. In MUX 1 of 2 S1=0 selects the input of FF output Q*. The above diagram is OLMC in the active-LOW registered mode of the effective logic diagram.

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For condition S1=0 S0=1 selects the Q* output to 1of 4 MUX and output will be high. In MUX 1of 2 S1=0 selects the input of FF output Q*. & the The diagram is OLMC in the active HIGH registered mode effective logic

diagram

Complex programmable logic devices (CPLD) CPLD is a logic device that consist of multiple SPLDS inter connected on a single chipCPLD can be used to implement large logic functions including shift registers A CPLD basically consists of multiple groups of PAL/GAL like arrays with programmable interconnections each PAL/GAL group is called a logic array block (LAB), function block. Each LAB contains several PAL/GAL like array called macro cell. Each LAB can be interconnected with other LAB or to other I/o using programmable interconnect array to form large complex logic functions. Any SOPS function can be implemented.

Micro cells

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Each LAB in a CPLD contains several macro cells CPLD architecture varies from manufactures to manufacture. But generally there are 32 to several hundred macro cells in one LAB. A typical macro cell has an AND array, a product term select matrix, an OR gate and a programmable registers. The logic is similar to OLMC logic in PAL/GAL

Basic CPLD Macro cell Refer basic micro cell diagram 1.31 and logic array block in figure 1.30.

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Each macro cells has a fixed no: of AND gate that feed into a product term selection matrix, where product terms can be selected and applied to an OR gate. Additionally, product term expands inputs from other macro cells allow more product terms to be selected in addition to those from the macro cell AND array. Also, a product term expands O/P provides any selected product term to other macro cells in the LAB or in other LABS through the PIA. The OR gate provides an SOP O/P through programmable select blocks to the I/O or to a flip flop. In this implementation there are three programmable selects, they are essentially data selectors (multiplexers) One programmable select block provides either a global clock or a product term CLK to be used as the clock input for the flip flop. A second programmable select block provides either a global clear or a product term clear to the flip flop. A third programmable select block routes either the O/P of the OR gate or the O/P of the flip flop to the I/O. The OR gate provides an combinational O/P and the flip flop provides a registered O/P. In CPLDS, the term registered is used in reference to the flip flop its associated circuits. The flip flops in a CPLD can be used for implementing shift registers or counters logic. Programmable Interconnect Array (PIA) PIA consists of conductors that run through out the CPLD chip and to which connections from the macro cells in each LAB can be made. By using PIA, any macro cells can be connected to other macro cells within the same LAB, or macro cells in other LABS

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Field programmable Gate Array (FPGA) CPLD consist of multiple PAL/GAL type logic blocks that are linked by programmable interconnection CPLDS are based on SOP logic FPGAS are distinctly different from CPLD in terms of architecture and it offer higher logic capacity. It consist of an array of logic blocks, surrounded by programmable I/O blocks and connected with programmable interconnect. The interconnection between elements are user programmable. FPGA consist of a two-dimensional array of logic block that can be connected by general interconnection resources. The interconnect comprises segments of wire, where The segment may be of various Length. Present in the interconnect are programmable switches that serves to connect the logic blocks to the wire segments, or one wire segment to another. See figure 1.33

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Logic Blocks The structure and content of a logic blocks is called its architecture each logic block in a generic FPGA contains several logic elements. Logic block architecture can be designed in many different ways varies from manufacturer to another. Generally there can be over 10 thousands logic elements in a single chip refer figure1.34 Logic element contains an LUT,(look up table) associated logic and a flip flop Figure 1.35

In the above mentioned logic element contains 4 I/P LUT, it can programmed as a logic function generator. It can be used to produces SOP functions or logic functions such as adder and comparators When configured as an adder, the carry in and carry out allow for adder expansion. Using cascading logic, an LUT can be expanded by cascade with LUT in other logic elements. The programmable selects choose either combinational function from the LUT O/P or registered function from the flip flop O/P The LUT The LUT is a memory device that can be programmed to perform logic function LUT replaces the AND/OR array logic in a CPLD. Consider this logic function Y=ABC+ABC+ABC. When any one of the three product terms appears on the LUT I/PS, the corresponding memory cell storing a 1 is selected and the 1 (HIGH) appears on the output. For any product term that are not part of the SOP function, the LUT O/P is O (LOW)

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FIFO (First-In-First-Out) This type of memory is formed by an arrangement of shift registers. The term FIFO, first in first out data bit written into the memory is the first to be read out. In a conventional register, a data bit moves through the register only as new data is entered FIFO register, a data bit immediately goes through the register to the eight most bit location that is empty

Conventional shift register I\P 0 1 1 0 X 0 1 1 0 X X 0 1 1 X X X 0 1 X X X X 0 Output of FIFO 1.37 BLOCK DIAGRAM FIFO SERIAL MEMORY O\P I\P 0 1 1 0 0

FIFO 1 1 1 1 1 0 0 0 0

This particular memory has 4 serial 64 bit data register and a 64-bit control register (marker register). When data are entered by a shift in pulse, they move automatically sender control of the marker register to the empty location closest to the O/P. Data advance into occupied position. However when a data bit is shifted out by a shift out pulse, the data bits remaining in the register

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automatically move to the next position toward the O/P. In FIFO, data are shifted out independent of data entry, with the use of two separate clocks.Serial memory block diagram is shown figure 1.38. FIFO Application One important application area for the FIFO register is the case in which systems of differing data rates must communicate. Data can be entered into a FIFO register at one rate and taken out at another rate. Irregular rate data to constant rate data lower rate data to higher data rate Constant rate data to lo burst data Burst data to constant rate data Dual Port RAM Dual port RAM are effective devices for high-speed communication between microprocessors. Typical dual port RAM are specialty SRAMS of small size (IK to 4K bytes} and medium speed (2550ns). Because of their relatively low density, it usually impractical in terms of chip count and cost to make large dual port RAM systems from these chips A dual port RAM is a single RAM, typically an SRAM, which can be accessed Simultaneously from two different ports, one port per microprocessor. Each microprocessor sees a simple SRAM interface, and the contents of the SRAM are common to both microprocessor. A block diagram of a dual port RAM in a dual microprocessor system is shown below. In this case, a conventional CPU communicates with a DSP CPU through the common memory of the dual port RAM FIGURE 1.39 shown above. A true port RAM has one set of SRAM cells and two independent sets of addressing logic, called ports. The RAM cells may be read on written by either side independently and simultaneously. This capability is valuable because each port may access the RAM cells without regard to activities on the other port. There is one exception to this simultaneous access. If one port is writing to a cell while the other port is reading the same cell, the data may be changing during the read which could cause errors. Most dual port RAMS provide address contention logic to prevent this unlikely condition by causing one side to wait if both are trying to access the same cell True dual port RAM, have some limitations. The dual port RAM cell is approximately twice as large as its single port SRAM counter port. This makes true dual port RAMS more

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expensive than SRAMS, especially at higher densities. However three is more than one way to achieve the dual port RAM function They are Time shared Dual port SRAM Time shared dual port SRAM using quick switches Ping-pong dual SRAM Features of DS 1609 Dual port RAM -Totally asynchronous 256-byte dual port memory -Multiplexed address and data bus keeps pin count low -Deal port memory cell allows random access with minimum arbitration -Each port has standard independent RAM control signals -Fast access time -Low power CMOS design -24 pin DIP or 24 pin SOIC surface mount package -Both CMOS & TTL compatible Description The DS1609 is a random access 256-byte dual port memory designed to connect two asynchronous address/data buses together with a common memory element. Both ports have unrestricted access to all 256 bytes of memory and with modest system discipline no arbitration is required Each port is controlled by three control signals : O/P enable, write enable, port enable The obvious advantage of the multiplexed bus is the slightly reduced system performance because address and data information is being transmitted serially. The equally obvious advantage is the reduced pin count achievable by multiplexing the addressing and data buses.The pin diagram is shown Fig 1.40 above. OPERATION READ CYCLE A read cycle to either port begins by placing an address on the multiplexed bus pins ADO-AD7. The port enable control (CE) is then transitioned low. This control signal causes address to be latched internally. Addresses can be removed from the bus provided address hold time is met. Next, the output enable control (OE) is transitioned low, which begins the data access portion of the read cycle. With both CE and OE active low, data will appears valid after the output enable access time. Data will remain valid as long as both port enable and output enable occurring rising remains low. A read cycle is determinate with first (edge of either CE or

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DE. The address/data bus will return to a high impedance state after time TCEZ or toez as referred to the first occurring rising edge. We must remaining high during read cycle toez)edge of either CE or OE. OPERATION WRITE CYCLE A write cycle to either port begins by placing an address on the multiplexed bus pins AD0-AD7. The port enable control (CE) is then transitioned low. This control signal causes address to be latched internally. As with a read cycle, the address can be removed from the bus provided address hold time is met. Next the write enable control signed (WE) is transitioned low which begins the write data portion of the write cycle. With CE and WE active low the data to be written to the selected memory location is placed on the multiplexed bus. The data setup (tps) and data hold time (tdh) times are met, data is written into the memory and the write cycle is terminated on the first occurring rising edge of either CE or WE. Data can be removed from the bus as soon as the write cycle is terminated. OE must remain high during write cycles. ARBITRATION THE DS1609 DUAL PORT ram has a special cell design that allows for simultaneous accesses from two ports. Because of this cell design, no arbitration is required for read cycles accessing at the same instant. However, an argument for arbitration can be made for reading and writing the cell at the exact same instant for writing from both ports at the same instant. A simple way to assure that read / write conflicts dont occur is to perform redundant read cycles. Write/write arbitration needs can be avoided by assigning groups of addresses for write operation to one port only. Groups of data can be assigned check sum bytes which would guarantee correct transmission. A software arbitration system using a mail box to pass status information can also be employed each port could be assigned a unique byte for writing status information which the other port would read. The status information could tell the reading port if any actively is in progress and indicate when activity is going to occur. Interfacing of DS1609 with microprocessor For implementation with the Intel 8086/8088 microprocessor family, the address/data pins of either port may be tied directly to the lower 8 address data lines of the Intel 8086 or 8088. The active-low RD pin from the microprocessor provides the active-low OE input to the port on the DS1609, while active-low WR provides the active-low WE input to the port. The ports active low CE input may be conditioned by a system decoder, which would require the 8086 ALE output as an input to provide address latching. Several of the un used address/data lines from the 8086 would also be required as input to indicate the DS1609 resides in the system memory map. In application where multiple DS 1609 ports are required, multiple active-low CE

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outputs could be provided from a system decoder using the ALE signal from an Intel 8086/8088 with user specified address lines to generate multiple chip selects.

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Micro controller Based system Design Embedded C Compiler 2

Compiler translates program written in high level language into assembly language. Advantages Easy source code portability Multiplatform programming Easier is to modify and update Reduction of the development time and the development costs The source codes are more readable Lucidity of the Source codes of the program and global implication of the developing process Optimization and validation tools

Module

Disadvantage Higher price of the high quality development tool Higher data and code memory requirements More difficult to learn. Header file Data types CX51 provides a number of basic data types. It offers standard C data types and also supports 8051 platform.
Data types Bit Signed character Unsigned character Signed integer Bytes 1 bytes 1 bytes 1 bytes 2 bytes Value range 0 to 1 -128 to 127 0 to 255 -32768 to +32767

# include < reg 51.h>

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Unsigned integer S bit S fr

2 bytes 1 bytes 8 bit

0 to 65535 0 to 1 0 to 255

Loop( generating delay) For (x=0 ; x<400 ; x++) (for delay) For (o, o,) repeat forever

While (1) repeat forever While (x==1); wait until x=0 Generating delay for 250 ns Void MS Delay (unsigned int value) declaration MS delay fn calling Void MS Delay (unsigned int time) unsigned int I,j i For (i=o; i< I time; i++ Memory Areas 8051 supports a number of physically separate memory and spaces for program and data. Memory models Determine default memory type to use fr arguments, valuables, declarations etc. 3 Types :Small, Compact, Large - Control directives (memory models) Small Model In this model all variables, by default, reside in the internal data memory (256 bytes) Variable access is very efficient best model However all objects as well as stack must fit to internal Compact Model All variables reside in one page of external d memory (256 bytes maximum)

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Limitations is due to addressing scheme used (indirect), @ R, Not efficient as small but faster than large modes Large model All variables reside in external data memory (up to) 64 bytes) DPTR is used for addressing Memory access through DPTR is inefficient Data access generates more code than the small compact models. memory model Memory Models Tiny Small Medium Compact Large Huge Memory model determines the default memory selection for variables. Unless special reasons exist, we should always use the small memory model. The programs will run faster and code generated will be smaller. C 166 users guide memory models

1. Tiny Memory Model Used for program those are limited to 2 K bytes in size Do not use external data memory all Compiler generates ACALL & AJMP instruction instead of LCALL & L J M P. No references to external data memory are allowed. So the complier well never generate the MOVX instruction Tiny & SMALL memory models are identical Variables are stored in near memory Functions are stored in near memory and are accessed

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Using near calls -generates 16 bit line as addresses by limiting codes -Generate data space to 64 K -This memory model is the best choice for program that have small code & small data requirements. It do not require access to additional address space. 2. Small Memory Model (Total RAM 128 bytes) - All variables and parameter passing segments will be placed in the 8051 internal memory. -Used for target systems do not have external data memory or where the data requirements of the program allow small memory model to be used. -Local variables & function arguments are located in internal data memory -By default global & static variables are located in internal data memory unless they are constant objects. -By using-x data keyword, we can make global & static variables (located) in external data memory -Single chip 8051 users may only use the SMALL models, unless they have an external ram -Variables are stored in near memory -Functions are stored in near memory and are accessed using near cells -This memory model is the best choice for programs that have small code & small data requirements 3. MEDIUM MEMORY MODEL -For application using larger amounts of RAM, this model will allow the use of external data memory. -Code efficiency is not quite as good as the small model, due to the over heads of addressing XDATA memory -compiled stack is still used like small model Static & global are in XDATA memory -Variables are stored in near memory

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-Functions are stored in for memory and are accessed using far calls. -This memory model is the best choice for programs that have large code & small data requirements. 4. COMPACT MODEL (Total RAM 256 bytes off-chip, 128 or 256 bytes on-chip) All variables by default reside in one page of external data memory. -This memory model can accommodate a maximum of 256 bytes of variables. -The limitation is due to the addressing scheme used, which is indirect through registers R0 & R1 (@R0,@R1) -It is not as efficient as the small model therefore variable access is not as fast. -However the compact model is faster than large model -Variables are stored in far memory -Functions are stored in near memory and accessed using near calls. -This model is the best choice for programs that have small code & large data requirements 5. LARGE MODEL -All variables, by default, reside in external data memory (up to 64 K bytes) -Variables..are placed in external memory addressed by @ DPTR -Local variables and function arguments are located in x data memory -By default, global & static variables are located x data memory unless they are const. object (which are located in program memory) -If the target s/m has no x data memory, the large memory cannot be used -This permits slow access to a very large memory space & easiest model to use. -Not often used for an entire program. Code Optimization

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Optimization techniques are used to produce smallest, fastest code possible. They are independent of the target processor and the code generation strategy. Some of the optimizations performed include. Constant folding :

Constant expressions (including floating point) are evaluated at compile time. Expressions only involving constants are replaced by their result. Strength reduction:

Multiplication is reduced by shifting and adding where possible. Expression reordering

Expressions are reordered and associative operators grouped to minimize complexity i.e. expressions are rearranged to allow more constant folding. -Expression simplification : Multiplication by 0 or 1 and addition or subtractions of 0 are removed. Such useless expressions may be introduced by macros in C or by the compiler itself. -Logical expression optimization : expressions involving , 11 and 1 are interpreted and translated into a series of conditional jumps. * Common code elimination / merging Where separate pieces of code produce common sequences they are merged. -Constant copy propagation: - A references to a variable with known contents is replaced by those contents. -Common sub expression elimination: - The compiler has the ability to detect repeated uses of the same (Sub-) expression such a common expression may be temporarily saved to avoid recomputation. This method is called common sub expression elimination (CSE) * Global Register Allocation Registers ae allocated to variables and temporaries based on function-wide analysis of variable usage. -Register parameters :- Function parameters are passed in registers where possible * Jump / Branch Optimization

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-Loop rotation: - With for and while loops, the expressions is evaluated once at the top and then at the bottom of the loop. This optimization does not save code, but speeds up execution. -Switch optimization: - A number of optimizations of a switch statement are performed, such as the deletion of redundant cause labels or even the deletion of the switch. -Control flow optimization: - By reversing jump conditions and moving code, the number of jump instructions is minimized. This reduces both the code size and the execution time. -Remove useless jumps: - An unconditional jump to a label directly following the jump is removed. A conditional jump to such a label is replaced by an evaluation of the jump condition. The evaluation is necessary because it may have side effects. -Conditional jump reversal :- A conditional jump over an unconditional jump is transformed into one conditional jump with jump condition reversed. This reduces both the code size and execution time. -Loop optimization: - In variant expression may be moved out of a loop and expressions involving an index variable may be reduced in strength. -Loop un rolling Eliminate short loops by replacing them with a number of copies * Dead code elimination

Unreachable code can be removed from the intermediate code without affecting the program. However, the compiler generates a warning message, because the unreachable code may be result of a coding error. Sharing of string literals and floating point constants

String literals and floating point constants are put in ROM memory. The compiler overlays identical strings and let them above the same space, thus saving ROM space. Like wise identical floating point constants are overlays and allocated only once. Frequency reduction

Execution time of a program can be reduced by moving code from a part of a program which is executed very frequently to another part of the program which is executed fewer times. 89C2051 Microcontroller 89C2051 and 89C51 are CMOS 8 bit microcontroller both have flash programmable and erasable read only memory (PEROM) [Flash memory is a non-Volatile memory, which can be

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electrically erased for lines and blocks. The mechanism for erasing the memory is easier and faster than that needed for E2 PROM, ie there is no waiting time for erasing the program memory] Both devices have the same instruction set as that of 8051. Both support fully static operation. Operating frequency could be from OHZ to 24MHZ. 89C51 is a 40-pin device and 89C2051 is a 20-pin device 89C2051 has two timers and 2K flash PEROM. 89C2051 Architectures over view The architecture is similar to 89C51 except port 0 port 2. Analog comparator is not available for 89C51.No Port three alternate function like RD,WR,ALE,EA etc. The architecture is shown below both 89C51 and 89C951. The memory organization of both 89C51 and 89C2051 also given in fig 2, fig2.1

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ARCHITECHURE OF 89C51

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89C51 PIN DIAGRAM Features of 89C51 89C51 has 4K on chip flash program memory It has 2 16bit timer /counter It has one full duplex, serial port. It has 128 bytes of on-chip RAM It has 32 I/O lines It has on chip oscillator and CLK circuitry It has 6 interrupt sources 89C2051 has a precision analog comparator P3.6 is not available externally, however, it can be read in software. P3.6 is the output of the precision analog comparator. It has 15 I/O lines. Only P1 &P3 are available Program written for 89C51 may not always work an 89C2051 because of the absence of ports P0 & P2 in 89C2051

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Any program related to 89C2051 precision comparator will not work on 89C51 Register structure, memory organization is almost same that of 89C51 The architecture does not support any external address/data bus and therefore RD, WR signals are absent in 89C2051 Similarly ALE, PSEN, EA signals are not there in 89C2051 89C2051 supports the full duplex serial communication and 6 interrupt sources It has idle mode and power-down mode

Pin diagram of 89C2051

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Precision analog comparator 89C2051 has a precision analog comparator. Pin P12 and pin P13 are the corresponding inputs. P3.6 is the output of this comparator accessible though software A. Precision analog comparator may be used for application where a comparison between the desired value and actual value is required. Power Saving Options The power requirement of a microprocessor board is a very important aspect. There are power saving methods based on oscillator frequency, power down & idle modes. Fully static operation 0 to 24MHZ frequency Important factor in selecting the oscillator frequencies are the power dissipation and speed of operation required.

Idle mode CPU to sleep On chip peripherals operational Internal clock signal to CPU is gated off Clock to time r, interrupt and serial port function continues Contents of on-chip RAM and all SFRs and complete CPU status including the PSW, stack pointer, accumulator are preserved To enter into ups idle mode, IDLE bit in PCON is to set by software Come out from idle mode by software By have were reset Activation of an enabled interrupt

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Power down mode Oscillator is frozen No clock is generated On chip RAM-SFRS maintain their values Hardware reset is the only way to come out of power down mode Reset action will modify SFRs but the one chip RAM will be pressured

Memory Organization of 89C 51 89C51 has internal RAM and ROM memory for variable data and program codes respectively. 4K Rom (or E2 PROM) is used for program codes and 128 byte internal RAM is used for data .figure is shown above fig 2.1 The 128 byte RAM is organized into 3 distinct areas as1. 32 bytes from address 00-IF that make up 32 working register, organized on 4 register banks of 8 register each. Bank is selected by the RS and RS o pins of PSW. Eight registers is named as R0-R7 in each bank. Register bank 0 is selected on reset. 2. A bit addressable area of 16 byte occupies RAM byte address 20h to 2Fh. There are a total of 128 bits in this area, which corresponds to the 128 byte of RAM. e.g. byte address 4FH is equivalent bit 7 of byte address 29. 3. A general purpose RAM area above the bit area, from 30H to 7FH, addressable as bytes. 128 byte internal RAM +128 bytes of SFRS is collectively known as the data memory. The 4K ROM is used for program codes. It is arranged as registers (8bit) of address from 0000 to OFFF. The additional memory can be added externally using suitable circuits. The program addresses higher than OFFF will cause the 89C51 to automatically fetch code bytes from external memory. This internal and external ROM collectively known as program memory.

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LED and Switch Interfacing Refer figure 2.2 above shows how LED and switch is connected with 89C51 When switch is pressed, LED should blink

Algorithm 1. 2. 3. 4. 5. 6. 7. Start P1.5 as I/p pin Put p1.7 (LED) is in OFF state (by setting the pin) Check whether switch is pressed, i.e. p1.5 is ground or not P1.5 is connected to ground, LED should be on by clearing the pin Continue END

Assembly Code ORG SETB WAIT: SETB JB GLOW CLR JNB SJMP END 0000H P1.5 P1.7 P1.5, P1.7 P1.5 GLOW WAIT (LED OFF) WAIT

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Interfacing Seven-Segment Display Seven segment displays commonly contain LED segments arranged as an 8, with one common lead (anode or cathode) and seven individual leads for each segment. 2 types of seven segment display Common Cathode Common Anode

Figure 2.3

figure 2.4

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Seven segment display

In order to display 1, the corresponding segments (b,c ) should be enabled In common cathode, each segment well be lit only if the segment line brought high and common cathode is brought low.

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In common anode, each segment will be lit only if the segment line brought low and common anode is brought high. Common cathode DP 0 g 0 f 0 e 0 d 0 to display 1 c b a 1 1 0 06H

Common Anode DP 1 g f c 1 1 1

to display 1 d c b a F 9H

1 0 0 1

Before writing the program, we have to create a LUT containing the seven segment pattern to display the corresponding hex digit

We can now interface a single 7-segment to microcontroller but for interfacing multiple 7 segment are use scanning principle where one 7 segment is displayed after another, but this process is very fast hence the flickering cannot be seen by human eye

Interfacing of Multiple 7-segment display For displaying 2 digit no using single module 7-seg. For displaying a 2 digit no loaded from a single port on two single module displays using multi-flexing. We use scanning principle for interfacing multiple 7 segment display, but this process is very fast hence the flickering cannot be seen by human eye.

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Figure 2.5 Refer the interface diagram is shown in fig 2.5 in the first module.

Assembly language ORG 500H DB 40H, 79H, 24H, 30H, 19H, 12H, 02H, 78H, 00H, 10H, 08H, 03H, 46H, 21H, 06H, OCH ORG 0000H MOV P1, #OFFH MOV DPTR, #500H CLR P3.0 CLR P3.1 MOV A, P1 MOV R3, A ANL A, # OFH

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MOVC A, @ A+DPTR SETB P3.0 MOV P2, A ACALL DELAY MOV A,R3 ANL A, # OFOH SWAPA MOV C, A @A+DPTR MOV A,R3 SWAP A MOVC A, @A+DPTR CLRP3-0 SETB P3-1 A CALL DELAY SJMP TOP DELAY : MOV R4, # 01FH LOOP 2 : MOV R5, # 01FH LOOP 1: DJNZ R5, LOOP1 DTNZ R4 LOOP2 RET 7 segment displays interface

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This seven segment display interface connected to the 89C2051 micro controller using port P1,and port P3. The control is made by software control of the two ports programs. No separate driver or decoder is required for this configuration. It is a common cathode configuration. By enabling the output P1.0 to P1.6 to high level positive voltage will be applied to a b c d e f g anode of the seven segment display. Port P3.0 to P3.3 will drive the cathode transistor. If output P3.0 to P3.3 is enabled by high voltage the transistor BC 547 is switched on which in turn supplies GND potential to the cathode. The current through the LED can be limited by a resister R220. If you want to reduce the current the value of the register can be increased. The seven segment codes and cathode of seven segment code is to be stored in the registers and outputted periodically. The period of updating the LED should be such that our eye should not able to distinguish the period. The frequency of up dating should be more than 20HZ i.e. our persistence of an eye. Take 100HZ is the updating time i.e. 10 m second; we have to refresh 4 no 7 segment display. one seven segment display is refreshed every 2.5 m sec. This can be achieved by enabling a interrupt for every 2.5 m sec and service it so that the seven segment display is up dated by software. Every interrupt the timer THI and TLI should be updated and seen segment display code is to be inputted through port 1 & port 3. Display 1to 4 pointer is to be updated for every interrupt.

Now by the control of software the seven segment interface can be achieved. It is not required any BCD driver or transistor driver chip. The designer should decide, the configuration by considering. -cost -space -time -system capacity

Assembly Language ORG 000H SJMP Start ORG 001 BH

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SJMP INT-T1 START MOV SP # 54H MOV RO # 40H MOV TMOD # IOH MOV TLI # COUNT L MOV THI # COUNTH SETB ETI SETB EA Enable timer global interrupt Start timer 1 Wait for interrupt Initialize stack pointer Pointer of Internal RAM Timer is mode 1 Timer for refresh 3msc T1

SETB TRI SJMP $ INT. Ti = MOV TLI # COUNTL MOV THI # COUNTH MOV PI @ RO INRO MOV P3 @ RO INRO CJNE R, # 48h MOV RO # 40H NEXT Dia R E T I

Least significant digit Increment next memory Load cathode out put Increment Next check for 48 If so R0=40 H

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LCD INTERFACE LCD liquid crystal display is a better use for any text messages. It consumes very less power compare to LED display. For better use of interaction LCD more suitable display. Now LCD controller same available which can be directly connected to all micro controllers. Even serial interface also available in LCD controllers. LCD displays are available 16x2 characters or 20x2 characters. Totally 2 lines with either 16 or 20 characters. All LCD controllers have data lines and controller lines to interface with micro controllers.

LCD pin descriptions

HD 4480

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-EN- enable line that indicates micro controllers sending the data RW/Write =0 Read=1 RS Register select 0-Command register 1-data register Enable signal is used for read/write or register select function. The instruction being executed by LCD is mainly depends up on the frequency at which control signal generated. If the command instruction is not completed and the controller executive some other operation then the LCD controller will hang it self. In order to avoid the frequency dependency LCD status can be made available in data bit 7. If the bit 1 the LCD controller is executing command and it is not busy If data bit 7-0 watch dog time can be utilized for not receiving not busy condition in definite. So that we can come out of the software loop. LCD instruction allow the display function to select such as cursor, left, cursor right clear the display, character fond, cursor blank number of times, no of data bus bits, display shift left, display shift right etc. To send any command Rs=0 and enable line 1 and for writing text or data EN=1, Rs=1, R/W =0

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During power on reset please ensure LCD is ready for receiving command or data. Normally wait for 15 m sec and provide necessary data to it. LCD HD44780 is connected to 89C51, port 1 and port 3. The data lines are connected to port 1 for programming command and input text data to the LCD Port 3 outputs the control signals RS, RW, EN lines Data D7 bit is polled for the LCD busy. Status for writing command or text. refer diagram 2.10 above Programming of LCD Text in the Display by 89C51 EN RS RW EQU EQU EQU P3.2 P3.1 P3.3 P1.7 8 bit data is 2 lines display (5x7 character (DL,N,F) Turn on LCD and cursor (D, C) (Move cursor position right automatically)

BUSY EQU MOVA #38h

CALL LCD COMD MOVA # OEH CALL LCD COMD CALL LCD COMD MOVA # O1H CALL LCD-COMD MOVA # L CALL LCD TEXT MOVA # C CALL LCD TEXT

clear display cursor at home

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MOVA # D CALL LCD TEXT LOOP SJMP LOOP LCD COMD CLR C CALL Write Ret LCD Text SETB C turn on cursor Turn off cursor in definite loop

CALL write RET WRITE Set b Busy Set b RW CLR RS WAIT set b EN CLR EN Tb Busy WAIT MOV RS, C MOV P1, A Clr RW Set b EN Clr ENEND 1 to 0 for execute the command Test bit Db7=1 IS/LCD BUSY if busy wait Test or command information in C, flag put in RS Test or command 8 bit to LCD write operation p1.7 busy line as an input read from LCD Select command register RS=0 command 1 to 0 an EN line

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LCD INTERFACING LCD discussed in this section has 14 pins. The functions of each pin is given below. 1. 2. 3. 4. VSS VCC VEE RS 01Ground +5V power supply power supply to control contrast Register select Select command register Select data register 0-for write 1-for read 6. E Enable pin

5. R/W

(7-14)DBO-DB7-8 bit data buses VCC and VSS provide _5V supply and VEE is used for LCD contrast. There are two important registers inside the LCD RS pin is used for their selection. If RS=0, the instructions command code register is selected, allowing user to send a command such as clear display, curser at home etc. If RS=1, data register is selected in order to send data to be displayed. The enable pin is used to latch the information presentation to its data pins. A H to L pulse must be applied to this pin for latching. LCD command codes 01 02 06 OE 80 38 clear display screen Return home increment cursor display on, cursor blinking Force cursor to the beginning of 1st line 2 lines and 5X7 matrix. Etc.

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Programming steps 1. 2. 3. 4. 5. 6. Select 2 lines 5x7 matrix Display on, cursor on Clear LCD Shift cursor right Move cursor to beginning of 1st line send data to be displayed

PROGRAM TO DISPLAY NO in LCD (USING PORT2 0) MOV A, #38 A CALL COMMAND A CALL DELAY MOV A, # OE A CALL COMAND A CALL DELAY MOV A, #01 A CALL COMMAND A CALL DELAY MOV A, #06 A CALL COMMAND A CALL DELAY MOV A, # 81 A CALL COMMAND A CALL DELAY MOV A, # N A CALL DATA A CALL DELAY DATA CLR SETB CLR RET MOV PI,A SETB CLR SETB CLR RET DELAY MOV R3, #50 H2 H1 MOV R4 #FF DJNZ R4, H1 P2.0 P2.1 P2.2 P2.2 A CALL DATA A CALL DELAY HERE : SJMP HERE COMMAND : MOV P1,A CLR P2.0 P2.1 P2.2 P2.2

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MOV A, # 0

DJNZ RET END

R3

H2

Electromechanical Relays A relay is an electrically controllable switch widely used in industrial controls, automobiles and appliances. It allows the isolation of two separate sections of a system with two different voltage sources. For e.g. +5V system can be isolated from a 120V system by placing a relay between them. One such relay is called an electromechanical relay. The electromechanical relays have three components - coil, spring and contacts. When current flows through the coil, a magnetic field is created around the coil (coil is energized) which causes the armature lobe attracted to the coil. The armature contacts acts like a switch and closes or opens the circuit. When coil is not energized, a spring pulls the armature to its normal state of open or closed.

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Driving a relay Digital systems and microcontroller pins lack sufficient current to drive the relay. While the relays coil needs around 10 mA to be energized, microcontroller pin can provide a maximum of 1-2m A current. For this reason we place a driver such as the ULN 2803 or a power transistor between the microcontroller and the relay. In choosing a relay, the following characteristic need to be considered.

1) The contacts can be normally open (No) or normally closed (NC). In the NC type, the contacts are closed when the coil is not energized. In No, the contacts are open when the coil is energized. 2) The current and voltage needed to energize the coil. The voltage can very from a few volt to 50V, while the current can be from a few mA to 20mA depends upon relay type. The relay has minimum voltage, below which the coil will not be energized. This minimum voltage is called the pull-in voltage. In the datasheet for relay, we see coil resistance V/R gives pull in current. For example if coil voltage is 5V & coil resistance is 500 ohms, we need a minimum of 10 mA (5/500 ) pull in current. Interfacing diagram shown in fig 2.12 Port pin can per of 20mA current to drive the relay. So base resistance around 1 K result into this much basic current. Now, base as the current through an inductor cannot be suddenly reduced to zeros, a free wheeling diode is employed. A free wheeling diode across the relay coil is required because when the transistor is switched off, the energy stored already in the inducator can be dissipate through the diode and internal resistance of the inductor . The operation of this circuit is very simple. If the port pin is made high, the basic current flows and the transistor is switched on. This will cause collector current that also flows through the relay coil. Thus, the contact will be closed. Putting O on port pin makes the transistor off the inductor current now flows through the free wheeling diode and slowly decays to zero as power is dissipated in the internal resistance of the coil and internal diode. PGM for light the lamp for 1 see and off it for isec ORG 0000H MAIN SETB p1.0

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MOV R5,#55 ACALL DELAY CLR P1.0

MOV R5,#55 ACALL DELAY SJMP MAIN DELAY: H1: H2: H3: MOV R4,#100 MOV R3,#253 DJNZ R3,H3 DJNZ R4,H2 DJNZ R5H1 RET TRAFFIC LIGHT CONTROL

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Consider a 4 way junction as shown fig 2.13. There are two lights in each direction. One Red and One green. Green for permitting vehicles on that way and Red for stopping. We can control these traffic lights by the use of a Microcontroller. If we are using bulbs, we cannot connect it directly to MC, because it cannot drive the bulb. Then we connect it through relays as shown above diagram fig2.14.

Here when the port pin activates relay operates and thus the bulb glows. When the port pin make Zero LED will glows : when it is one LED will OFF. We prefer this method. The condition for traffic control is; permit vehicles only in one direction. I.e. only one green light. Will glow at a time and, in all other direction, red will glow. For this we connect these lights (Say LEDS) to a port as shown :

If we want to glow GA (green in North direction) make P1-0 low. At that time all other green will be off by making corresponding pins high. All reds except RA will glow. I.e. for passage of vehicles in north direction, we have to store ; To port 1. It will make green in north direction and Red in all other direction After a delay make the next green to glow and red in all other direction and so on, Bit Sequence 0110 1010 1001 1010 1010 0110 1010 1001 PROGRAM BACK : MOV A, # 6A MOV P1, A # make flow in North direction Hex Code 6A 9A A6 A9 passage in N direction passage in W Direction passage in S direction passage in E direction

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ACALL DELAY MOV A, # 9A MOV P1, A A CALL DELAY MOV , # A6 MOV P1, A A CALL DELAY MOV A, # A9 # Make flow in East direction # make flow in South direction # make flow in West direction

MOV P1, A A CALL DELAY SJMP, BACK

DELAY : MOV R3, #50 HERE2 : MOV R4, #255 HERE : DJNZ R4, HERE DJNZ R3, HERE 2 RET If we are using bulbs, we can glow it by making corresponding port pins high. Ie just opposite of the above operation. Then the hex codes are; 95H, 65H, 59H, and 56H respectively.

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Trainer kit design The typical trainer kit design shown in figure 2.15

MODULE-3
ANALOG TO DIGITAL CONVERTER

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An ADC produces a digital output that is proportional to the value of the input analog signal. When an analog signal is processed by a digital system, an ADC is used to convert analog voltage to digital form suitable for processing by a digital system. Types of ADCs 1) DELTA SIGMA ADC

FIGURE 3.1 In a convertor, the analog input voltage signal is connected to the input of an integrator, producing a voltage rate- of change or slope, at the output corresponding to input magnitude. This ramping voltage is then compared against ground potential (0Volts) by a comparator. The comparator acts as 1-bit ADC, producing 1 bit of output depending on whether integrated output is positive or negative. The comparators output is then latched through a D-type flip flop clocked at a high frequency, and fed back to another input channel on the integrator to drive the integrator in the direction of a 0 volt output. This method is based on the data modulation where the difference between 2 successive sample is quantized delta modulation is a 1 bit quantization method. The O/P of a delta modulator is a single bit data stream where the relative number 1 is and 0s indicates the level or amplitude of the input signal. The number of 1 is over a given number of clock cycles establishes the signal amplitudes during that interval. A max number of 1 is corresponds to the max positive i/p voltage. A number of 1 is equal to the one half the

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maximum corresponds to the i/p V. This is shown in figure below. E.g.:- assume that 4096 is occur during the interval when the i/p signal is a +ve menu. Since 0 is the mid point of the dynamic range of the i/p signal, 2048 is occur during the interval when the i/p s One of the more advanced ADC technologies is the so-called delta-sigma, or (using the proper Greek letter notation). In mathematics and physics, the capital Greek letter delta () represents difference or change, while the capital letter sigma () represents summation: the adding of multiple terms together. Sometimes this converter is referred to by the same Greek letters in reverse order: sigma-delta, or . In a converter, the analog input voltage signal is connected to the input of an integrator, producing a voltage rate-of-change, or slope, at the output corresponding to input magnitude. This ramping voltage is then compared against ground potential (0 volts) by a comparator. The comparator acts as a sort of 1-bit ADC, producing 1 bit of output ("high" or "low") depending on whether the integrator output is positive or negative. The comparator's output is then latched through a D-type flip-flop clocked at a high frequency, and fed back to another input channel on the integrator, to drive the integrator in the direction of a 0 volt output. The basic circuit looks like this:

The leftmost op-amp is the (summing) integrator. The next op-amp the integrator feeds into is the comparator, or 1-bit ADC. Next comes the D-type flip-flop, which latches the comparator's output at every clock pulse, sending either a "high" or "low" signal to the next comparator at the top of the circuit. This final comparator is necessary to convert the single-polarity 0V / 5V logic level output voltage of the flip-flop into a +V / -V voltage signal to be fed back to the integrator. If the integrator output is positive, the first comparator will output a "high" signal to the D input of the flip-flop. At the next clock pulse, this "high" signal will be output from the Q line into the noninverting input of the last comparator. This last comparator, seeing an input voltage greater than the threshold voltage of 1/2 +V, saturates in a positive direction, sending a full +V signal to the other input of the integrator. This +V feedback signal tends to drive the integrator output in a negative direction. If that output voltage

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ever becomes negative, the feedback loop will send a corrective signal (-V) back around to the top input of the integrator to drive it in a positive direction. This is the delta-sigma concept in action: the first comparator senses a difference () between the integrator output and zero volts. The integrator sums () the comparator's output with the analog input signal. Functionally, this results in a serial stream of bits output by the flip-flop. If the analog input is zero volts, the integrator will have no tendency to ramp either positive or negative, except in response to the feedback voltage. In this scenario, the flip-flop output will continually oscillate between "high" and "low," as the feedback system "hunts" back and forth, trying to maintain the integrator output at zero volts: Signal is a ve maximum. SUCCESSIVE APPROXIMATION ADC

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FIGURE 3.2 It consists of a very special counter circuit known as a successive approximation register. Instead of counting up in binary sequence, this register counts by trying all values of bits starting with the MSB and finishing at the LSB. Throughout the count process, the register a monitor the comparators output to see if the binary count is less than or greater than the analog signal input, adjusting the bit values accordingly. The way the register counts is identical to the trial and fit method of decimal to binary conversion, whereby different values of bits are tried from MSB to LSB to get a binary number that equals the original decimal number. The advantage to this counting is much faster results the DAC output converges on the analog signal input in much larger steps than with the 0 to full count sequence of a regular counter. Figure shows a basic block diagram of a 4 bit successive approximation ADC. It consist of a DAC, SAR and comparator. The bits of ADC are enabled one at a time. Starting with the MSB. As each bit is enabled, the comparator produces an o/p that indicate whether the analog i/p voltage is greater or less than the o/p of DAC. If the D/A o/p is greater than the analog i/p, the comparators o/p is now, causing the bit in the register to reset. If the DAC o/p is less than analog. i/p the bit is retained in the register. In order to better understand the operation, take a 4 bit conversion. Assume that DAC has the following characteristics. V out = 8V, for 23 bit,(MSB), v out =4V, for the 22 bit, V out=2V for 21 bit and v out=IV for the 20 bit (LSB FLASH ADC

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FIGURE 3.3 It is also called parallel A/D connecter. It is formed of a series of comparators, each one comparing the input signal to a unique reference voltage. The comparator outputs connects to the input of a priority encoder circuit, which then produces a binary output. V ref is a stable reference voltage provided by a precision voltage regulator. As the analog input voltage exceeds the reference voltage at each comparators, the comparator outputs will sequentially saturate to a high state. The priority encoder generates a binary number based on the highest-order active input, ignoring all other active inputs. An additional advantage of the flash converter is the ability for it to produce a nonlinear output. With equal-value resistors in the reference voltage divider network, each successive binary count represents the same amount of analog signal increase providing a proportional response. 2) SINGLE SLOPE ADC In this system a continuous sequence of equally spaced pulses is passed through a gate. The gate is normally closed and is opened at the instant of the beginning of a linear ramp. The number of pulses which pass through the gate is proportional to the voltage being measured. The clear pulse resets the counter to the zero count. The counter then records in binary form the number of pulses from the clock time. The clock is a source of pulse. Since the number of pulses counted increases linearly with time, the binary word representing this count is used as the input of D/A converter. As long as the analog input Va is greater than Vd, the comparator

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output is high and the AND gate is open for the transmission of pulses to the counter when Vd exceeds Va, the comparator output changes to the low value and the AND gate is disable.

FIGURE 3.4

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It does not require a D/A converter. It uses a linear ramp generator to produce a constant slope reference voltage. All the beginning of the conversion cycle the counter is reset and the ramp generator 0/p is 0 V. The analog i/p is greater than the sequence voltage at this point and therefore produce a high o/p from the comparator. This high enables +ve clock to the counter and starts the ramp generator. Assume that the slope of ramp is iv/ms. It will be increase until it equals the analog i/p. At this point the ramp is reset and binary count is stored in the latches by the control logic. Let us assume that the analog i/p is 2 v at the point of comparison. This means the ramp is also 2V and has been running for 2ms. Since the comparator o/p has been high for 2ms, 200 clock pulses have been allowed to pass through the gate to the counter. At the point of comparison, the counter is in the binary state representing decimal 200 with the proper scaling and recording, this binary number can be displayed as 2.00 V. 3) DAUL SLOPE ADC The analog part of the circuit consists of a high input impedance buffer A, precision integrator A2 and a voltage comparator. The converter first integrates the analog input signal Va for a fixed duration of 2 n clock periods. Then it integrates an internal reference voltage VR of opposite polarity until the integrator output is zero. The number N of clock cycles required to return the integrator to zero is proportional to the value of Va averaged over the integration period. N represents the desired output code.

FIGURE 3.5 The operation of this type of ADC is similar to that of the single slope ADC. Except that a variable slope ramp and a fixed slope ramp or both used. This converter in common is digital voltmeters and other types of measurement instruments.

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A ramp generator A is used to produce the dual stope characteristics. Assuming that the counter is reset and o/p of the integrator zero. Now, assume that a + ve i/p v tg is applied through the switch as selected the control logic. Since the inverting up of A1 is at virtual ground and assume that Vin is constant for a period of time, here will be constant current through the i/p resistor R and thereafter the capacitor C . C with charge linearity as the current is constant, and thus a ve going linear vtg. Ramp on the o/p of A1. When the converter reaches a specific count, it will be reset, and the control logic will switch the ve reference voltage (-vref) to i/p A1. This point, the capacitor is charged to a negative (-ve) proportional to the i/p analog voltage.

Now capacitor discharges linearly due to the constant current from the v ref. This produces a +ve going ramp on the A1 o/p starting at ve end with a constant slope that is independent of this charge voltage. As the capacitor discharges, the counter advances from reset state. The time taken to discharge to zero depends on the initial voltage ve across the discharge rate is constant. When the integrator o/p reaches zero. The comparator switches to the low state disable the clock to the counter. The binary counter is proportional to this because it takes the capacitor to discharge depends only on ve and the counter records this interval of time

DIGITAL TO ANALOG CONVERSION Digital to analog conversion is an important interface process in many application. An example is a voice signal that has been digitized for processing or transmission and must be charged into an approximation of the originated signal to ultimately drive a speaker. In real time applications, we need to use physical quantities. In order to work with then it is required to connect analog signal to digital and vice versa. Digital signals are easy to be processed. Once digital data have been processed by DSP, they are converted to analog form using digital to analog converter. Types of DA converters are

BINARY-WEIGHTED INPUT D/A CONVERTER

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The one method of D/A conversion uses a resistor net work with value that refers the binary weight of the i/p but if the digital code. In fig the switch symbol represents the transistor. The op-amp provides high impedance load to the resister net work and at inverting i\p look like virtual ground so that the o/p is proportional to the current through the feedback resister Rf. Almost all load impedance o/p of the op-amp. The inverting/ i/p is approximately at OV. The lowest value of resistor (R) corresponds to the highest binary weighted input (23). Each of the other resistors is a multiple of R, 2R,4R and 8R corresponding to the binary weights 23,22, and 21 respectively. One of the disadvantages of this type of D/A converter to the number different resister values.

FIGURE 3.6 It was network of resistance values that represent binary weights of input bits of digital code. Each input will have current or have no current depending on input voltage level. If input=0, current is zero. If input is high, amount of current depends on input resistor value. Value of input resistors are inversely proportional to binary weights of input bit, lowest value R corresponds to highest binary weighted input 32, others are multiples of this.

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There is practically no current into operational amplifiers inverting input. So all the inputs, sum together to grow through Rf. Since inverting input is at zero ( virtual ground) the drop across Rf is equal to output voltage. V out = I f R f Therefore, output voltage is directly proportional to sum of binary weights because sum of input current is through Rf. It is difficult to achieve different resistance values. Mode equals 2R. Thus, there is equal division of current at each node. As a result, current is weighted as its distance from operational amplifier. The current in the resistor reduces as we move away from operational amplifier. R-2R Ladder D/A converter Another method of D/A converter is the R/2 . It over comes one of the problem in the previous type is that it requires only 2 resistor values. Again, the switch symbols represent transistor switch. Assume that the D3 switch is connected to 5V and the others to ground. This represents analysis will show you that the reduce it equivalent from these essentially. Thus all of the current through Rf and o/p ratio 5v When D1 i/p is connected to +5v and the others to ground. Again there is looking from Rs, we set 1.25v is series with R. This results in a current through Rf of I=1.25v/r which gives an o/p voltage of -1.25v. When Do is connected to 5v and other i/p to ground there from R5 gives an equivalent of 0.025v is series with R. The resulting current through Rf: is I=0.025 v/2r which gives an o/p voltage of -0.025 v. 0.625v Each successively lower weighted i/p produces an o/p voltage that is halved to that the o/p voltage. Is proportional to the binary weighted of the i/p bits.

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FIGURE 3.7 Number of data input decides resolution of DAC If n is the number of data inputs Number of level =2n Current output is converted into in to voltage using a current to voltage converter I out = I ref (D7/2+ D6/4+.Do/256) D7-MSB Do-LSB If=input current Vo=R8 I ref (D+ + D6 +.Do 2 4 256

ADC 0804 chip :-Successive Approximation type2)+5V power supply3)Resolution of 8 bits -conversion time is 100 MS -symbol indicates tri state o/p

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PIN DESCRIPTION

FIGURE 3.8 CS (Chip Select) :- To access 804 ADC, this pin must be low RD (Read) :- RD is used to get the converted data out of the ADC 804 chip. When CS=0 and if a H to L pulse on RD is applied, digital o/p will occur at Do-D7 pins. WR (Write/Start conversion) If CS=0. When WR makes a L to H transition, the ADC 804 start converting the analog i/p. Time taken for conversion will varies depending on CLK IN and CLK R values.

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CLK IN and CLK R:CLK IN is connected to external clock source. But ADC 804 has an internal clock generator. To use internal clock, CLK IN and CLKR pins are connected to a capacitor and a resistor as shown. Then f= 1 =606HZ 1.1 RC INTR (interrupt/End of conversion) :- It is a normally high pin and when the conversion is finished, it goes low. Vin (+) and Vin (-) :- Differential analog inputs. VCC :- +5v power supply used as reference voltage when the Vref/2 i/p is not connected. VREF/2 :- used for reference voltage. The voltage applied at this point determines the step size of ADC (i.e. the smallest change that can be done by an ADC) VREF/2 (V) N.C 2 1.5 1.28 0.5 v in (V) 0 to 5 0 to 4 0 to 3 0 to 2.56 0 to 1 Step size (mv) 5/256 =19.53 4/25 =15.62 3/256 =11.71 2.56/256 =10 1/256 =3.90

VCC=5V: when Vref/2 is not corrected is measured at 2.5v=Vcc/2. (Do-D7):Data o/p :- o/p an tri-state buffered. A GND and DGND :- Ground pins providing ground for both analog and digital signals. Two ground pins is to isolate the analog Vin signal from transient voltage caused by digital switching. WORKING 1. male CS=0 and send a L to H pulse to pin WR to start conversion. 2. Keep monitoring the INTR pin. If INTR is low the conversion is finished. 3. After INTR=0: make CS=0 and send a H to L pulse to the RD pin to get the data out of the ADC 804.

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FIGURE 3.9 Figure shows the interfacing of ADC 804 with 89C51 Mc. Since the frequency of MC is too high, we use D flip flops to divide the frequency. One f/f divide the frequency by two, if we connect its Q to D i/p. Program :MOV P1, # FFH BACK : CLR P3.5 CLR 3.7 SET B P3.5 HERE : JB CLR P3.4, HERE P3.6 : : : : : : : : : Make P1 i/p

Clear write Select CS low L to H pulse for start conversion Wait for end of conversion Enable RD Read data Display the data Rd=1 for next round

MOV A, P1 A CALL DISPLAY SETB P3.6 SJMP BACK. ADC DESCRIPTION

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Analog to digital interface to the microcontroller can be established by two methods 1. Parallel interface 2. Serial interface In order to process analog inputs 89C51 is interfaced with an analog to digital converter. Model ADC 0808. The analog to digital converter translates the frequency and amplitude of the signal into the digital data. There are two parameter to be considered 1. Resolution 2. MAX frequency Resolution ADC converts the analog signal to the maximum of 5v in to 8 bit digital information then resolution becomes 5v/255=0.0196v. 8 bit is equal to 0-255 counts. Each bit corresponds to 0.0196v. Suppose 16 bit ADC is used then 5v/65356=0.762uv. As the no of bit inversion increases the resolution also increases. We have 8 bit 16 bit 24 bit ADC in the market. Depends up on the resolution requirement the designer can select the ADC. Also the frequency of operation to be considered by the designer.

Reference Voltage The analog input voltage is compared with the reference voltage. Before it converts into the digital value. The analog input is max 5v then the reference voltage also to be selected max 5v. Depends up in the analog voltage input the reference voltage is to be selected to get max resolution. Also the reference voltage should be very stable since the conversion is depends on entirely by the reference voltage. Functional description ADC 0808 is a 8 channel analog to digital converter. The channel is selected by address selection inputs. ADC 0808/0809 with 8 analog channels ADC 0804 has only one analog input, this ADC 0808/0809 has 8 analog inputs. The ADC 0808/809 chip allows us to monitor up to 8 different analog inputs using only a single chip. The ADC 0808/0809 has an 8 bit data output just like ADC 0804. The 8 analog input channels are multiplexed and selected using three address pins A, B & C

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In ADC 0808/0809. Vref (+) & Vref (-) set the reference voltage Vref (-) =GND Vref(+)=5v step size =5/256=19.56mv

Vref(-)=GND Vref(+)=2.56v step size =2.56/256=10mv Use A,B,C address to select INO-INT and activate ALE to latch in the address SC-start of conversion (WR) EOC-end of conversion INTR OE-output enable (READ)-RD C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 selected Analog Channel INO INI IN2 IN3 IN4 IN5 IN6 IN7

Steps to program the ADC 0808/0809 1) 2) 3) 4) Select an analog channel by providing bits to A, B, C and address according above table Activate ALE (address latch enable)pin. It needs an L to H pulse to latch in the address Activate SC (start of conversion) by an L to H pulse to indicate conversion. Monitor EOC (end of conversion) to see whether conversion is finished. H to L o/p indicates that the data is converted and is ready to be picked up. If do not use EOC, we can read the converted digital data buffer a brief time delay. The delay size depends on the speed of the external clock we connect to the CLK pin. The EOC is the same as the INTR pin in other ADC chip. 5) Activate OE (o/p enable) to read data out of the ADC chip. An L to H pulse to the OE pin will bring digital data out of the chip. OE is same as the RD pin in other ADC chip. 6) Select an analog channel by providing bits to A, B, C and address according above table

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7) Activate ALE (address latch enable)pin. It needs an L to H pulse to latch in the address 8) Activate SC (start of conversion) by an L to H pulse to indicate conversion. 9) Monitor EOC (end of conversion) to see whether conversion is finished. H to L o/p indicates that the data is converted and is ready to be picked up. If do not use EOC, we can read the converted digital data buffer a brief time delay. The delay size depends on the speed of the external clock we connect to the CLK pin. The EOC is the same as the INTR pin in other ADC chip. 10) Activate OE (o/p enable) to read data out of the ADC chip. An L to H pulse to the OE pin will bring digital data out of the chip. OE is same as the RD pin in other ADC chip. ADC 0808/0809 there is no self-clocking and clock must be provided from an external source of the CLK pin. The speed of conversion depends on the frequency of the clock connected to the CLK pin; it cannot be faster than 100/us. ADC 808/809 Chip with 8 analog Channels

figure 3.10
Pin Number Description

1 2 3

IN3 - Analog Input 3 IN4 - Analog Input 4 IN5 - Analog Input 5

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4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

IN6 - Analog Input 6 IN7 - Analog Input 7 START - Start Conversion EOC - End Of Conversion 2(-5) - Tri-State Output Bit 5 OUT EN - Output Enable CLK - Clock Vcc - Positive Supply Vref+ - Positive Voltage Reference Input GND - Ground 2(-7) - Tri-State Output Bit 7 2(-6) - Tri-State Output Bit 6 Vref- - Voltage Reference Negative Input 2(-8) - Tri-State Output Bit 8 2(-4) - Tri-State Output Bit 4 2(-3) - Tri-State Output Bit 3 2(-2) - Tri-State Output Bit 2 2(-1) - Tri-State Output Bit 1 ALE - Address Latch Enable

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23 24 25 26 27 28

ADD C - Address Input C ADD B - Address Input B ADD A - Address Input A IN0 - Analog Input 0 IN1 - Analog Input 1 IN2 - Analog Input 2

-Here eight different i/p can be monitored using single chip. -Eight analog i/p channels are multiplexed and selected according to the starts of A,B and C. (Address pins). -Here V ref (+) and V ref (-) set the reference voltage and step size. -ALE pin latch the address constitute by A,B and C -SC pin is start conversion equivalent to WR in 804. -EOC End of conversion = INTR in 804 -DE o/p Enable = RD in 804. END of conversion 0=EOC-LOW when conversion is in process 1=EOC-high conversion is completed

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Program ALE BIT P2.4

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OE SC EOC ADDR-A ADDR-B ADDR-C MYDATA ORG MOV SETB CLR CLR CLR BACK : CLR CLR SETB ACALL SETB ACALL SETB ACALL CLR CLE

BIT BIT BIT BIT BIT BIT EQU 0000H P1,#OFFH EOC ALE SC OE

P2.5 P2.6 P2.7 P2.0 P2.1 P2.2 P1

ADDR-C ADDR-B ADDR-A DELAY ALE DELAY SC DELAY ALE SC

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H1:JB EOC, H1 HERE 2: JNB SETB ACALL MOV A, CLR A CALL DISPLAY SJMP BACK. EOC, HERE2 OE DELAY MY DATA OE

. DAC 0808 (MC 1408 DAC) -R-2R method is used -8 bit DAC. So provide 256 voltage levels -This convert digital i/p s into current and by connecting a resistor to the I O pin, we convert this into voltage. I O = I ref (D7/2+D6/4+D5/8+D4/16+D8/32+D1/64+D1/128+D0/256) D0-LSB and D7-MSB: I ref is the current applied to the ref. pin. Generally set to 2 mA.

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FIGURE 3.11 DAC PIN DIAGRAM In real life, the i/p resistance of load where it is connected will also affect the o/p Voltage. For this reason, I ref current o/p is isolated by connecting it to an op-amp with Rf=5k for feedback. E.g.-If R=5k : I ref = 2ma : i/p =10011001 (=99H) =153 Io=2ma (153/255) = 1.195ma : Vo=1.195mx5k=5.975V. Figure of the DAC0808 datasheet is a good place to start your design. The pins are labeled A1 through A8, but note that A1 is the Most Significant Bit, and A8 is the Least Significant Bit (the opposite of the normal convention). Ground the two least significant bits. The D/A converter has an output current, instead of an output voltage. The output pin should stay at about 0 volts. The op-amp on the "Typical Application" on the datasheet converts the current to a voltage. How does it do this? The output current from pin 4 ranges between 0 (when the inputs are all 0) to Imax*255/256 when all the inputs are 1. The current, Imax, is determined by the current into pin 14 (which is at 0 volts). Note: Since we are using 8 bits, the maximum value is Imax*255/256. You'll need to modify the circuit given in the datasheet to get a full scale range of 0 to 5 volts. Again, our output will be just under 5 volts. The output of the D/A converter takes some time to settle. You may need to take this in consideration when planning the timing of the A/D conversion in later sections of this lab. Check the DAC0808 datasheet for specs. The code below shows an easy way to send 8 bits to the output of the micro controller. You should probably test your code without the D/A converter separately to ensure that the microcontroller is behaving as you expect.

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Figure 3.12. Typical Application DAC0808

Where, Rf = Feedback Resistor of Current to Voltage Converter circuit

Temperature Sensors Transducer (sensor) convert (physical datas) temperature, light intensity, flow, speed etc to electrical signals. Temperature conversion is done with the help of transducer called thermister It is by varying resistance. Widely used temperature sensors are LM 34 and LM 35. LM 34 o/p voltage linearly proportional to of temperature. Internally calibrated. LM 34 A, LM34, LM34CA, LM34C, LM34D etc. o/p voltage varies IOMV/F. LM 35- o/p voltage linearly proportional to C0 (Celsius) temperature. o/p voltage varies 10mv/C0

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Interfacing of LM 35 or 34 to/8051

FIGURE 3.13 (INTERFACE PROGRAM SAME AS ADC) -Transducer o/p is conditioned to fed to the ADC.

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-Conditioning may be current to voltage conversion amplification etc. -Here thermostat change resistance according to temperature. Thus o/p voltage will vary. -Since LM 35 or 34 produces 10mv for every degree of temperature charge, step size of ADC must be 10 mv. -So ADC 0809 produce of a full scale o/p of 2560mv=2.56v for that we need to set Vref/2=1.28v

FIGURE 3.14 We use LM 336-2.5 zero diode to fix the voltage across the 10k pot at 2.5 volts.
temp C 0 1 2 10 30 Vin (mv) 0 10 20 100 300 Vout 0000 0000 0000 0001 0000 0010 0000 1010 0001 1110

Programming similar to that of ADC

Program in C / *program for analog to digital converter*/ /*using parallel AD 0808*/ /*include < std io-h >/*header tile initialization*/ # include <reg 51H >

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S bit ALE PO5/* P0.5 for address latch enable line*/ S bit SOC Po4/*P0-4 start conversion*/ S bit CLK Po7/* Po.7 clock input*/ S bit OE P0.6/*P0.6 output enable*/ Void delay (VOID),/*delay function declaration*/ 1nt c ;/* variable declaration for clock count*/ Main ( )

While (1) [Address=0x01 ; / *select channel */ P0=Address ; P1=0Xff; /*port 1 declared as in put port*/ ALE=0 ; /Address LATCH=1/ SOC=0/* Start conversion */ OE=0 / * output enable=0 * L=0 ; /* i=0 */ While (i<=1000)/ *counter clock pulse*/ Ci=i+1; CLK-1; / *clock high*/ Delay ( );

CLK=0;/*clock Low*/ Delay ( );

If (i==5) { ALE=1 ; SOC=1;} /* ALE=1 SOC=1 */ Else { ALE=0 ; SOC=0 ;} /* ALE=0 SOC=0 */

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OE=1; / * output enable=1 P2=P1 / Read P1 data and transfer to P2*/ Void delay ( {Int 1 ; For (i=1 ;L <=2; C++) ; Assembly program Assembly Language Program ALE OE SC EOC BIT BIT BIT BIT P0.5 P0.6 P04 P3.2 P0.0 P0.1 P0.2 )

ADD A BIT B BIT C BIT

MY DATA EQU P1 ORG 0000 H MOV P1 # OFFH SETB EOC CLR ALE CLR SC CLR OE BACK CLR CLR ADD ADD C B MOV A, MY DATA CLR OE JB EOC HI H1 JB/EOC H1 H2 JNB/EOC H2 SETB OE A CALL DELAY

DEEPAK . P AP/SNGCE

CLR

ADD

A CALL DELAY SJMB BACK DELAY ROOTINE

A CALL DELAY SETB ALE

A CALL DELAY SETB SC

A CALL DELAY CLR CLR ALE SC

Digital to Analog convertor Interface to 89C51 In several control application the digital system is required to produce analog voltage 05v or current output 5-20ma in the process or image process application. The digital output form the microcontroller is to be converted in to the analog voltage by using DAC.

FIGURE The full current output form DAC v2.5v 5k 2.5v reference voltage connected to v ref through a resistor 5k the current output max =2.5v x 255 = .498ma 5k 256 The output current is converted by the operational Amplifier in to the voltage. 0.498ma x 5k=2.49v

DEEPAK . P AP/SNGCE

To obtain 0 to 2.49v the digital output B1-B8 0-255 is to be outputted to DAC. Write a DAC interface program in C to generate saw tooth wave form /*program to generate saw tooth wave for in using DAC*/ /*Analog converter /*using DAC 0800 */ Main ( ) */

{While (1) I=0x00 ; {Po=I; I++; Delay ( ); )

}Void delay ( {int k;

For (K=1 ; K<=2;K++) ; TRIAC Driving by Microcontroller

FIGURE Triac is an in expensive solution for controlling the power delivered to load. Triac has three terminal MT1,MT2,Gate. During each half cycle of ac gate pulse is required to switch on Triac. For isolation between microcontroller and power device Triac is required MOC 3031 is an optically isolated zero crossing Triac driver. Triac MAC 212 A10 can handle up to 12 A rms current with a peak voltage of 800V.

DEEPAK . P AP/SNGCE

Temperature sensors and interface to Microcontroller Transducer convert the physical value of the parameter like, temperature, light intensity, speed, flow into a electrical signals. The temperature sensor LM34,LM35 are used in the operating range of-55 C to 150 c to measure the temperature. In LM34 the voltage is linearly proportional to the temperature and varies with a IF temperature increase 10mv/OF Lm35 output voltage linearly proportional to the temperature measured in 0C. The output will be 10mv/0C LM35 Specification Linear+10.0mv/oc Scale Range-55c to 150 0c Accuracy=0.5 0c Operating voltage 4 to 30v Low heating 0.08 0c Non linearity =+1/4 0c Low impedance output=0.10hms for/ma load

Interfacing LM35 to 89C51

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FIGURE Since 89C51 or 8051 do not have build in ADC the external ADC is to be used. But latest microcontroller f Intel, Atmel, Microchip, national, all have multi channel ADC in side the microcontroller. LM35 is operated in 5v supply The signal conditioning unit amplifier again to be decided for ADC input 0-5V Range 1= 10mv 0-127.5 0c 127.5=1275mv =1.275 V Select amplifier the gain =5v =3.921 =3.92 1.275 Now each incremental value of ADC =0.5 0C If you select 8 bit ADC; then ADC resolution of 1 bit =0.5 0C
ADC BIT 00000000 00000001 00000010 11111111 Temp 0c 0.5 0c 10c 127.5c

V ref =5v V input INO Analog input 0-5v Resolution 0.5 c /1 bit Module-4 2 Wire Serial E2 PROM 24CO4 Sl No 1 2 3 Important Features High reliability Two Wire serial interface. I2C bus compatible

DEEPAK . P AP/SNGCE

4 5 6 7 8 9 10 11

Supply voltage 3V to 5.5 V I million write cycle 100 years data retention 512x8 byte organization 5m sec write cycle 8 pin, bidirectional data transfer device Write protection pin for hard more data protection

Pin Description

A0-A2 SCL SDA WP GND,VCC

ADDRESS Serial clock Serial DATA/ADS Write protect Power supply lines

Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device Used to synchronize all data in and out of the memory. Normally a resistor from SCL is connected to VCC act as pull up Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-O Red with any number of other open-drain or open collector devices. It is bidirectional used to transfer data in and out of memory.

DEEPAK . P AP/SNGCE

Write Protect (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table. GND, VCC Power supply pins. The device code of E2 PROM is 1010. I,e while connecting external devices to MC, it detects the device using this code. E2 PROM 24CO4 consist of 4K memory which is arranged as 32 pages of 16 byte each. Device/Page Address (A2, A1, A0) A2 and A1 inputs for hardware addressing. In 24CO4 A0 is with no connection. With A2 and A1, we can address four devices at a time. So while interfacing this with a MC through an I2C bus we can address four devices of 4K memory. I 2C bus can be use either 7 bit (128) or 10 bit (1024) address. If the 8th bit 0 --------- Master writing to slave 8th bit 1 ---------- Master reading to from slave

DEEPAK . P AP/SNGCE

More Features 5-16 byte page address 6-Write protection 7-One million write cy 8-100 years data rate 9-5 m sec write cycle Data transfer will be start with MSB Data 0 or 1 placed in SDA line-when SCL=0 SCL is pulsed high and then low for data transfer ACK is send back after receiving the 8 bit by the receiver if it can further receive data it will make ACK line low will be placed by slave ACK is will be high if the slave can not receive the further data Then master send stop bit which indicates of termination of data transfer.

Low-Voltage and Standard-Voltage Operation 5.0 (VCC = 4.5V to 5.5V) 2.7 (VCC = 2.7V to 5.5V) 2.5 (VCC = 2.5V to 5.5V) 1.8 (VCC = 1.8V to 5.5V) Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) 2-Wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility

DEEPAK . P AP/SNGCE

Write Protect Pin for Hardware Data Protection 8-Byte Page (1K, 2K), 16-Byte Page (4K, 8K, 16K) Write Modes Partial Page Writes Are Allowed Self-Timed Write Cycle (10 ms max) High Reliability Endurance: 1 Million Write Cycles Data Retention: 100 Years ESD Protection: >3000V Automotive Grade and Extended Temperature Devices Available 8-Pin and 14-Pin JEDEC SOIC, 8-Pin PDIP, 8-Pin MSOP, and 8-Pin TSSOP Packages

Interfacing Here a maximum of 4 nos E2PROM devices can share the same bus as shown. But each device must have its address i/p s hardware to unique address. For device zero, A2=A1=0 (GND) ; for device 1 A2=0 (GND), A1=I (Vcc) and so on. Here the bidirectional data transfer between a master and several slaves done through the common 2 wire bus. Master initiates the data transfer by generating a start condition on bus. For this master transmits a byte; (containing the device code, device address, page no: and read write bit) to the bus; starting from MSB. 1 0 1 0 A2 A1 Po R/W

Fixed portion

Programmable portion

DEEPAK . P AP/SNGCE

Sl No 1 2 3 4 5 6

Bits A2,A1 Po R/W Fixed portion Start End

Function device address page no 0 = read ; 1= write device code H-L pulse L-H pulse

After the 8th bit is transmitted, the master releases the data line and generates the 9th CLK bit. If a device has recognized the transmitted device address, it will respond to the 9th clock by sending an acknowledge signal. After getting the acknowledge signal the data transfer begins. The master can stop the data transfer at any time by generating a stop condition. [L to H SDA with SCL high]

DEEPAK . P AP/SNGCE

SCL P1. 2 Up to 4th stage SDA P1. 3 89C51 SCL SDA WP SCL SDA WP SCL SDA WP

Device 1

Device 2

Device 3

Figure 3 Wire serial EE PROM 93C 46 Sl No 1 2 3 4 5 6 Features Low power CMOS technology 64x16 bit organization Automatic erase before write cycle Self timed write/erase cycle 3 wire serial interface One million write cycle

DEEPAK . P AP/SNGCE

7 8 9 10 11

2MHZ clock rate 40 years of data retention Low volt and standard volt operations 8 pin package Programming cycle -2msec

Pin Description

CS SK 93c46 DI D0

VCC NC ORG GND

Figure Pins:CS chip select SK serial data CLK (shift clock) DI serial data i/p DO serial data o/p VCC;GND power supply. -It provides 1024 bits of EEPROM organized as 64 words of 16 bits each. Pin description

DEEPAK . P AP/SNGCE

Chip select is the enable the chip. A high level selects the chip Serial clock is the synchronize the data transfer between master and slave. Clock will be dontcare either the CS is low or the start bit is not sent Data in is used to clock in a start bit, OP code, address and data synchronously with CLK. Data out is used in read mode. It also provides ready/busy status information during erase andwrite cycles. At 93C 46A is accessed via a simple and versatile 3 wire serial commn. Interface deviceoperation is controlled by 7 instructions issued by the master. A valid instruction starts with arising edge of CS and consists of a start bit (1) followed by desired memory address.

Instruction Start bit

op code address

Address

Comments

Read

1 0

A5 A4 A3 A2 A1 Read data stored in specified A0 A5 A4 A3 A2 A1 A0 A5 A4 A3 A2 A1 A0 0 1 1 x x x x 0 0 x x x x Write memory Erase (A5-A0) Write enable

Write Erase EWEN

1 1 1 1

0 1 1 0 0 1

all program instr: disables

EDIS ERAL WRAL 1 1 0 0 1 0 x x x x Erase all memory Program entire memory

0 0

0 1 x x x x

DEEPAK . P AP/SNGCE

VCC

GN Address decoder

Memory array 64*16

Data register DI O/P buffer Mode decode logic

D0

CS

SK

Clock generato r Figure

R2 232 Standards Features

DEEPAK . P AP/SNGCE

RS

Recommended standard

-RS 232 is the most widely used serial I/o standard -Input and output levels are not TTL compatible -logic 1= -3 to-25V ; logic 0= +3 V to +25V ; -3 to +3 undefined -Line drivers like max 232 issued to convert TTL voltage levels to RS 232 levels. -Standard set by EIA [Electronics industries Association]. First they produce a 25 pin connector named DB 25 for RS 232 cable. DB-25P DB-25S plug (male) connector Socket (female) connector.

Since all the pins are not used in PC cables IBM introduced the DB-9 version, which used 9 pins only

Data communication Classification:Data comm. Equipments are classified as 1. Data Terminal equipment (DTE) and 2. Data common equipment (DCE). DTE refers to terminals and computers that send and receive data, while DCE refers to communications equipment that are responsible for the data transfer. RS 232 Hand Shaking Signals:For fast and reliable data transmission, it must be coordinated. [eg: in case of printer, there is no room for data, there must be a way to inform the sender to stop sending data]. Many of pins of the RS -232 connector are used for handshaking signals.

DEEPAK . P AP/SNGCE

DB-9; 9-pin connector 1 5

6 9 Figure DB 9 Signals:1 2 3 4 5 6 7 8 9 Description Data carrier detect (DCD) Received Data (RxD) Transmitted Data (TxD) Data Terminal ready (DTR) Signal Ground (GND) / (SG) Data set Ready (DSR) Request to send (RTS) Clear to send (CTS) Ring indicator (RI)

DEEPAK . P AP/SNGCE

Hand shaking Signals:1. DTR :- When one terminal (DTE) (say PC) terms on, it sends out signals DTR to indicate that it is ready for communication. 2. DSR :- When DCE is turned on (Say Modern) and has gone through the self-test, it asserts DSR to indicate that it is ready to communication. (modem PC). 3. RTS :- When DTE (PC) has a byte to transmit, it asserts RTS to signal the modem that it has a byte of data to transmit. Active low. (PC-modem)

4. CTS :- When DCE (modem) has a room for storing data it sends out signals CTS to DTE. (modem PC) 5. DCD :- The modem asserts signal DCD to inform DTE (PC) that a valid carrier has been detected and that contact between it and the other modem is established 6. RI :- DCE (modem) sends this to DTE (PC) indicates that the telephone is ringing (busy). This is the least of less used handshaking signal. The PC and modem communication. Can be summarized as follows: - When PC and modem are alive, they send signals DTR and DSR resp. while PC wants to send data it asserts RTS and in response; if the modem is ready ; it sends back CTS. The simplest connection between a PC and MC requires a minimum of three pins ie TxD, RxD and GND.

DEEPAK . P AP/SNGCE

MAX 232:RS 232 is not compatible with todays MPS we need a line driver to convert RS 232 levels in to TTL voltage level and vice versa, for that we are using MAX 232. It uses a +5v power source, which is same for 89C51. It consists of two sets of line drivers for transferring and receiving data. In many application only one is used. VCC

C1

1 3 4

161 22 6 6

C3

C2 T1 in 11

C4

5 14 12 7 RS 232 SIDE 9 T1 out R1 out

R1 in 13 10 8

TTL SIDE

Figure

It requires 4 capacitors for proper working. (Commonly 22MF). 89C51 TxD Rx xD T1 in ; R1 out ; T1 out Rin in RxD. TxD. RS 232

DEEPAK . P AP/SNGCE

11 11

14

D B 9

8 TXD 9c 5 1 RXD

10 12

M A X 2 3

13

DB-9 connected to 89c51

RS-232C is not compatible with MPs we need to have compatible voltage source device MAX 232 MAX 232 interface with the MP since it is compatible with TTL MAX 232 converts all RS 232 voltage levels to TTL compatible voltage MAX 232 line drives uses a 5V power supply and it is compatible with all MC MAX 232 has two line drives (Two channel

TxD = T1xT2 RxD =R1xR2 LOW VOLTAGE DIFFERENTIAL SIGNALING [LVDS]: A generic interface standard for high speed data transmission. Low noise, low power, low amplitude method EIA-644 [RS-644] standard specifies the physical layer as an electronic interface. A multipurpose interface standard-Transmission media may copper cables, or PCB traces Data rate > 400 mbps.

DEEPAK . P AP/SNGCE

Comparison with RS 422 with RS-644 Features Diff. O/P voltage Receiver I/P threshold Data rate Power distance RS 422 +2-5v +200mv <30mbps very less 1000M RS 644 +250-450mv +100mv >400 Mbps very less 10M

LVDS differs from normal I/O: Natural I/O works with 5v as high, and 0 volt as low. When we use differential, a third option is there with which to encode to increase data transfer rate, is possible. Low voltage means Std. 5v replaced by 3.3v or 1.5v. Uses a dual wire twisted running 1800 out of phase. This enables noise to travel at the same level which in can gets filtered easily. Data storage is distinguished only by +ve and ve voltage values. Not affected by wire length.

LVDS Physical Layer:-

DEEPAK . P AP/SNGCE

Current steering driver Figure

Differential receiver

The differential driver produces odd mode- transmission ie equal and opposite current flows is two lines. Since the current are equal and opposite and wires are closely arranged, electromagnetic interference (EMI) is low. The differential receiver is a Li-Z device that detects differential signals as low as 20mv and then amplifier them into standard logic levels. Another feature is the failsafe function, which prevents output oscillations when the I/P pins are floating. Advantages:1. 2. 3. 4. 5. Ability to reject common mode noise. Reduced amount of noise emission. Reduce wires b/w Rx and Tx Low power consumption Space at power saving.

PARALLEL PRINTER PORT: IBM-PCS parallel printer port has a total of 12 digital output and 5 digital input accessed via 3 consecutive 8 bit ports. The lines in DB 25 connector are divided into 3 as-

DEEPAK . P AP/SNGCE

1. Data lines (data bus) - 8 No: (O/P) 2. Control lines - 4 NO: (O/P) 3. Status lines - 5 No: (I/P) The registers found in standard parallel ports are 1. Data resister 2. Control resister 3. Status resister. Each resister is connected to corresponding data lines. Whatever we write to these registers, will appear in corresponding lines and I/P to lines can be read from registers. -8 O/P pins accessed via data port. -4 O/P pins (3 inverted) accessed via control port -5 I/P pins (1 inverted) accessed via status port. -Remaining 8 pins are grounded. (18-25) Data lines connected to pin no:2 to 9 Status lines S3 S4 S5 S6 S7* Status lines Error - Selected in - paper end - Acknowledge - Busy Pin no: 15 13 12 10 11 Control lines C0* Strobe C1* Auto feed C2 Initialize C3* Select Pin No: 1 14 16 17 -

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Signal name Strobe Data bit 0 Data bit 7 Acknowledge Busy Paper end Select in Auto feed Error Initialize Select Ground

Bit C0* D0 D7 S6 S7* S5 S4 C1* S3 C2 C3*

Pin 1 2 9 10 11 12 13 14 15 16 17 (18-25)

I/O. O/P O/P O/P I/P I/P I/P I/P O/P I/P O/P O/P

DEEPAK . P AP/SNGCE

D7

D6

D5

D4

D3

D2

D1

D0

S7

S6

S5

S4

S3

C3

C2

C1

Co

Figure

DEEPAK . P AP/SNGCE

Interface Diagram

P0.0-P0.7 D0-D7 P1.0 P1.1 P1.2 P1..3 P1.4 P1.5 P1.6 P1.7 P2.0 GND C0 S6 S7 S5 S4 C1 S3 C2 C3 18-25 IBM

89c51

GND

Serial communication The data transfer can be made in two ways 1) Parallel Communication 2) Serial Communication Parallel communication all eight bit data is transferred simultaneous through 8 data lines. In addition hand snake signals are required to communicate. The parallel communication is employed only in short distance communication since the number of wire is more. Serial communication can be carried out by 2 wires or 3 wires. Due to this the serial communications become popular for data transfer for long distance. Parallel Communication Data transfer width min 8 bit and it can go up to 32 bit width depends up in the data width. Control lines are required for transfer of data Speed will be high since all data transfer occurs instantly

DEEPAK . P AP/SNGCE

Short distance only applicable due to no of wires PC to printer and hard disks

Serial Communication Only one transmits line all data bits are to be transferred through this line. Data transfer is slower due to 1 bit at a time. Cost will be less due to no of wire reduction in it can be transmitted 50-100 feet of distance Control lines may be required Serial Communication (Program) Glow an array of LED connected to receiver according to the combination of switches connected to transmitter [Display the transmitted data using LED array] Serial Txn ORG 0000H MOV TMOD, # 20H; MOV TL, #6 ; 4800 Baud rate Serial mode 1 (where an 8 bit data is framed with starts stop bits) TIMER 1, MODE 2

MOV THI, # 6

MOV SCON, # 50H ; SET B AGAIN : MOV HERE : TRI

SBUF , # A JNB T1 , HERE Check Interrupt bit

CLR T1 SJMP AGAIN END Serial Reception ORG 0000H MOV TMOD , # 20H

DEEPAK . P AP/SNGCE

MOV THI, # -6 MOV SCON, # 50H SETB TRI AGAIN: JNB RI, AGAIN MOV A, SBUF CLR RI SJMP AGAIN END. Methods of Communication Two methods of serial communication is available. 1) Synchronous communication 2) Asynchronous communication Synchronous communication The data is transmitted or received by one clock rate and one dock is used for both operation Transmit takes place during falling edge of the clock Receiving takes place during raising edge of the clock SPI, I2C are typical example of synchronous communication High speed transmission is possible up to 1 M bit/SCC MSB in transmitted first For example the data 61H is transmitted by synchronous method with the following wave form The raising edge shift the data from one device to 2nd device and falling edge shift to data from 2nd device to first device. Normally there will be finite delay of transmit of data from 1st to II nd similarly there will be a finite delay from IInd to 1st device. The delay is requires to stabilize the finite data in the transmit line. In this mode MSB transmitted first and LSB last. next

DEEPAK . P AP/SNGCE

Figure Asynchronous communication Asynchronous communication (USART) depends up on the CLK generated in side the chip. The transmit data clock and received clock will be the same clock it is not out putted to output. The clock frequency or baud rates are same but in the same clock it is not transmitted or received by sensing edges. RS 232 is the example for asynchronous communication.

Figure The data transmitted with start bit LSB MSB and stop bit. It is normally used in PC & modem interface and data transfer. LSB transmitted first and MSB is last. I 2C Interface There are three wires 1) SDA Serial DATA/ADS 2) SCL Serial Clock line 3) GND Ground

DEEPAK . P AP/SNGCE

I2C bus VCC Device 1 Device 2 Device 3

SCL SD GND

SDA and SCL are open drain output. SCL is the clock used to transfer the data between devices. And the frequency of SCL determines the speed of the data transfer. Normally 400 KHZ frequency is used for data transfer. Since SDA / SCL open drain the pull up resister to be connected to the 5V supply. Normally the device which generates CLK is called as master and other devices are slave. At a time any one device only be master all other devices are slave I 2 C normally used for flash memory read/write in the microcontroller. I 2 C Protocol SDA SDA SCL SCL High high Start sequence Stop sequence

When ever SDA line goes from high to low and SCL line is high the start sequence is beginning of data transfer cycle Whenever SDA line goes from low to high and SCL line is high. The stop sequence ie end of the data transfer cycle. 8 Bit= 0 8 Bit=1 ACK=0 ACK=1 Master writes slave Master reads slave Received 8 bit data by slave further data can be received Received 8 bit data no more data

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I 2 C Write sequence Master sends start sequence Slave device expect address Master Send slave address with write bit 8 =0 Slave check the 7 bit address (correct slave) Will wait for data, other slave continue for its operation? Master will now send internal address of the slave from which the data to be stored Master will continue to send data to slave Slave will receive all data and store it in its RAM and automatically slave increment the internal ADDRESS If ACK=1 the slave can not further receive data, now master initiate stop sequence I 2C read sequence Master sends start sequence Slave expects address from master Master sends address with 8 bit =0 Slave check address and if it matches, slave will wait for receive data, other slaves do their own work Master send data with 8 bit =1 read data M<aster will send another start sequence. SP I interface communication In many application more than one Micro controllers are required for communicate to peripheral devices EP Rom, ADC, LED, MATRIX key board etc. one type of interface is called SPI interface with following features.

DEEPAK . P AP/SNGCE

MOSI

MOSI

SS Mas ter
MISO MISO

Slav e
GND

SCK

Figure

SCK

SS

Pin description SCK Clock output in the master mode, but it is the clock input in the slave mode. MOS I Master output slave input Data written by the master shift out from this pin are bit at C time. In the slave Microcontroller this pin is used for receive the data from the master controller. MISO Master input slave output Data written by the slave controller shift out from this pin one bit at a time. In the master controller the pin is used to receive the data from the slave microcontroller.

DEEPAK . P AP/SNGCE

Features Full duplex communication 3 wire synchronous data interface Master or slave operation 1.5 MHZ maximum speed LSB first or MSB first data transfer selection is possible End of transmission interrupts flag Protection for write collision Wake up from idle mode MOS I & MISO of master output & input are connected to slave MISO & MOSI and both clock is connected together.

Serial communication standard RS 232 RS 422 RS 485 comparison Descript Speed RS-232 C 20 K baud RS-422 A 10 M baud 40ft 100 K baud 4000f 4000 t B>A B<A + 7V RS-423 A 100K baud 30ft 1 K baud 4000ft 4000f +4V to +6V -4V to -6V + 12V RS 485 2.5 MB for 4000 H 4000 H +7V -7V +12V

Distance 50 feet Logic 0 3V to 25V Logic 1 -3V to -25V Receiver input voltage +15 V

BxA differential input to OP amp

DEEPAK . P AP/SNGCE

USB -Universal serial BUS -Support plug and play capacity -Uses serial data transmission -Supports 3 speed of operation Low = 12 m bit/SCC Full = 150m bits/SCC High = 430 m bits/SCC -Tree architecture -Depends upon processer architecture -High band width -No multiplexing

PCI -Peripheral component Inter connect Bus -supports plug and play capability -Not serial transmission -Operates with 33MHZ or 66MHZ clock

-No tree architecture -Independent of process architecture -Low band width 32/64 bit address/Data bus multiplexed to reduce the size

DEEPAK . P AP/SNGCE

Module 5

DS 1232 WATCH DOG TIMER :- (WDT) Watch dog are used to ensure that if a code operating on a microprocessor enters into an unanticipated state, then the processor will reset after some minimal amount of time elapses. [Simply speaking it will reset the processor when it is hanged]. Features:-Halts and restarts an out of control MP. -Holds MP in check during power transients -Automatically starts MP after power failure -Monitors push button for external override. -Eliminates the need for discrete components. Pin description :-

PBRST - Push button reset input TD TOL GND RST - Time delay set - Selects 5% or 10% VCC detect - Ground - Reset output (Active high)

DEEPAK . P AP/SNGCE

RST ST VCC

- Rest O/P (Active low-open drain) - Strobe input +5V power.

DS 1232 chip monitors three vital conditions for a MP (a) power supply (b) software execution and (c) External override. (a)( out of- tolerance condition occurs, an internal power fail signal is generated which forces reset to the active state. Reset signal will kept in active state for 250ms to allow the supply and processor to stabilize. (b) Push button reset control :- DS 1232 provides a pin for direct connection to a push button. This I/P requires an active low signal. When a low is connected to this pin, the RST and RST signals are generated after a short time delay. Watch dog timer operation forces RST and RST signals to active state when the ST pin not stimulated for a predetermined time period. The time period is set by the TD I/P. Delay is 150ms; when TD is connected to GND, 600ms with TD left un connected and 1.2 Sec with TD connected to VCC The ST signals are derived from MP address signals data signals, and/or control signals. If a H to L transition occurs on the ST prior to time out, WDT is reset and time out again. Ds 1302 Real Time Clock (RTC):-It counts seconds, minutes, hours, date, month, day of week, and year with Leap-year compensation up to 2100. -31x8 RAM for scratch pad date storage. -2.v to 5.5 full operation -Single byte or multiple byte data transfer. -simple 3-wire interface -TTL compatible -Operational temperature range -400C to 850C Pin Description :-

DEEPAK . P AP/SNGCE

Pin 1 :- VCC2 Primary power supply in dual supply configuration. Vcc1 is connected to a back up source to maintain the time and data in the absence of primary power. When VCC2 > Vcc, +0.2V, Vcc2 powers the DS 1302. When Vcc2<Vcc1 Vcc1 power the RTC. Pin 2,3 X1 and X2 :- connected to 32.768 KHZ quartz crystal (internal) It can also driven by an external oscillator. In this X1 pin is connected to external oscillator and X2 is floated. Pin 4 : GND -Ground Pin 5 : CE :- It must be asserted high during a read write. The functionality of the pin has not changed. Pin 6 : I/O :- The bidirectional data pin for the 3-wire interface. Pin 7 :- SCLK:- is used to synchronize data movement in the serial interface. Pin 8:- Vcc1:- Low power operation in single supply and battery-operated systems. (Secondary power supply)

DEEPAK . P AP/SNGCE

AT Keyboard IBM compatible keyboards are also known as AT keyboard or PS/2 keyboards. All modern PCS support this device they are the easiest to interface. PS/2 keyboard was originally an extension of the AT devices. At keyboard and PS/2 keyboards were very similar devices, but the PS/2 device used a smaller connector and supported a few additional features IBM AT keyboard (1984) 84-101 keys 5 pin DIN connector Bidirectional serial protocol Uses scan code set 2 8 Host to keyboard commands. IBM PS/2 keyboard (1987) comp labile with AT 84-101 keys 6 pin mini DIN-connector Bidirectional serial protocol Offers optioned scan code set 3 17 host to keyboard commands Modern PS/2 (AT) compatible lay boards

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Any no: of keys (Usually 101 or 104) 5 pin or 6 pin connector, adaptor usually included Bidirectional serial protocol Only scan code set 2 guaranteed Acknowledges all commands, may not act on all of them

General Description Keyboards consist of a large matrix of keys, all of which are monitored by an on-board processor (called the keyboard encoder). The specific processor varies from keyboard to keyboard; but they all basically do the same thing. Monitor which keys are being pressed/ released and send the appropriate data to the host. This processor takes care of all the debounce of keys and buffers the data in its 16 byte buffer. The mother board contains a keyboard controller that is in charge of decoding of all data received from the key board and informing yours software all common. Between the host and the keyboard uses an IBM protocol Scan Codes The keyboards processor spends most of its time scanning or monitoring, the matrix of keys. If it finds that any key is being pressed, released or held down, the keyboard well send a packet of information known as a scan code to your computer. There are two different types of scan codes make codes and break codes. A make code is sent when a key is pressed or held down. A break code is sent when a key is released every key is assigned its own unique make code and break codes so that host can determine exactly what happened to which key by looking at a single scan code. The set of make break codes for every key comprises a scan code set. There are three std keyboards default to set two We have to figure out what the scan codes are for each key. Theres no simple formula for calculating this. If you want to know what the make code or break code is for a specific key, youll have to look up in a table.

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Make Codes, Break Codes & Type matic Repeat Whenever a key is pressed, that keys make code is sent to the computer. There is no defined relation ship between a make code and an ASCII code [A make code only represents a key on a keyboard-It doesnt represent the character printed on that key]. Its up to the host to translate scan code to characters or commands. The most set two make codes are only one-byte wide, there is hand full of extended keys whose make codes are 2 or 4 bytes wide. These make codes can be identified by the fact that their first byte is EOh. When ever a key is released, a break code sent to the computer. Certain relationships do exist between make codes and break codes. Keys Set 2 Make code A 5 FIO Right Arrow G shift key+ g make code make cedi for Shift key (12h) Break code Fo, 12h make code for + g Fo, 34 IC 2E O9 Eo,74 (Set 2) Break code Fo,IC Fo, 2E Fo,09 Eo. Fo, 74

Scan code

Scan code- 12h, 34h, Fo,34h, Fo, 12h When you press and hold down a key, that key becomes typematic, which means the keyboard will keep sending that keys make code until the key is released or another key is pressed. Typematic delay :- short delay b/w the first and send character (0.25 sec to 1.00 sec)

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Typematic rate :- how many character per sec will appear on your screen after the typematic delay (2.0 cps to 30.0 cps) Command sets Below are few notes regarding commands the host can issue to the keyboard 1. The keyboard clears its output buffer, when if receives the command 2. If the keyboard receives an invalid command as argument, it must respond with resend (OXFE) 3. The keyboard must not send any scan codes while processing a command 4. If the keyboard is waiting for an argument byte and it instead receives a command it will discard the previous command and process this new one Command that host may send to the keyboard 1. OXFF (Reset) resets the keyboard 2. OFE (Resend) Upon receipt of the re-send command, the keyboard will retransmit the last-byte sent 3. OXFD (Set key Type make) Disable break codes and type matic repeat for specified keys. 4. OXFC (Set key Type make/Break) IIIr to previous command, except this one only disables typematic repeat 5. OXFB (Set key type typematic) :- IIIr to previous command, except this one only disable break codes 6. OXFA (Set all keys Typematic/Make/Break):Keyboard expends with Ack (OXFA) sets all keys to this normal setting (generate scan code on make code, break code & typematic repeat) 7. OXFO :- Set all key make-keyboard responds with ack (OXFA). IIIr to OXFD, except applies to all keys. 8. OXF8 Set all keys make/break):- Keyboard responds with ack (OXFA). IIIr to OCFC except applies to all keys. 9. OXF7 (-Set all key typematic):- IIIr to OXFB except applies to all keys. 10. OXF6 (Set default)-Load default typematic rate/ delay (10, 9 cps /500ms), key types (all keys typematic / make/break) and scan code set (2) 11. OXF5 (Disable) :- Keyboard stops scanning loads default value (See default command) and waits further instruction) 12. OF4 (Enable) :- Re enables keyboard after disabled, using previous command 13. OXF3 (Set typematic rate / delay) 14. OXF2 (Read ID):- The keyboard responds by sending a two-byte device ID of OXAB, OX83

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15. OXFO (Set scan code set):- Keyboard responds with ack then reads argument byte from the host 16. 0x00- the keyboard respond with ack followed by the current scan code set. 17. OXEE (Echo):- The keyboard respond with Echo (0xEE) 18. OXED (Set status LEDS) Turn on or off number lock, caps lock, scroll lock, LEDS. After sending ED, keyboard will reply with ACK (FA), wait another byte which determines their status. Matrix Key Board # include <reg 51.h> # define COL P 0.0-P 0.3 # define ROW P0.4-P0.7 Void MS delay (unsigned int value) Unsigned char keypad [4] [4] ={ 0,1,2,3,456789 ABCDEF Void main ( ) { unsigned char colloc, rowloc ; Unsigned char value ; COL = OXFE ; While ( ) { Do { ROW= 0x00 ; COIIOC = COL; Colloc D=0x0f ; // gnd all rows at once // read the columns // mark used bits

} While (Colloc/ = 0xof); // check until all keys released Do {

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Do { MS Delay (20) ; Colloc = COL; Colloc &= 0xof; } While (Colloc ==0xof); // keep checking/ for key press-// MS Delay (20) ; Colloc=COL; Colloc &=0x0f; }While (Colloc ==0x0f); // Wait for key press While (1) { ROW = 0xFE ; Colloc =COL ; Colloc &=0x0F ; If (colloc = 0x0f) { Rowloc =0 ; Break ; } ROW = OXFD ; Colloc= COL ; Colloc & =OXOF ; If (Colloc =OXOF) // Call delay for debounce // call delay

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{ Rowloc =1 ; Break ; } ROW =OXFB Colloc=COL ; Colloc & =OXOF; If (Colloc =OXOF) { Rowloc =2; Break; } ROW =OXF7; Colloc=COL; Colloc & =OXOF; Rowloc =3; Break; } If (Colloc = OXOE) Value = keypad [row loc] [0]; Else if (Colloc= OXOD) Value = keypad [rowloc] [1]; Else if (Colloc=OXOB) Value = keypad [rowloc] [2];

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Else Value= keypad [rowloc][3]; } MATRIX KEYBOARD INTERFACING :Here the keyboard is organized in a matrix of rows and columns. The processor accesses both rows and columns through ports. So with two 8-bit ports, an 8x8 matrix of keys can be connected to a microcontroller. Here we take an example of 4x4 matrix key board; connected to two ports. The rows are connected to an O/P port and columns are connected to I/P ports. Reading the I/P port will give high level for all colums, where no key is pressed, since they are connected to VCC. If all the rows are grounded, and a key is pressed, one of the column will have o since the key pressed provides the path to ground. Micro controller scan the keyboard continuously to identify the pressed key.

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Scanning of pressed key :First ground all the rows by providing Oto the output latch; then read the columns. It column reads D3-D0=1111, no key has been pressed and continue the process until findout a key is pressed. If one of column bit is zero, it means one key is pressed in that column. If column is 1101, a key in column D1 is pressed. For identifying pressed key, the microcontroller grounds the rows one by one, starting from the top row. Their reads the column. If D3-D0 reads all Is, no key is pressed in that row.

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Then ground the next row and read the column. Continue this until we fin out a O in the column. We can find that the pressed key is in that row. Thus finding the rows and column we can find out the key and then call the these code corresponding to that particular key. Steps for find out the key :1. Start 2. 3. 4. 5. Check whether all the keys are open, if no, wait for all keys are become open. Ground all rows. Read the columns, and check whether it is equal to 11 11. If yes; go to step 4 (no key is pressed) If no, go to stop 6. (key pressed) 6. Wait for debounce 7. Ground next row and read columns. 8. If any column read zero, then find which key is pressed 9. Get scan code from table 10. Return to steps 1.

Program:ASSUME ;P1.0-P1.3 connected to rows, P2.0-P2.3 connected to columns ;ASCII code for pressed key to P0.1- P0.7 MOV P2, # FF H KI : MOV PI,#00 MOV A,P2 ANL A, 00001111B CJNE A, # 00001111B, K ; wait until all keys released K2 : A CALL DELAY MOV A, P2

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ANL A, #00001111B CJNE A, # 00001111 B, OVER SJMP K2. A ebounce OVER 1 A CALL DELAY MOV A, P2 AN L A, # 00001111 CJNE A # 00001111 OVER SJMP K2 OVER : MOV P1, #11111110 B MOV A, P2 ANL A, #00001111B CJNE A, #00001111B, ROW-0 MOV P1, # 11111101 B MOV A, P2 ANL A,#00001111B CJNE A,#00001111, ROW-1 MOV P1,# 11111011 B MOV A, P2 ANL A, # 00001111 B CJNE A,#00001111, ROW-2 MOV P1,#11110111B

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MOV A, P2 ANL A, P2 CJNE A, # 0000 1111, ROW-3 LJMP K2 ROW-0:MOV DPTR, # KCODE 0 SJMP FIND ROW-1: MOV DPTR, #K CODE 1 SJMP FIND ROW-2: MOV DPTR, #K CODE 2 SJMP FIND ROW-3: MOV DPTR, #K CODE 3 SJMP FIND FIND: RRC A JNC MATCH INC DPTR SJMP FIND MATCH : CLR A MOVC A, @A+DPTR MOV P0, A LJMP K1 ASC11 LOOK UP TABLE FOR EACH ROW ORG 300H KCODE 0 : DB 0 1 1 3 K CODE 1 : DB 4 5 6 7

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K CODE 2 : DB 8 9 A B K CODE 3 : DB C D E F DC Motor Interfacing and PWM *DC Motors A direct current motor is used to translates electrical Voltages into mechanical movement. In the DC motor we leave only + ve and ve leads. Connecting them to a dc voltage source moves the motor in one direction. By reversing the polarity, the DC motor will move in the opposite direction. The maximum speed of a DC motor is indicated in rpm and is given in the datasheet. The DC motor has two rpms 1) loaded; 2) unloaded rpm. The no-load rpm can be from few thousands to tens of thousand. The rpm is reduced when moving with a load and it decreases as the load is increased. DC motors also have voltage and current ratings. The nominal voltage is the voltage for that motor under normal condition and can be from 1 to 150 V depending on the motor. As we increase the voltage, rpm increases. The current rating is from 25m A to a few amps depends up on the load. At the load increases, the rpm is decreases, unless the current provided to the motor is increased, which in turn increase the torque. With a fixed voltage, as the load increases, the current consumption of a DC motor is increased. If we over load the motor it will stall and damage the motor due to the heat generated by high current consumption.

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Bidirectional Control Motor operation Off

Using H- Bridge S1 open S2 open S3 open S4 open

Clock wise Counter clock wise Invalid PGM open close

close open close close

open close close

close open close

A switch is connected to pin 2.7. Rotate the motor in clockwise or anti clock wise depends switch position.

ORG MAIN :

OH CLR P1.0 Switch 1

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CLR CLR CLR SETB Clock Wise : JNB SETB CLR CLR SETB

P1.1 P1.2 P1.3 P2.7

Switch 2 ; Switch 3 ; Switch 4 Import mode

P2.7, Counter P1.0 P1.1 P1.2 P1.3 SW 1 SW 2 SW 3 SW 4

SJMP Clock Wise COUNTER CLOCK WISE : CLR SETB SETB CLR P1.0 P1.1 P1.2 P1.3 SW 1 SW 2 SW 3 SW 4

SJMP Clock wise END Pulse width modulation PWM is the different way of controlling the speed of motor. The speed of the motor depends on three factors : (a) load (b) voltage (c) current. For a given fixed load one can maintain a steady speed by using a method called PWM. By changing (modulating) width of the pulse applied to the DC motor can increase or decrease the amount of power provided to the motor, thereby increasing or decreasing the motor speed. Although voltage has a variable duty cycle, by increasing width of the pulse the speed can be increased.

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PWM is so widely used DC motor speed control that the PWM circutry embedded in the chip. PWM circuitry can create the various duty cycle pulses using software and it varies the speeds torque of the DC motor. DC motor control using optoisolator *8051 is protected from EMI created by motor brushes by using an

opto-isolator and a separate power supply. Interfacing Diagram

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PGM for speed control A switch connected to P3.2 for selection

(a)normally the motor runs with a 33% duty cycle (b)When INTO is activated, the motor runs with 10% duty for a short duration ORG SETB JNB 0000 P3.2 Set as input

P3.2, DUTY-TEN SETB P1.0

DUTY-NORMAL :

MOV RO, # 33 A CALL DELAY CLR P1.0

MOV RO, # 67

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A CALL DELAY SJMP DUTY-NORMAL DUTY-TEN : SETB MOV RO, # 10 A CALL DELAY CLR P1.0 P1.O

MOV RO, # 90 A CALL DELAY SJMP DUTY-TEN DELAY : L3:MOV L2:MOV L1:DJNZ DJNZ DJNZ RO, L3 RET END STEPPER MOTOR It is a widely used device that translates electrical pulses into mechanical movement. In application such as disk drives, dot matrix printers robotics etc, the stepper motor is used for position control. Every stepper motor has a permanent magnet rotor (Shaft) surrounded by a stator. The most common stepper motors have four stator windings that are paired with a center tapped common. The center tap allows the change of current direction resulting in polarity change of stator. The stepper motor shaft moves in a fixed repeatable increment which allows one to move it to a precise position. This movement is possible as a result of basic magnetic theory R1, # 20 R2, # 100 R2, L1 R1, L2

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where similar poles repel and opposite pole attract. The direction of rotation is dictated by the stator poles.

WORKING The stepper motor has 6 leads; 4 stator windings and 2 common. When current flows through a stator it will act as a north pole and the opposite stator act as an south pole due to the centre tap. This stator will attract the rotor poles. The activation of stator windings in an order will rotate the rotor. There are several widely used sequences where each has different degree of precision. The common wires are connected to the +ve side of motors power supply (+5v). The four leads of stator winding are controlled by four bits of 8051 ports. Since 8051lakhs sufficient current to drive stepper motor wdgs, we must use a driver such as ULN 2003 (Which also protect the MC from back emf).

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Normal 4 steps sequence :-

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CW

STEP 1 2 3 4

Wdg A 1 1 0 0

Wdg B 0 1 1 0

Wdg C 0 0 1 1

Wdg D 1 0 0 1

ACW

PROGRAM:MOV A, # 66H A A

BACK : MOV P1, RR

A CALL DELAY SJMP BACK. DELAY : H1 : H2 : MOV R2, # 50H MOV R3, # FF DJNZ R3, DJNZ R2, RET. H2 H1

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Step Angle :A is the movement of rotor associated with a single step. It is related to the no. of stator winding and no. of teeth on rotor as Step angle = 360 =7.20 1 step = 1.80 NSxNr angle NS =No. of stator winding. Nr = No. of rotor pairs. (N-S pair). After completing four steps, the rotor rotates only one tooth pitch. Eg:- A stepper motor with 200 steps per revolution has 50 teeth on its rotor. Since 4x50=200 steps are needed for complete revolution. Ie No. of teeth = steps per revolution in a 4 step require 4 Movement per 4 step= 360 No: of teeth There are two another sequences are used to rotate the motor. They are

Half Step (8step) sequence

Step 1

Wdg.A 0

Wdg.B 0

Wdg.C 0

Wdg.D 1

CW

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CCW

2 3 4 5 6 7 8

1 1 0 0 0 0 0

0 1 1 1 0 0 0

0 0 0 1 1 1 0

0 0 0 0 0 1 1

Wave drive 4 step sequence :-

CW

Step

Wdg A B 0 1 0 0 C 0 0 1 0 D 0 0 0 1 CCW

1 2 3 4

1 0 0 0

Frequency measurement using 89C51

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To measure the frequency of a signal, the time period for half cycle is measured which is inversely proportional to the freq. A sinusoidal signal is converted to square wave using voltage comparator (op amp). A diode is used to rectify the O/P signal. A program has been developed to sense the zero instant of the rectified square wave from fig, very near to P3 at its left side the magnitude of square wave is zero and at P4, at logic 1 (+5V). The Mc reads the value at P3 first and then reads the value at P4 and subtract the first from the second value, so the result is non-zero instant point. Suppose MC takes reading at P1& P2 where both magnitudes are zero. Difference of the two values read is zero. So this is not zero instant of wave. At points P4 and P6, the difference of the two values is zero, so it is also not a zero instant point. At P7 & P8 the difference of values is non-zero but as first read value is subtracted from second there is carry. So it is end of half square wave As soon as zero instant point is detected the MC initiates a register (DPTR) pair whose count is incremented from OOOOH until the MC detects the end point of the half square wave

Program MOV P1, # FF (to configure port 1 as an I/P port) Back : MOV A, MOV RO, MOV A, SUBB A, JZ back P1 A P1 RO

MOV DPTR, # 0000

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Again : INC DPTR MOV A, PRC JC END A again Total=6 MSCC P1

For direction of zero instant The different MOV A,P1 instruction is first read of magnitude of square wave, the value is then copied to reg. The 2nd MOV A,P1 takes the second reading of magnitude of wave. The two values are then compared. If zero flag is Set the pt P3 has not occurred if carry is set, end pt, has occur which are not what we want hence the program control just back to reading to values the wave to detect occurrence of once the pt. P3 has been detected, the program moves in a loop which detects the occurrences of P7. The magnitude of the signal is read and loaded into LSB of accumulator. The content of accumulator is rotated through carry to right to bring LSB into carry. If carry is set the end point has not occurred (the signal is still at logic). The program keeps incrementing a counter (DPTR) until a zero is detected. The time taken to increment the counter once is time taken to execute instructions--INC DPTR to JC again once let that time be T. Count in counter xT= half time period of signal. = 1 6 u sec x DPTR x2= frequency Phase Angle and power factor measurement The phase angle between two sinusoidal signals can be measured by MC signals are first converted to square waves. The MC measures the time period

between positive going zero instants of the two signals. Figure shows two sinusoidal signals V & I and corresponding square wave

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Program MOV DPTR, # 0000 MOV P1, # FF MOV P2, # FF BACK MOV A MOV RO, MOV A, SUBB A, JZ BACK DPTR P2 - 2 Micro second - 1 Micro second P1 A P1 RO detecting +ve going zero instant of signal V

Again INC MOV A,

RRC

A detecting +ve going zero instant of second signal I Micro second

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JNC

again END

2 Micro second

= 6 uscc x DPTR COUNT

The zero instants are detected the same way as we did in frequency measurement. After detecting zero instant of first signal a count in data pointer Register is incremented until the +ve going zero instant of second signal I is detected. The count in DPTR x time taken to execute the instructions from INC DPTR to JNC again =x If T is the time period of the two signals phase 6 u scc x DPTR = Total time. Q= x X 360 (in degrees) T Power factor To find power factor is can convert & in degrees to & in radians and write a program to find Cos Q= 1-Q2 + Q4 21 41

C-- LANGUAGE PROGRAM

LCD Interfacing using C- language

# include < reg 51.L> Sfr data = 0x90; S bit RS = P20;

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S bit RW= P21; S bit EN =P2 2; Void MS Delay (unsigned int); Void main ( ) { Lcd cmd (0x38); Ms Delay (250) Lcd cmd (0x0E); MS Delay (250); Lcd cmd (0x01); MS Delay (250); Lcd cmd (0x06); MS delay (250); Lcd cmd (0x84); MS delay (250); Lcd data (N); MS delay (250); Lcd data (0); Void lcd cmd (consigned char value) { Rs=0; R/w=0; En=1; MS delay (1);

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} Void data (unsigned char value) { Rs=1; R/w=0; En=1; MS delay (1); EN=0 } Void MS delay (consigned int itime) { Consigned int x,y; For (x=0; x<itime; x++) For (y=0; y<1275; y++) }

ADC 0804 Infacing using C language

# include < reg 51.h > S bit rs=P2 5; S bit rw= P2 6; S bit INTR =P2 7; Sfr my-data =P1 ; Void main ( )

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{ Unsigned char value; My-data = OXFF; INTR =1 ; WRm = 1 ; RD = 1 ; While (1) ; { WR=0 ; WR=1 ; While ( INTR ==1) ; { RD=0 ; Value=my-data; Display (value); RD=1 ; }

} } DAC Interfacing using C- language

# include <reg 51.h> Sfr DAC DATA = P1 ; Void main ( ) { Unsigned char WAVE VALUE = {128, 192, 238, 255, 238, 192, 128, 64, 17, 0, 17, 64}

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Unsigned char x While (1) ; { For (x=0 ; x<12 ; x++ { DAC DATA = WAVE VALUE (x) ; } } }

Stepper Motor Interfacing using C language

# include < reg 51.h> Sfr P1= 0x90 ; Void main ( ) { While (1) { P1=0x66 ; MS Delay (100) ; P1=0 x CC; MS Delay (100) ; P1=0x99 MS Delay (100) ; P1=0x33

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MS Delay (100) ; } }

DC Motor Speed Control using C- language

Program : (1) When switch is closed, motor runs with 50% duty cycle (2) When switch is opened, motor runs with 75% duty cycle # include < reg 51.h> S bit SW=P2 7 ; Void main ( ) { SW=1 ; MTR =0 ; While (1) { If (SW) ==1) { MTR =1 MS Delay (75) ; MTR =0 MS Delay (25) ; } else { S bit MTR = P1. 0 ;

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MTR =1 ; MS Delay (50) ; MTR =0; MS DELAY (50) ; } } } Alternative method Measurement of an in put signal frequency If the signal is square wave then it can be connected to external Timer input to directly. If the signal is sine wave it has to be converted in to square wave by using a comparator & rectifier Input is connected to To. The method is to count the number of pulses in the fixed internal of 1 Sec or it can be counter 125m/sec & multiply by 8 into fire for 1 refund Sequence of operation -Counter 0 is configured as external event counter C/T =1 mode 1 -Timer 1 is programmed for the internal of 125 MSC mode 1 -Counter 0 turned on TRO=1 -Timer 1 turned on TRI=1 -Timer 1 will overflow after a delay TFI is checked if it is set read the content of counter 0 (Read THO TLO) -The value gives the no of cycles in 125 m sec -Multiply by 8 gives the frequency of the input signal -Decide the timer 125 MSCC in related to the input clock frequency of the controller or clock frequency

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Program to Count the frequency of an input signal Assume clock frequency 6MHZ -Configure counter 0 for External event -Configure Timer 1 mode 1 and overflow for 125 m sec -Frequency of timer 6MHZ = 0.5 MHZ 12 -Time for each unit 0.5 MHZ =2 Micro Second -Timer value = 65536-125mscc 2 micro sec = 65536-62500 = 3035 = OBDCH TH = OB ORGOOH LJMP Timers ORG 100 Timers MOV TMOD # 15 h Set timer/timer 0 mode 1 EXT/event ; timer 1 mode 1 Low byte TL=DC

MOV TLI #DC MOV THI #OB SETB SETB HERE TRO TRI JNB TFI

High bite Timer/counter 0 RUNS Timer/counter 1 RUNS HERE over flow T1 Clear over flow bit Clear counter RUN=0 Clear timer run

CLR TFI CLR TRO CLR TRI

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MOV R0 TLO Counter 0 (TLO) to/RO Counter 0 (TLO) to R0 MOV R1 THO Counter 0 (THO) to/RI MOV R2 # 3 MUL 8 MOV A, R0 CLRC RLCA MOV R0, A MOV A, R1 RLC MOV R1, A DJNZ R2 MUL 8 END R0 R1 will have the frequency of the input. Design of a position control system interfacing Position sensors are used for application like robot ARM positioning, pen positioning of strip chart recorder. Easy way of meaning position is by using potentiometer Assuming that the Robot arm moves from 00to 1200. This in order to increase the resolution there is 1:2 gear is introduced between arm movement & potentiometer. The potentiometer will move 0-2400 corresponding voltage will be generated and fed to the Microcontroller. The potentiometer 1kwire wound with 2 700 range can be inter connected to the gear of the robot arm. The proportional voltage can be converted to digital value by ADC and connected to 8051 Microcontroller. The Robot arm position in degree becomes proportional to the potentiometer voltage. Load LSB Clear carry Rotate left with carry Back to R0 Load MSB Shift with carry of LSB Back to R1 Counter 0(THO) to R1

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Robot Arm 00 100 1200 122.50

Potentiometer 0 200 2400 2550

ADC 0 0.3920 4.7314 5.0000

Digital output 00000000 00010100 11110000 1111 1111

Excitation voltage 6.86V Voltage 5.33V-270 10=0.01974 ADC= 255= 11111111 =122.50

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Alternate Method Angular position can be measured by optical encoders. The encoder generates the digital data corresponds to the angular position of the shaft. There are two type encoders 1) Absolute Encoder 2) Incremental Encoder. Absolute encoder gives the angular position directly Incremental encoder provides the relative position.

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Optical incremental encoder no of equally spaced opaque or transparent mark in the circumference of the disc. The disc can be calibrated to 12,24,36,2500,5000 no of opaque and transparent marks which can be sensed by a photo detect or & light source. The output of the photo detector will be either 0 or 1 since the mark are equally spaced the frequency will be uniform. There will be 3 photo sensors to detect A track, B track, C track. CW direction A leads B by 900 CCW direction B leads A by 900. It will be sensed by photo selector. Track C the zero reference pulse. The clock output will be made TTL compatible and gives to Micro controller. In order to avoid noise in the line Schmitt triggers are used as buffers. The Encoder used for very high speed positioning. The frequency is depends up an rpm of rotation of the disc. The pulses A and B are inputted through the Exclusive or gate. The output of the gate will generate two pulses and hence, two raising two falling edges. Thus we will get 4 pulses in one period. It indicates the resolution will increase 4 times of the number of clock pulses. For example if you take 256 pulses /rev encoder it will generate 1024 pulses/rev at the microcontroller. Also it gives the direction by sensing which signal A or B leading. The rising & falling edge of the pulses can decode the position signal. After each interrupt, the interrupt service subroutine should toggle this interrupt edge select bit and the input the three channel signal A,B,C depending upon the current & previous A & B bits the direction can be decoded and position variable i.e. angle is either incremented (CW) or decremented (CCW). Each reference pulse C the position count value (Angle) will be cleared.

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