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Environment
Introduction
CadenceisanElectronicDesignAutomation(EDA)environmentwhichallows differentapplicationsandtoolstointegrateintoasingleframeworkthusallowingto supportallthestagesofICdesignandverificationfromasingleenvironment.These toolsarecompletelygeneral,supportingdifferentfabricationtechnologies.
ThevariousDesignsteps
FirstlyaschematicviewofthecircuitiscreatedusingtheCadenceComposer SchematicEditor.Alternatively,atextnetlistinputcanbeemployed. Then,thecircuitissimulatedusingtheCadenceAffirmaanalogsimulation environment.Differentsimulatorscanbeemployed,somesoldwiththe Cadencesoftware(e.g.,Spectre)somefromothervendors(e.g.,HSPICE)iftheyare installedandlicensed. Oncecircuitspecificationsarefulfilledinsimulation,thecircuitlayoutiscreated usingtheVirtuosoLayoutEditor.Theresultinglayoutmustverifysomegeometricrules
dependentonthetechnology(designrules).Forenforcingit,aDesignRuleCheck (DRC)isperformed. Then,thelayoutshouldbecomparedtothecircuitschematictoensurethatthe intendedfunctionalityisimplemented.ThiscanbedonewithaLayoutVersusSchematic (LVS)check. AlltheseverificationtoolsareincludedintheDivasoftwareinCadence(more powerfulCadencetoolscanalsobeavailable,likeDracula,orAssuraindeepsubmicron technologies). Finally,anetlistincludingalllayoutparasiticsshouldbeextracted,andafinal simulationofthisnetlistshouldbemade.ThisiscalledaPostLayoutsimulation,andis performedwiththes ameCadencesimulationtools.Onceverifiedthelayoutfunctionality,thefinallayout isconvertedtoacertainstandardfileformatdependingonthefoundry(GDSII,CIF,etc.) usingthe Cadenceconversiontools.TheSummaryofthedesignstepsisagainexplainedwith aninverterexampleasfollows.
1.InvokingCadencetool
ThecommandInterpreterWindowcanbeinvokedbytyping icfb& Thetoolisavailableonvlsi34,vlsi35,vlsi36,vlsi27.Thefollowingwindowwill appearonthescreenoninvokingthecommand.
2. CreateLibrary
InordertocreatethelibrarygotoTools>LibraryManagerontheToolsmenu oftheCIW.
NowtocreateanewlibrarygotoFile>New>LibraryfromtheFilemenuof theLibraryManager.
Thenfillinthenameofthenewlibrary.ClickOK.Thefollowingfigureappears.
NowclickonAttachtoanexistingtechfileasshown
NowthelibraryyoucreatedshouldappearintheLibraryManagerwindow.
3.CreateSchematic
Startbyclickingonthelibrary(createdbyyou)intheLibraryManagerwindow, thengotoFile>New>CellViewandfillinwithInverter(inthiscase) asthecellname,schematicastheviewname,andComposerSchematicasthe tool,thenpressOK.
AnemptyWindowappearsasnextfigure.
Youcaneditthepropertiesoftheinstancewhentheabovefigureappears
NowClickontheSchematicwindowtoplaceaninstanceasshownbelow Similarlyyoucanplacepmos. YoucanpresstheESCkeyonthekeyboardtogetoutoftheplaceinstancemode oryoucankeepplacingotherparts. 3.2AddingtheI/OPins InthelowerleftsideoftheComposerwindowclickonthePinicon.Addtheinput andoutputpins,shownasfollowing. UnderPinNames,typeInorOutoranyothername.NotethatDirectioninthe formreadsinputoroutput. 3.3AddingWires OntheleftsideoftheComposerwindowclickontheWireicon.Nowclickonthe schematicfromwhereyouwantto
drawthewireandclickonthepointwhereyouwanttofinishthewire.Thefinal schematicshouldlooksomewhatlikethis:
4. Simulation
IntheVirtuosoSchematicwindowgotoTools>AnalogEnvironment.Thereis goingtotheanother"What'sNew"popupwindowthatyoucanreadandcloseor minimize.
ThedesignshouldbesettotherightLibrary,CellandView.Thewindowappearsas shownbelow.
5.Layout
Wewillusealayoutthathasasimilartopologytotheschematic.Itwillhave horizontalvdd(top)andgnd(bottom)linesINontheleft andOUTontheright,allinmetal1. TostarttheVirtuosoXLenvironment,opentheschematicviewofcellinverter. Next,inthe Composerwindow,clickonTools>DesignSynthesis>LayoutXL. TheVirtuosoXLStartupOptionwindowwillappear,askingwhetheranewlayout cellviewshouldbecreatedoranexisting layoutcellshouldbeused.EnableCreateNewandclickonOK.ACreateNewFile windowwillthenappear.
theGNDrailisgenerallybelowthecell.Ingeneral,thepowerandgroundrailshavea fixedspacingbetweenthemsothatdifferentcellscaneasilybeconnectinarow. AddPins Onceyouhavefinishedcreatingthelayout,thenextstepistoaddtheI/Opinsofyour circuit.Itisnecessarytoaddthevdd!andgnd!pinstoyourcircuitforthepurpose ofverification(ifyouhaveusedtheseterminalsintheschematic).Netlabelsendingin ! meanglobalnodes(i.e.,allwiresintheentiredesignhierarchylabeledwiththisname are consideredtobeconnected,eveniftheyphysicallyarenot.Theyareusuallypower nets). ThefollowingisaprocedureforaddingI/Opinstoyourcircuit: FromyourLayoutwindow: 1.ChooseCreate>Pin...fromthemenu.TheCreatePinformwillappear
6.Verification
Errorsarealsoindicatedbythemarkers(whitecolor)onthecircuit. Youmaythenproceedtocorrecttheerrorsaccordingtothedesignrules. Forhugelayouts,themarkersmightnotbeeasilylocated.Tofindmarkers, chooseVerify>Markers>Findinlayoutwindow. Apopupmenuwillappear.ClickontheZoomtoMarkersbox. 6.2LayoutversusSchematic(LVS) Oncethelayoutfulfillsallthedesignrules,thenextverificationstepfollows.The netlistbehindthe layoutviewisextractedandcomparedtothatoftheschematicview.Thisisthe LayoutVersus Schematic(LVS)Check. IntheVirtuosolayoutwindow,selectAssura>RunLVS.