Vlsi Manual

VLSI Lab Manual
(Session: Jan May 2012)
LIST OF EXPERIMENTS Cycle I 1. Design Inverter using FETs. 2. Design two input NAND and NOR. 3. Design XOR and XNOR. 4. Design AND and OR using instantiation. Cycle II 5. Realization of Boolean expressions. 6. Design D, T, JK and Master Slave flip-flops. 7. Implement serial and 2 bit parallel adders. 8. Implement 4 to 1 Multiplexer. Cycle III 9. Implement shift register capable of holding and shifting 4 bit words. 10. Design asynchronous and synchronous 4 bit counters. 11. Design of 6T SRAM cell with 4-bit line and Word line control. 12. Design and implement 4 X 4 barrel shifter.
Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B
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VLSI Lab Manual

Experiment 1
AIM: Draw a circuit for inverter for specified length and width using schematic and for the same draw the layout a) For the above verify the timing diagrams in both schematic and layout. b) Plot voltage v/s time and VTC (Voltage transfer characteristics). c) Perform LVS for the same. THEORY: The digital Logic NOT Gate is the most basic of all the logical gates and is sometimes referred to as an Inverting Buffer or simply a Digital Inverter. It is a single input device which has an output level that is normally at logic level "1" and goes "LOW" to a logic level "0" when its single input is at logic level "1", in other words it "inverts" (complements) its input signal. The output from a NOT gate only returns "HIGH" again when its input is at logic level "0" giving us the Boolean expression of: A = Q.Then we can define the operation of a single input logic NOT gate as being: "If Input is NOT true, then Output is true" The Digital Inverter or NOT gate Symbol Truth Table A 0 1 Boolean Expression Q = not A or A PROCEDURE S-EDIT: 1) Click on S-EDIT icon on desktop. 2) From File click on NEW and open the new design. i. New design - name the design 3) Select Cell from the tool bar ->New view -> Give the cell name and select view type as schematic 4) Go to Library window and click on ADD button to select library. Path to select the library --- my doc\ tanner EDA\ Tanner tool\ Libraries\ all 5) In the library window i. select devices to select nMOS, pMOS etc., select the required component and drag & drop in the cell. ii. Select Misc to select Vdd and Gnd. ( drag and drop) 6) Ctrl R is used to rotate the components. 7) Build circuit ( using wire icon from the tool bar to make the connections and input port and output port to make the input and output connections) 8) Check the schematic for any errors. ( click on the double tick icon on the tool bar) i. If any errors or warnings it will display (correct both errors and warnings) 9) Click on Open in T-spice from the tool bar. NOTE: Alt + left mouse button will help to drag any component after selecting it. Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B Page 2/ 37 Q 1 0
Read as inverse of A gives Q
VLSI Lab Manual

S-EDIT FILE:
T-SPICE: (AFTER SCHEMATIC) 1) Open T-SPICE file from schematic window toolbar and save it in the desired location.(do save as ) 2) On toolbar of the T-SPICE , click on INSERT COMMAND prompt. 3) Keep the cursor where the arrow marks shown of the T-SPCIE window and Select:
FILES->Library file Browse for the technology file (path : my doc\ Tanner EDA\ tanner tool\libraries \ models \ generic_025.lib)and Type TT in the Library. --- > Click on insert button Voltage Source->Constant ->Voltage Source name: V1 ->Positive terminal: Vdd ->Negetive terminal: Gnd ->DC value: 5 To initialize the input Voltage source name: v2 Positive terminal: wirte the port name what you have given in Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B Page 3/ 37
VLSI Lab Manual

the schematic diagram Negetive terminal: Gnd DC value : 5 input can be bit stream or pulse. Then click on insert button. Analysis in this select Transient maximum step size: 10n simulation length: 100n start time: 0n (Note: above values can vary subject to design) Then click on insert button DC analysis DC transfer sweep sweep type : linear parameter type : source parameter name: name the voltage source of the input start voltage : 0 and Stop voltage: 5 Increment : 0.1( as your wish) Then click on accept Next click on insert button.
Output click on transient result if the analysis is transient /click on DC results is the analysis is DC analysis. enter the node name of both input and output ( which waveforms you have to observer, that particulars node names should be entered)
click on insert button. SAVE. 4) Select the RUN simulation option from the toolbar. (Click on the green arrow ) 5) Verify the waveforms.
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VLSI Lab Manual

T-SPICE FILE: (AFTER inserting the commands netlist of the schematic) For Transient Analysis and DC Analysis:
W-EDIT WAVEFORM (S): after clicking the simulation button in the T-SPICE
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VLSI Lab Manual

L-EDIT: 1) Open L-EDIT icon on desktop. 2) Select FILE from toolbar and go to New File. 3) Browse and add TDB setup file Generic_025.tdb ( my doc\ tanner EDA\ tanner tools\LVS and Ledit\ tech\generic_025 4) Go to Cell in the tool bar, Select instance, browse for T-Cells ( path: my doc\ tanner EDA \ TCells or my doc\ T-Cells ) and select instantiate p and n transistors from T-cell library (TC_NMOS and TC_PMOS).Keep the L and W values of transistors same as in s-edit. 5) Complete the layout connections and Select A (port) option from toolbar to NAME all the ports as per the schematic circuit design. 6) Click on the layer you want to name. 7) Select the ON LAYER and enter its PORT NAME. 8) SAVE the file in the form - <filename_l.tdb> 9) Perform Design rule check and if any errors, correct all the errors.. 10) Click on Setup Extract ->Check on (check book ) extract standard rule set- click on the pencil/pen icon browse the path for extract file ( my doc\ tanner eda\ tanner tools\ LVS and L-edit\ tech\ generic_025u\generic.ext give the output location where you want to save ( T-SPICE of the Layout ) 11) Select EXTRACT from the toolbar. 12) Next open the T-SPICE file where you have save and repeat all the steps the 2 to 6 of the TSPICE ( what you did after the schematic) LAYOUT:
T-SPICE FILE: (netlist of the layout ) Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B Page 6/ 37
VLSI Lab Manual

W-EDIT WAVEFORM (S): AFTER LAYOUT
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VLSI Lab Manual

LVS: 1) 2) 3) 4) Open LVS from the desktop. Go to New->LVS Setup->Add layout and schematic netlist which are spice files. Perform Run Verification Check for the schematic and layout equality.
Results:
Marks:
Signature of the Faculty:
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VLSI Lab Manual

Experiment 2 AIM: Draw the circuits for nand and nor for specified length and width using schematic and for the same draw the layout a) For the above verify the timing diagrams in both schematic and layout. b) Perform LVS for the same S-EDIT PROCEDURE:
T-SPICE FILE:
W-EDIT FILE:
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VLSI Lab Manual

L-Edit Procedure:1) Construct the layout as shown below
2)Set up extraction and extract the spice output. 3)Add all the required simulation commands and check for the waveforms. These waveforms should match the Schematic waveforms. 4) Perform the LVS to check whether schematic and layouts are same. Similarly perform an experiment for NOR functionality as well.
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VLSI Lab Manual

Schematic: Layout:
Results:
Marks:
Signature of the Faculty: Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B Page 11/ 37
VLSI Lab Manual

Experiment 3 AIM: Draw the circuits for XOR and XNOR for specified length and width using schematic and for the same draw the layout a) For the above verify the timing diagrams in both schematic and layout. b) Plot voltage v/s time and input voltage v/s output voltage. c) Perform the LVS to check circuit and layout equality.
Theory: XOR Gate: The exclusive-OR (XOR), operator uses the symbol and it performs the following logic , operation: X Y = X Y + X Y The graphic symbol and truth table of XOR gate is shown in the figure.
The result is 1 only when either X is equal to 1 or Y is equal to 1, but not when both X and Y are equal to 1. XNOR Gate: The exclusive-NOR (XNOR), operator uses the symbol , and it performs the following logic operation X Y = X Y + X Y = (X Y) The graphic symbol and truth table of XNOR (Equivalence) gate is shown in the figure.
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VLSI Lab Manual

The result is 1 when either both X and Y are 0s or when both are 1s. That is why this gate is often referred to as the Equivalence gate. The truth tables clearly show that the exclusive-NOR operation is the complement of the exclusive-OR. This can also be shown by algebraic manipulation as follows: (X Y) = (X Y + X Y) = (X Y) (X Y) = (X + Y) (X + Y) = (XY + XY) =X The XOR gate can be constructed using MOSFETS as shown below:
Schematic:
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VLSI Lab Manual

T-Spice:
Layout:
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VLSI Lab Manual

Spice Net list(Layout):
Waveforms:
Perform the LVS for both schematic and layout. Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B Page 15/ 37
VLSI Lab Manual

Similarly perform an experiment for XNOR functionality as well. Schematic:
Net List:
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VLSI Lab Manual

Layout:
Simulations:
Results: Marks:
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VLSI Lab Manual

Experiment 4 AIM: Draw the circuits for AND gate and OR gate for specified length and width using component instantiation in schematic editor and for the same draw the layout a) For the above verify the timing diagrams in both schematic and layout. b) Plot voltage v/s time and input voltage v/s output voltage. c) Perform the LVS to check circuit and layout equality.
Procedure: And Gate: 1) Construct NAND gate and Inverter using the procedure mentioned before in s-edit using MOSFETs. 2) Create a symbol for Nand and Inverter with the procedure below. Creating a Symbol: 1) Construct a Nand Gate with MOSFETs as shown below. 2) Go to Cell in the tool bar and click on Update Symbol. The symbol will be created. Check for its functionality in T-spice and save the s-edit project.
3) Similarly construct the Inverter and update the symbol. Check its functionality in T-spice and save the s-edit project. 4) Open a new project to construct and gate. Go to Add in the library Browser and add Nand and Inverter files which were constructed as shown below.
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VLSI Lab Manual

5) Construct the And circuit with the symbols of Nand and inverter as shown below.
6) Check the functionality in T-spice.
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VLSI Lab Manual

Waveforms in W-Edit:
L-Edit: Note: Add one inverter to the output of Nand gate. Use poly contact while joining poly and metal. Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B Page 20/ 37
VLSI Lab Manual

7) Similarly Construct Or gate using component instantiation in s-edit, Verify its functionality using T-spice.Build the layout by adding inverter to the output of the NOR gate. 8) Perform the LVS for schematic and layout in both And gate as well as in Or gate to check the circuit equality in schematic and layout.
Results:
Marks:
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VLSI Lab Manual

Experiment 5
AIM: Simplify the given expression and implement using the Universal (NAND) Logic Gates. Use automatic place and Route for the layout. Ex: 1) Y = ABC+ABC+ABC+ABC. Simplify this. This can be reduced to AB+BC+CA Procedure: 1. Construct the schematic for the above equation using only universal gates (Nand). 2. Before implementing in schematic check the cell name and the port names of the logic gates to be used in the circuit. 3. Steps for the (2) : a. Open the L-Editor. File->New->browse for morbn20d.tdb file(MyDocuments/morbn20d/morbn20d.tdb) b. Go to Cell->Instance->browse for morbn20d file. (same path as above) Now go through the list of the library components. Click the required cell and instantiate in the L-Editor. From that instance note down the input and output port names. And also note the cell name in the list. 4. In schematic Editor: ( this steps are only for the logic gates(ex. Only for one nand gate) a. File->New Design->Design Name. b. Cell->New Cell->cell name(same as the cell name in L-Editor library) c. Draw the schematic and give the input and output names same as(3b) d. Update the symbol : Cell->Update symbol. e. Go to properties window click on property icon.(View->properties) and add the properties as shown in the below window
5. Implement the given expression in a New design instantiating the cell created in step (4) in S-Editor. Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B Page 22/ 37
VLSI Lab Manual

6. Once the circuit is completed check for errors and simulation. Export the design by using following steps. Files->Export->Export TPR-> Give the path (your design folder) to save the exported file in .tpr format and click on Export.
7. Go to L-Edit open New Design. File->New->browse for morbn20d.tdb file(MyDocuments/morbn20d/morbn20d.tdb) 8. Click on Tools (from toolbar) -> SPR -> Place and Route 9. A window will pop up. Uncheck the last two options(Pad setup) .Then click on Setup from the same window. Here browse for the technology file(morban20d.ext) and browse the path of the net list file ( .tpr file; path saved in step(6) ). Click on OK and then click on Run button. 10. Layout will be generated automatically in the layout window for the designed circuit
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VLSI Lab Manual

Example of the .tpr file

C Nand2 A B Out; UNand2_1 A A N_1; C Nand3 A B C Out; UNand3_1 N_6 N_5 N_4 Out; C Nand2 A B Out; UNand2_2 B B N_2; C Nand2 A B Out; UNand2_3 C C N_3; C Nand2 A B Out; UNand2_4 N_2 N_1 N_4; C Nand2 A B Out; UNand2_5 N_3 N_2 N_5; C Nand2 A B Out; UNand2_6 N_1 N_3 N_6;
Results:
Marks:
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VLSI Lab Manual

Experiment 6
AIM: Draw the schematic using component instantiation in schematic editor for a) J K Flip flop b) J K Master Slave Flip flop c) D Flip flop d) T Flip flop Verify the timing diagrams in schematic and generate the layout for the same using Place and route.
Procedure:
Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B Page 25/ 37
VLSI Lab Manual

Follow the same procedure given in the Experiment 5 Layout: generated layout for the MSJKFF
Similarly implement for the DFF and TFF
Results:
Marks:
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VLSI Lab Manual

Experiment 7
AIM: Design Serial and paralle adder and draw the schematic using component instantiation in schematic editor and for the same generate the layout using Place and route. Verify the timing diagrams in schematic.
Circuit Diagram:
Procedure:
Same as in experiment 5 S-EDIT FILE:
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VLSI Lab Manual

Generated Layout for the above circuit
Note: Similar procedure is followed for the construction of parallel Adder.The schematic of parallel adder is as given below:
Results:
Marks:
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VLSI Lab Manual

Experiment 8
AIM: Design 4:1 Mux and draw the schematic using component instantiation in schematic editor and for the same generate the layout using Place and route. Verify the timing diagrams in schematic. Implement using universal gates.
Procedure:
Follow the steps as in experiment 5
S-Edit:
Generated layout for the above circuit:
Results: Marks:
VLSI Lab Manual

Experiment 9
AIM: Design of Asynchronous, Synchronous Up-Down counters with minimum number of gates and draw the schematic using component instantiation in schematic editor and for the same generate the layout using Place and route. Verify the timing diagrams in schematic.
DESIGN OF SYNCHRONOUS COUNTER

TRUTH TABLE Q3 Q2 Q1 Q0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Q3+ 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Q2+ 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Q1+ 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Q0+ 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Now, using the karnaugh map we find the simplified expressions for Q3+, Q2+, Q1+, Q0+
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VLSI Lab Manual

PROCEDURE:
1.) In the first step for building the circuit for a synchronous counter, design a D-FF using NAND2 NAND3 gates as shown below using component instantiation: (create the cell name and port name same as in the morbon20(in L-edit)).
2.) Update the symbol
3.) Add the DFF cell(symbol) in the library. Instantiate DFF to build the Asynchronous counter. Same way build the circuit for Synchronous counter along with required gates as per the above design. Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B Page 31/ 37
VLSI Lab Manual

Asynchronous Counter:
Synchronous Counter:
4.) Check the working of the both COUNTERs and verify the truth table as per the usual procedure of T-SPICE and W-EDIT. W-EDIT FILE:
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VLSI Lab Manual

5.) Export the schematic and generate the layout by TPR.
Results:
Marks:
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VLSI Lab Manual

Experiment 10
AIM: Design SERIAL REGISTER capable of holding and shifting 4 bit words and draw the schematic using component instantiation in schematic editor and for the same generate the layout using Place and route. Verify the timing diagrams in schematic. Circuit
A Simple Shift Register Consisting of D-type Flip-flops
PROCEDURE:
1.) Use the same DFF used in counters.
2.) Circuit diagram.
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VLSI Lab Manual

3.) Export the schematic and generate the layout by TPR.
Results:
Marks:
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VLSI Lab Manual

Experiment 12
AIM: Design a barrel shifter using nMOSFETs and draw the schematic in schematic editor Verify the timing diagrams in schematic for shift right operation. Theory: A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift distance. For example, take a 4-bit barrel shifter, with inputs A, B, C and D. The shifter can cycle the order of the bits ABCD as DABC, CDAB, or BCDA; in this case, no bits are lost. That is, it can shift all of the outputs up to three positions to the right (and thus make any cyclic combination of A, B, C and D). The barrel shifter has a variety of applications, including being a vital component in microprocessors (alongside the ALU). A common usage of a barrel shifter is in the hardware implementation of floating-point arithmetic. For a floating-point add or subtract operation, the significant of the two numbers must be aligned, which requires shifting the smaller number to the right, increasing its exponent, until it matches the exponent of the larger number. This is done by subtracting the exponents, and using the barrel shifter to shift the smaller number to the right by the difference, in one cycle. If a simple shifter were used, shifting by n bit positions would require n clock cycles.
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VLSI Lab Manual

Results:
Marks:

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VLSI Lab Manual

(Session: Jan May 2012)

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Read as inverse of A gives Q

VLSI Lab Manual

VLSI Lab Manual

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

VLSI Lab Manual

W-EDIT WAVEFORM (S): AFTER LAYOUT

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Signature of the Faculty:

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

L-Edit Procedure:1) Construct the layout as shown below

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

VLSI Lab Manual

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Spice Net list(Layout):

VLSI Lab Manual

Similarly perform an experiment for XNOR functionality as well. Schematic:

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Signature of the Faculty:

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

6) Check the functionality in T-spice.

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

VLSI Lab Manual

Signature of the Faculty:

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

VLSI Lab Manual

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Example of the .tpr file

Signature of the Faculty:

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

VLSI Lab Manual

Similarly implement for the DFF and TFF

Signature of the Faculty:

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Faculty Incharge: Mrs. Rekha S S Mr. Ravikant G B

VLSI Lab Manual

Generated Layout for the above circuit

Signature of the Faculty: