Re: systemverilog interface connects RTL and TML

Re: systemverilog interface connects RTL and TML

Source: http://newsgroups.derkeiler.com/Archive/Comp/comp.lang.verilog/200707/msg00072.html

From: Kecheng <kechenghao@xxxxxxxxx> Date: Wed, 18 Jul 2007 04:15:03 0000 Thank you very much for your explaination, it make me much more clear about the TLM design in SystemVerilog, and it make me more intereted in this methodology. But I'm still have questions, you know the TML could speed up the simualtion time, it gets rid of timing. this in SystemVerilog, it seams that the TL interface only encapsulate the timing into the task, like the example you show me. And I also find an example from DOULOS. It's an APB bus interface. interface APB ; // See also modports and tasks: // // modport RTL_slave connect any RTL slave model to one of these // modport RTL_master connect an RTL master model to this (one only) // modport TF_master Connect a behavioural master to this (one only) // task read; BFM entry point for behavioural tests // task write; BFM entry point for behavioural tests // __________________________________________________________________________ parameter master_Tco = 1; logic PCLK; logic psel = 0; // Address signal from master // T_APB_a PADDR; // Write data, from master // T_APB_d PWDATA; // Write and enable signals from master // logic PWRITE = 0; logic PENABLE = 0; Re: systemverilog interface connects RTL and TML 1

Re: systemverilog interface connects RTL and TML // Readback data signal, written by selected slave // T_APB_d PRDATA; // __________________________________________________________________________

// _____________________________________________________________ MODPORTS ___ // Any slave connects like this... // modport RTL_slave ( input PCLK, // Slaves get their clock from the bus //input psel, // Select signal global for all slaves input PWRITE, // Active in the clock when address is sent input PENABLE, // Direction control, sent with the address input PADDR, input PWDATA, output PRDATA ); // modport RTL_slave // The one and only master connects like this: // modport RTL_master ( output PCLK, // Master supplies clock to the bus output PWRITE, // Active in the clock when address is sent output PENABLE, // Direction control, sent with the address output PADDR, output PWDATA, input PRDATA ); // modport RTL_master // Alternatively you can connect a behavioural master // to this BFMlike modport: // modport TF_master ( output PCLK, // Master supplies clock to the bus import task master_write(), import task master_read() // Master calls these tasks to do cycles ); // modport TF_master

// _____________________________________________________ BFM ENTRY POINTS ___ // Nonsynthesisable taskcall interface for a testbench master Re: systemverilog interface connects RTL and TML 2

Re: systemverilog interface connects RTL and TML // so that it can exercise slaves on the bus without the need for // a fullyfunctional model of a master device.

// Call read and write tasks at the posedge of the clock // right at the beginning of the cycle. They return just after // the final posedge of the cycle. task master_read ( input T_APB_a adrs, output T_APB_d data ); time start_delay; CheckLastClock(start_delay); #(start_delay) PADDR = adrs; PWRITE = 1'b0; psel = 1'b1; @(posedge PCLK) PENABLE <= #master_Tco 1'b1; @(posedge PCLK) data = PRDATA; PADDR <= {$bits(PADDR){1'bx}}; psel <= 1'b0; PENABLE <= 1'b0; endtask // read task master_write ( input T_APB_a adrs, input T_APB_d data ); time start_delay; CheckLastClock(start_delay); #(start_delay) PADDR = adrs; PWDATA = data; PWRITE = 1'b1; psel = 1'b1; @(posedge PCLK) PENABLE <= #master_Tco 1'b1;

Re: systemverilog interface connects RTL and TML

Re: systemverilog interface connects RTL and TML @(posedge PCLK) PWDATA <= {$bits(PADDR){1'bx}}; PADDR <= {$bits(PADDR){1'bx}}; psel <= 1'b0; PENABLE <= 1'b0; endtask // write Then, if I define the master at transaction level like this. module master_TF ( APB.TF_master apb, output logic async_reset ); localparam period=10, MEMADDR=16'h0001; logic signed [15:0] data=16'hFFFF; logic signed [15:0] newdata=16'hzzzz; initial $timeformat (9,0,"ns",8); always begin: ClockGenerator apb.PCLK=0; apb.PCLK <= #(period/2) 1; #period; end //ClockGenerator initial begin: TestSequence //reset async_reset=1; //apb.idle(4); @(negedge apb.PCLK) async_reset=0; //wait for a few rising clcks //apb.idle(3); //write operation apb.master_write(MEMADDR, data); $display ("write data to the memory"); //read operation apb.master_read(MEMADDR, newdata); $display ("read data from the memory new data= %x",newdata);

end //TestSequence endmodule Re: systemverilog interface connects RTL and TML 4

Re: systemverilog interface connects RTL and TML And I also can define the master at RTL level. module master_RTL ( APB.RTL_master apb, output logic async_reset ); localparam period=10, MEMADDR=16'h0001, master_Tco=1;

logic signed [15:0] data=16'hFFFF; logic signed [15:0] newdata=16'hzzzz; always begin: ClockGenerator apb.PCLK=0; apb.PCLK <= #(period/2) 1; #period; end //ClockGenerator initial begin: TestSequence //reset async_reset=1; //apb.idle(4); @(negedge apb.PCLK) async_reset=0; //write operation write(MEMADDR, data); $display ("write data to the memory"); //read operation read(MEMADDR, newdata); $display ("read data from the memory new data= %x",newdata); end //TestSequence task read ( input T_APB_a adrs, output T_APB_d data ); // Get to Tco after the most recent possible clock ClockTcoSync; apb.PADDR = adrs; apb.PWRITE = 1'b0; @(posedge apb.PCLK) apb.PENABLE <= #master_Tco 1'b1; @(posedge apb.PCLK) Re: systemverilog interface connects RTL and TML 5

Re: systemverilog interface connects RTL and TML data = apb.PRDATA; apb.PADDR <= {$bits(apb.PADDR){1'bx}}; apb.PENABLE <= 1'b0; endtask // read // ______________________________________________________ write() ___ // task write ( input T_APB_a adrs, input T_APB_d data ); // Get to Tco after the most recent possible clock ClockTcoSync; apb.PADDR = adrs; apb.PWDATA = data; apb.PWRITE = 1'b1; @(posedge apb.PCLK) apb.PENABLE <= #master_Tco 1'b1; @(posedge apb.PCLK) apb.PWDATA <= {$bits(apb.PADDR){1'bx}}; apb.PADDR <= {$bits(apb.PADDR){1'bx}}; apb.PENABLE <= 1'b0; endtask // write task ClockTcoSync; time t; // If this task was called as the result of a clock edge, we must // be sure that the LastClock value has already been updated. // That's why we need a #0 delay prefix here. // #0 t = $time ClockEdgeLogger.LastClock; // Are we too late to start the bus cycle on the current clock? // if (t > master_Tco) begin // Yes, we're too late. Wait for the next clock. @(posedge apb.PCLK) t = master_Tco; end else begin // No, we're in time. Calculate how long we need to wait // before applying the right signals. Re: systemverilog interface connects RTL and TML 6

Re: systemverilog interface connects RTL and TML t = master_Tco t; end // Finally, align to Tco after the chosen clock #(t); endtask always @(posedge apb.PCLK) begin : ClockEdgeLogger time LastClock; LastClock = $time; end // ClockEdgeLogger endmodule You see, only the interface is different, but I think it the TL code won't be faster than the RTL code. And could you please give me an example of how to define a component at transaction level. thanks a bunch!

Best, Kecheng .

Re: systemverilog interface connects RTL and TML