L6225

DUAL DMOS FULL BRIDGE MOTOR DRIVER

PRELIMINARY DATA
s

OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 2.8A PEAK CURRENT (1.4A DC) RDS (ON) 0.73 TYP. VALUE @ Tj = 25 C CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN OPERATING FREQUENCY UP TO 100KHz HIGH SIDE OVER CURRENT PROTECTION CMOS/TTL INPUT INTRINSIC FAST FREE WHEELING DIODES UNDER VOLTAGE LOCKOUT
transistors with CMOS and bipolar circuits on the same chip. The Logic Inputs are CMOS/TTL and P compatible. The High Side switches are protected against unsafe over current conditions. Each full bridge is controlled by a separate Enable and has a sense pin for the current sense resistor insertion. Another feature is the thermal shutdown. The L6225 is assembled in PowerDIP20(16+2+2), PowerSO20 and SO20(16+2+2) packages.
PowerDIP20 PowerSO20 SO20 (16+2+2) (16+2+2) ORDERING NUMBERS: L6225N L6225PD L6225D

s s s s s s s s s

TYPICAL APPLICATIONS
s s

STEPPER MOTOR DUAL OR QUAD DC MOTOR

DESCRIPTION The L6225 is a dual full bridge driver for motor control applications manufactured with Multipower BCD technology which combines isolated DMOS power

BLOCK DIAGRAM
OUT1A GND GND GND GND ENA ENB IN1A IN2A IN1 B IN2B VBO OT
VS A

SENSE A

OUT2 A
VS A

VS A
VS A

Logic & Drivers

Charg e Pump VCP

VS B VS B VS B

OUT1 B

SENSEB

OUT2 B

VS B

March 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change with out notice.

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L6225
FUNCTIONAL BLOCK DIAGRAM

Vboot
Thermal Protection Voltage Regulator 10V Vboot 5V

VCP
Charge Pump Vboot Vboot

V SA

Over Current Detection

10V 10V

OUT1 A OUT2 A

EN A SENSE A IN1 A IN2 A BRIDGE A BIPOLAR STEPPER MOTOR Logic

EN B IN1 B IN2 B BRIDGE B VSB OUT1B OUT2 B SENSE B

ABSOLUTE MAXIMUM RATINGS

Symbol VS VIN,V EN V SENSE VBOOT IS(peak) Parameter Supply Voltage Input and Enable Voltage Range DC Sensing Voltage Range Bootstrap Peak Voltage Pulsed Supply Current (for each VS pin), internally limited by the overcurrent protection DC Supply Current (for each VS pin) Differential Voltage Between VS A, OUT1A, OUT2A, SENSEA and VS B, OUT1B, OUT2 B, SENSEB Storage and Operating Temperature Range tPULSE < 1ms Test conditio ns Value 60 -0.3 to +7 -1 to +4 V S + 10 3.55 Unit V V V V A

IS VOD

1.4 60

A V

Tstg, TOP

-40 to 150

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L6225
RECOMMENDED OPERATING CONDITIONS
Symbol VS VOD Supply Voltage Differential Voltage Between VS A, OUT1A, OUT2A, SENSEA and VS B, OUT1B, OUT2B, SENSEB Sensing voltage (pulsed tw<trr) (DC) Vref IOUT Tj fsw Vref Operating Voltage DC Output Current Operating Junction Temperature Switching Frequency -25 -6 -1 -0.1 6 1 5 1.4 +125 100 V V V A C kHz Parameter MIN 12 MAX 52 52 Unit V V

V SENSE

PIN CONNECTION (Top View)

IN1A IN2A SENSEA OUT1A GND GND OUT1B SENSEB IN1B IN2B

1 2 3 4 5 6 7 8 9 10
D99IN1093A

20 19 18 17 16 15 14 13 12 11

ENA VCP OUT2A VSA GND GND VSB OUT2B VBOOT ENB
GND VSA OUT2A VCP ENA IN1A IN2A SENSEA OUT1A GND 1 2 3 4 5 6 7 8 9 10
D99IN1092A

20 19 18 17 16 15 14 13 12 11

GND VSB OUT2B VBOOT ENB IN2B IN1B SENSEB OUT1B GND

PowerDIP20/SO20

PowerSO20

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L6225
PIN DESCRIPTION
Name V SA V SB OUT1A OUT2A OUT1B OUT2B SENSE A SENSE B GND EN A
PowerSO20

PowerDIP20/ SO20 17 14 4 18 7 13 3 8 5, 6,15,16 20 Supply Voltage of the Bridge A.

Function

2 19 9 3 12 18 8 13 1,10,11,20 5

Supply Voltage of the Bridge B. This pin must be connected to VSA. Bridge A outputs. Bridge B outputs. Sense resistor for the bridge A Sense resistor for the bridge B Common ground terminals. In Powerdip and SO packages, these pins are also used for heat dissipation toward the PCB. Enable of the Bridge A. A LOW logic level applied to this pin switches off all the power DMOSs of the related bridge. The Bridge A over current protection open drain is internally connected to this pin. Enable of the Bridge B. A LOW logic level applied to this pin switches off all the power DMOSs of the related bridge. The Bridge B over current protection open drain is internally connected to this pin. Logic inputs of the Bridge B. Provided the ENA signal is HIGH, a HIGH logic level applied to any of these pins switches on the related high side power DMOS, while a logic LOW switches on the related low side power DMOS . Logic inputs of the Bridge B. Provided the ENB signal is HIGH, a HIGH logic level applied to any of these pins switches on the related high side power DMOS, while a logic LOW switches on the related low side power DMOS . Bootstrap Oscillator. Oscillator output for the external charge pump. Supply voltage to overdrive the upper DMOSs.

EN B

16

11

IN1 A IN2 A

6 7

1 2

IN1 B IN2 B

14 15

9 10

VCP VBOOT

4 17

19 12

THERMAL DATA
Symbol Rth-j-pins R th-j-case R th-j-amb1 R th-j-amb1 R th-j-amb1 R th-j-amb2 Description MaximumThermal Resistance Junction-Pins Maximum Thermal Resistance Junction-Case MaximumThermal Resistance Junction-Ambient (1) Maximum Thermal Resistance Junction-Ambient (2) MaximumThermal Resistance Junction-Ambient (3) Maximum Thermal Resistance Junction-Ambient (4) PowerDIP20 13 41 57 SO20 15 51 78 PowerSO20 2 36 16 63 Unit C/W C/W C/W C/W C/W C/W

(1) Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm 2 (with a thickness of 35 m). (2) Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m). (3) Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m), 16 via holes and a ground layer. (4) Mounted on a multiplayer PCB without any heatsinking surface on the board.

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L6225
ELECTRICAL CHARACTERISTICS(Tamb = 25 C, Vs = 48V, unless otherwise specified)
Symbol VS IS Tj Parameter Supply Voltage Quiescent Supply Current Thermal Shutdown Temperature All Bridges OFF; -25C<Tj < 125 C 150 Test Conditions Min 8 5.5 Typ Max 52 10 Unit V mA C

Output DMOS Transistors IDSS Leakage Current VS = 52V Tj = 25 C Tj =125 C 1.47 2.35 1 1.69 2.7 mA

R DS(ON) High-side + Low-side Switch ON Resistance Source Drain Diodes VSD trr tfr Forward ON Voltage Reverse Recovery Time Forward Recovery Time

ISD = 1.4A, EN = LOW If = 1.4A 300 200

1.2

V ns ns

Switching Rates tD(on)EN Enable to out turn ON delay time (5) ILOAD = 1.4 A tD(on)IN tON Input to out turn ON delay time (5) Output rise time(5) 20 250 600 105 450 500 20 78 1 0.75 1 300 300 ns ns ns ns ns ns s MHz

tD(off)EN Enable to out turn OFF delay time (5) tD(off)IN toff tdt fCP
Input to out turn OFF delay time (5)

Output fall time (5) Dead time protection Charge pump frequency

UVLO comp V th(ON) Turn ON threshold 6.6 5.6 7 6 7.4 6.4 V V

Vth(OFF) Turn OFF threshold Logic Inpu t V INL VINH IINH IINL Low level logic input voltage High level logic input voltage High level logic input current Low level logic input current VIN, EN = 5 V VIN, EN = GND

-0.3 2

0.8 7 70 -10

V V A A

Over Current Protection IS OVER Input supply over current protection threshold VDIAG Open drain low level output voltage I = 4 mA 2 2.8 3.55 0.4 A V

(5) Resistive load used. See Fig. 1.

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Figure 1. Switching rates definition
En or IN

50 % t

IOUT 90 % 10 %

t
tD(OFF) tOF F t D(ON) t(ON)

CIRCUIT DESCRIPTION
The L6225 is a dual full bridge IC designed to drive DC or stepper motors and other inductive loads. Each bridge has 4 power DMOS transistors with a typical R DS(ON) of 0.3 Ohm. Any of the 4 half bridges can be controlled independently by means of the 4 TTL/CMOS compatible inputs IN1 , IN2A, IN1B, IN2B, and 2 enable ENA, ENB . A External connections are provided so that sensing resistor can be added for constant current chopping applicatio n. A non dissipative current sensing on the supply rails of the high side power DMOSs of each bridge, an internal reference and an internal open drain, with a pull down capability of 4mA (typical value), will pull to GND the ENABLE pin of the bridge under fault conditions, turning OFF all the four PowerDMOSs. This ensures a protection against short circuit to GND and between two phases of each of the two independent full bridges. By using an external R-C on the EN pins, the off time before recovering normal operation conditions after a fault can be easily programmed, by means of the accurate threshold of the logic inputs. Note that protection against short to the supply rail is typically provided by the external current control circuitry. The trip point of this protection is set at 2.8A (typ value).

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DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T

MIN. 0.1 0 0.4 0.23 15.8 9.4 13.9

mm TYP.

MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5

MIN. 0.004 0.000 0.016 0.009 0.622 0.370 0.547

inch TYP.

MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570

OUTLINE AND MECHANICAL DATA

1.27 11.43 10.9 5.8 0 15.5 0.8 11.1 0.429 2.9 6.2 0.228 0.1 0.000 15.9 0.610 1.1 1.1 0.031 10 (max.) 8 (max.) 10

0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043

JEDEC MO-166

0.394

(1) D and F do not include mold flash or protrusions. - Mold flash or protrusions shall not exceed 0.15 mm (0.006). - Critical dimensions: E, G and a3

PowerSO20

N a2 b e A

c DETAIL B a1 E DETAIL A

DETAIL A e3 H

lead

D a3 DETAIL B
20 11
Gage Plane 0.35

slug

- C-

S E2 T E1 BOTTOM VIEW

SEATING PLANE G C

(COPLANARITY)

E3
1 10

h x 45

PSO20MEC

D1

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DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.38 0.51 0.85

mm TYP. MAX. MIN. 0.020 1.40 0.50 0.50 24.80 8.80 2.54 22.86 7.10 5.10 3.30 1.27 0.015 0.033

inch TYP. MAX.

OUTLINE AND MECHANICAL DATA

0.055 0.020 0.020 0.976 0.346 0.100 0.900 0.280 0.201 0.130 0.050

Powerdip 20

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DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4

mm TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 1.27 10.65 0.75 1.27 0.394 0.010 0.016 MIN. 0.093 0.004 0.013 0.009 0.496 0.291

inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.050 0.419 0.030 0.050

OUTLINE AND MECHANICAL DATA

SO20
0 (min.)8 (max.)

h x 45

A B e K H D A1 C

20

11 E

1 0
SO20MEC

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L6225

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:/ /www.st.com

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